ge this by directly reusing condition
check if reused codes are direct:
+ case X86_VENDOR_HYGON:
case X86_VENDOR_AMD:
if (msr >= MSR_F15H_PERF_CTR)
return (msr - MSR_F15H_PERF_CTR) >> 1;
return msr - MSR_K7_PERFCTR0;
Also will branch codes for Hygon in case of complicated checking condition
such as in xen_pmu_arch_init().
Thanks,
Pu Wen
On 2018-07-29 07:42, Paolo Bonzini wrote:
On 23/07/2018 15:20, Pu Wen wrote:
scrubval = scrubrates[i].scrubval;
- if (pvt->fam == 0x17) {
+ if (pvt->fam == 0x17 || pvt->fam == 0x18) {
__f17h_set_scrubval(pvt, scrubval);
} else if (pvt->fam == 0x15 &&
.
For code consistency, will check explicitly for Hygon before testing
family 18h in next patch set.
Thanks,
Pu Wen
Hygon machine check arch is similar to AMD family 17h. To enable the MCE
infrastructure support, add CPU vendor check for Hygon to share the code
path of AMD.
Add hygon mce init function mce_hygon_feature_init() to minimize further
maintenance effort.
Signed-off-by: Pu Wen
---
arch/x86/include
Hygon Dhyana CPU has the SVM feature as AMD family 17h does.
Add Hygon support in the KVM infrastructure.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/kvm_emulate.h | 4
arch/x86/include/asm/virtext.h | 5 +++--
arch/x86/kvm/emulate.c | 11 ++-
3 files changed
Hygon PMU arch is similar to AMD Family 17h. To support Hygon PMU, the
initialization flow for it just call amd_pmu_init() and change PMU name
to "HYGON". To share AMD's flow, add code check for Hygon family ID 18h
to run the code path of AMD family 17h in core/uncore functions.
Signed-
Hygon processors use modern APIC, so just return in modern_apic() and
sync_Arb_IDs(). And should break in switch case in detect_init_API().
When running on 32 bit mode, should set bigsmp if there are more than
8 cores.
Signed-off-by: Pu Wen
---
arch/x86/kernel/apic/apic.c | 19
b_misc_ids[], hygon_nb_link_ids[].
To enable Hygon north bridge support, add new variable root_ids, and
assign its value based on whether CPU vendor is AMD or Hygon. Modify
the CONFIG_AMD_NB to depends on either AMD or Hygon.
Add Hygon support in amd_postcore_init(), early_root_info_init().
Signed-
vulnerability as AMD's,
so add exception in array cpu_no_meltdown[] for Hygon.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/nospec-branch.h | 4 ++--
arch/x86/kernel/cpu/bugs.c | 28 +++-
arch/x86/kernel/cpu/common.c | 1 +
3 files changed, 18 insertions
Hygon Dhyana shares similar perfctr arch with AMD family 17h.
It returns the bit offset of the performance counter register and the
event selection register for Hygon CPU in the similar way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/perfctr-watchdog.c | 2 ++
1 file changed, 2
The ideal_nops for Dhyana processors should be p6_nops.
Signed-off-by: Pu Wen
---
arch/x86/kernel/alternative.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index a481763..8f4925b 100644
--- a/arch/x86/kernel/alternative.c
Tool cpupower is useful to get CPU frequency information and monitor
power stats on Hygon platforms. So enable platform support to cpupower
for Hygon Dhyana Family 18h processors by checking vendor ID and vendor
string.
Signed-off-by: Pu Wen
---
tools/power/cpupower/utils/cpufreq-info.c
is needed for edac driver.
Signed-off-by: Pu Wen
---
drivers/edac/amd64_edac.c | 45 -
drivers/edac/amd64_edac.h | 5 +
drivers/edac/mce_amd.c| 12 +++-
3 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/drivers/edac
Enable ACPI cpufreq driver support for Hygon by adding family ID check
along with AMD.
As Hygon platforms have SMBus device(PCI device ID 0x790b), enable Hygon
support to function amd_freq_sensitivity_init().
Signed-off-by: Pu Wen
---
drivers/cpufreq/acpi-cpufreq.c | 5 +
drivers
For Dhyana processors have NONSTOP TSC feature, so enable the support
to ACPI driver.
Signed-off-by: Pu Wen
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index
a separated Kconfig entry
(CPU_SUP_HYGON) for Dhyana CPU in kernel config setup.
Signed-off-by: Pu Wen
---
MAINTAINERS | 6 +
arch/x86/Kconfig.cpu | 13 ++
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu
().
Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
functions to initialize Dhyana cache info. Setup cache cpumap in
the same way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/cacheinfo.h | 1 +
arch/x86/kernel/cpu/cacheinfo.c | 31
Dhyana use no delay in smp_quirk_init_udelay(), and return in
mwait_play_dead() as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/kernel/smpboot.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index db9656e..32eec7f
RRs, then cleared to 0 for
operation.
The number of variable MTRRs for Hygon is 2 as AMD's.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
arch/x86/kernel/cpu/mtrr/generic.c | 5 +++--
arch/x86/kernel/cpu/mtrr/mtrr.c| 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
d
On 2018/8/14 6:14, Bjorn Helgaas wrote:
On Sat, Aug 11, 2018 at 09:27:42PM +0800, Pu Wen wrote:
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 2950223..d0e98a9 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -511,6 +511,8 @@
#define
On 2018/8/12 3:56, Michael Jin wrote:
On Sat, Aug 11, 2018 at 9:30 AM, Pu Wen wrote:
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 18aeabb..fb81354 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -211,7 +211,7 @@ static int __set_scrub_rate
On 2018/8/12 3:56, Michael Jin wrote:
On Sat, Aug 11, 2018 at 9:30 AM, Pu Wen wrote:
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 18aeabb..fb81354 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -211,7 +211,7 @@ static int __set_scrub_rate
On 2018/8/12 4:10, Michael Jin wrote:
On Sat, Aug 11, 2018 at 3:56 PM, Michael Jin wrote:
On Sat, Aug 11, 2018 at 9:30 AM, Pu Wen wrote:
@@ -1051,6 +1065,16 @@ static void determine_memory_type(struct amd64_pvt *pvt)
else
pvt->dram_type = MEM_D
On 2018/8/12 17:55, Rafael J. Wysocki wrote:
On Sat, Aug 11, 2018 at 3:36 PM Pu Wen wrote:
Enable ACPI cpufreq driver support for Hygon by adding family ID check
along with AMD.
As Hygon platforms have SMBus device(PCI device ID 0x790b), enable Hygon
support to function
On 2018-08-21 16:13, Borislav Petkov wrote:
On Mon, Aug 20, 2018 at 12:14:58AM +0800, Pu Wen wrote:
...
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 18aeabb..3cefb25 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -211,7 +211,8 @@ static
a separated Kconfig entry
(CPU_SUP_HYGON) for Dhyana CPU in kernel config setup.
Signed-off-by: Pu Wen
---
MAINTAINERS | 6 +
arch/x86/Kconfig.cpu | 13 ++
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu
RRs, then cleared to 0 for
operation.
The number of variable MTRRs for Hygon is 2 as AMD's.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
arch/x86/kernel/cpu/mtrr/generic.c | 5 +++--
arch/x86/kernel/cpu/mtrr/mtrr.c| 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
d
().
Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
functions to initialize Dhyana cache info. Setup cache cpumap in
the same way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/cacheinfo.h | 1 +
arch/x86/kernel/cpu/cacheinfo.c | 31
it returns the bit offset of the performance counter register and
event selection register for Hygon CPU in the similar way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/events/amd/core.c | 6 ++
arch/x86/events/amd/uncore.c | 15 ++-
arch/x86/eve
Dhyana use no delay in smp_quirk_init_udelay(), and return in
mwait_play_dead() as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/kernel/smpboot.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index f02ecaf..5369d7f
The ideal_nops for Dhyana processors should be p6_nops.
Signed-off-by: Pu Wen
---
arch/x86/kernel/alternative.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index a481763..8f4925b 100644
--- a/arch/x86/kernel/alternative.c
is needed for edac driver.
Signed-off-by: Pu Wen
---
drivers/edac/amd64_edac.c | 52 ++-
drivers/edac/amd64_edac.h | 5 +
drivers/edac/mce_amd.c| 15 +-
3 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/edac
Hygon Dhyana CPU has the SVM feature as AMD family 17h does.
Add Hygon support in the KVM infrastructure.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/kvm_emulate.h | 4
arch/x86/include/asm/virtext.h | 5 +++--
arch/x86/kvm/emulate.c | 11 ++-
3 files changed
Tool cpupower is useful to get CPU frequency information and monitor
power stats on Hygon platforms. So enable platform support to cpupower
for Hygon Dhyana Family 18h processors by checking vendor ID & family
and vendor string along with AMD.
Signed-off-by: Pu Wen
---
tools/power/cpup
Enable ACPI cpufreq driver support for Hygon by adding family ID check
along with AMD.
As Hygon platforms have SMBus device(PCI device ID 0x790b), enable Hygon
support to function amd_freq_sensitivity_init().
Acked-by: Rafael J. Wysocki
Signed-off-by: Pu Wen
---
drivers/cpufreq/acpi-cpufreq.c
For Dhyana processors have NONSTOP TSC feature, so enable the support
to ACPI driver.
Acked-by: Rafael J. Wysocki
Signed-off-by: Pu Wen
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b/drivers
vulnerability as AMD's,
so add exception in array cpu_no_meltdown[] for Hygon.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/nospec-branch.h | 4 ++--
arch/x86/kernel/cpu/bugs.c | 28 +++-
arch/x86/kernel/cpu/common.c | 1 +
3 files changed, 18 insertions
-by: Bjorn Helgaas# pci_ids.h
Signed-off-by: Pu Wen
---
arch/x86/Kconfig | 2 +-
arch/x86/kernel/amd_nb.c | 51 ++--
arch/x86/pci/amd_bus.c | 6 --
include/linux/pci_ids.h | 2 ++
4 files changed, 52 insertions(+), 9 deletions(-)
Hygon processors use modern APIC, so just return in modern_apic() and
sync_Arb_IDs(). And should break in switch case in detect_init_API().
When running on 32 bit mode, should set bigsmp if there are more than
8 cores.
Signed-off-by: Pu Wen
---
arch/x86/kernel/apic/apic.c | 19
Hygon machine check arch is similar to AMD family 17h. To enable the MCE
infrastructure support, add CPU vendor check for Hygon to share the code
path of AMD.
Add hygon mce init function mce_hygon_feature_init() to minimize further
maintenance effort.
Signed-off-by: Pu Wen
---
arch/x86/include
more clear.
Regards
Pu Wen
, make the assumption clear and try to keep it small.
If that's ok, we will rework this patch.
Thanks for all the suggestions.
Regards,
Pu Wen
-by: Bjorn Helgaas# pci_ids.h
Signed-off-by: Pu Wen
---
arch/x86/Kconfig | 2 +-
arch/x86/kernel/amd_nb.c | 51 ++--
arch/x86/pci/amd_bus.c | 6 --
include/linux/pci_ids.h | 2 ++
4 files changed, 52 insertions(+), 9 deletions(-)
Hygon machine check arch is similar to AMD family 17h. To enable the MCE
infrastructure support, add CPU vendor check for Hygon to share the code
path of AMD.
Add hygon mce init function mce_hygon_feature_init() to minimize further
maintenance effort.
Signed-off-by: Pu Wen
---
arch/x86/include
The ideal_nops for Dhyana processors should be p6_nops.
Signed-off-by: Pu Wen
---
arch/x86/kernel/alternative.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 014f214..3f51d1c 100644
--- a/arch/x86/kernel/alternative.c
Dhyana use no delay in smp_quirk_init_udelay(), and return in
mwait_play_dead() as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/kernel/smpboot.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index f02ecaf..5369d7f
Enable ACPI cpufreq driver support for Hygon by adding family ID check
along with AMD.
As Hygon platforms have SMBus device(PCI device ID 0x790b), enable Hygon
support to function amd_freq_sensitivity_init().
Acked-by: Rafael J. Wysocki
Signed-off-by: Pu Wen
---
drivers/cpufreq/acpi-cpufreq.c
vulnerability as AMD's,
so add exception in array cpu_no_meltdown[] for Hygon.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/nospec-branch.h | 4 ++--
arch/x86/kernel/cpu/bugs.c | 28 +++-
arch/x86/kernel/cpu/common.c | 1 +
3 files changed, 18 insertions
().
Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
functions to initialize Dhyana cache info. Setup cache cpumap in
the same way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/cacheinfo.h | 1 +
arch/x86/kernel/cpu/cacheinfo.c | 31
of kernel Hygon use the lagacy and safe versions of MSR
access. It works fine when VPMU enabled in Xen on Hygon platforms by
testing with perf.
Reviewed-by: Boris Ostrovsky
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git
it returns the bit offset of the performance counter register and
event selection register for Hygon CPU in the similar way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/events/amd/core.c | 6 ++
arch/x86/events/amd/uncore.c | 15 ++-
arch/x86/eve
For Dhyana processors have NONSTOP TSC feature, so enable the support
to ACPI driver.
Acked-by: Rafael J. Wysocki
Signed-off-by: Pu Wen
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b/drivers
Hygon Dhyana CPU has the SVM feature as AMD family 17h does.
Add Hygon support in the KVM infrastructure.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/kvm_emulate.h | 4
arch/x86/include/asm/virtext.h | 5 +++--
arch/x86/kvm/emulate.c | 11 ++-
3 files changed
RRs, then cleared to 0 for
operation.
The number of variable MTRRs for Hygon is 2 as AMD's.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
arch/x86/kernel/cpu/mtrr/generic.c | 5 +++--
arch/x86/kernel/cpu/mtrr/mtrr.c| 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
d
a separated Kconfig entry
(CPU_SUP_HYGON) for Dhyana CPU in kernel config setup.
Signed-off-by: Pu Wen
---
MAINTAINERS | 6 +
arch/x86/Kconfig.cpu | 13 ++
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu
Tool cpupower is useful to get CPU frequency information and monitor
power stats on Hygon platforms. So enable platform support to cpupower
for Hygon Dhyana Family 0x18 processors by checking vendor ID & family
and vendor string by using the code path of AMD family 0x17.
Signed-off-by: Pu
with AMD.
Also Hygon PCI Device ID DF_F0/DF_F6(0x1460/0x1466) of Host bridges
is needed for edac driver.
Signed-off-by: Pu Wen
---
drivers/edac/amd64_edac.c | 20 +++-
drivers/edac/amd64_edac.h | 4
drivers/edac/mce_amd.c| 4 +++-
3 files changed, 26 insertions(+), 2
Hygon processors use modern APIC, so just return in modern_apic() and
sync_Arb_IDs(). And should break in switch case in detect_init_API().
When running on 32 bit mode, should set bigsmp if there are more than
8 cores.
Signed-off-by: Pu Wen
---
arch/x86/kernel/apic/apic.c | 19
vulnerability as AMD's,
so add exception in array cpu_no_meltdown[] for it.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/nospec-branch.h | 4 ++--
arch/x86/kernel/cpu/bugs.c | 28 +++-
arch/x86/kernel/cpu/common.c | 1 +
3 files changed, 18 insertions(+), 15
On 2018-08-30 03:35, Andi Kleen wrote:
Pu Wen writes:
Add x86 architecture support for new processor Hygon Dhyana Family 18h.
Rework to create a separated file(arch/x86/kernel/cpu/hygon.c) from the
AMD init one(arch/x86/kernel/cpu/amd.c) to initialize Dhyana CPU.
Standard approach would
On 2018-08-30 20:35, Borislav Petkov wrote:
+HYGON PROCESSOR SUPPORT
+M: Pu Wen
+L: linux-a...@vger.kernel.org
This is probably the wrong ML. You either have your own or use lkml,
I'd say.
That's all right, I'll use linux-kernel@vger.kernel.org instead.
+++ b/arch/x86/kernel/cpu
On 2018/9/5 2:33, Borislav Petkov wrote:
On Wed, Aug 29, 2018 at 08:44:30PM +0800, Pu Wen wrote:
...
+ if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+boot_cpu_data.x86 >= 0xf) ||
+boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
return
On 2018/9/5 21:15, Borislav Petkov wrote:
On Wed, Sep 05, 2018 at 08:59:24PM +0800, Pu Wen wrote:
If CONFIG_X86_MCE_AMD=n, mce_hygon_feature_init will call the other
one mce_amd_feature_init which is a null function and located in the
else branch of "#ifdef CONFIG_X86_MCE_AMD". The c
On 2018/9/4 18:48, Borislav Petkov wrote:
On Wed, Aug 29, 2018 at 08:43:54PM +0800, Pu Wen wrote:
Hygon PMU arch is similar to AMD Family 17h. To support Hygon PMU, the
initialization flow for it just call amd_pmu_init() and change PMU name
That sentence reads funny.
Will rewrite
PCI_DEVICE_ID_HYGON_18H_DF_F30x1463
+#define PCI_DEVICE_ID_HYGON_18H_DF_F40x1464
Why are you adding those if you can use the AMD f17h ones? They're
the same.
I add these definitions to indicate that there are Hygon PCI device IDs.
You are right, I can just use the AMD f17h ones here.
--
Regards,
Pu Wen
On 2018/9/6 16:39, Borislav Petkov wrote:
> On Thu, Sep 06, 2018 at 11:52:42AM +0800, Pu Wen wrote:
>> In most of the normal use cases MCE is necessary. Rarely in some cases
>> such as for test purpose MCE may be unselected.
>
> Test with MCE disabled? Please
for CPU_SUP_HYGON to solve the
dependency issues in kernel.
--
Regards,
Pu Wen
to it in find_num_cache_leaves().
Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
functions to initialize Dhyana cache info. Setup cache cpumap in
the same way as AMD does.
Reviewed-by: Borislav Petkov
Signed-off-by: Pu Wen
---
arch/x86/include/asm/cacheinfo.h | 1 +
arch/x86/kernel
(CPU_SUP_HYGON) in kernel config setup. And select CPU_SUP_AMD
to solve the dependency issues in kernel.
Signed-off-by: Pu Wen
---
MAINTAINERS | 6 +
arch/x86/Kconfig.cpu | 14 ++
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1
t.
- Split the patchset to small series of patches.
- Rework patch descriptions.
- Create a separated arch/x86/kernel/cpu/hygon.c for Dhyana CPU
initialization to reduce long-term maintenance effort.
Pu Wen (16):
x86/cpu: Create Hygon Dhyana architecture support file
x86/cpu: Get cache in
The Hygon Dhyana CPU have a special magic MSR way to force WB for
memory >4GB, and support TOP_MEM2. Therefore, it is necessary to
add Hygon Dhyana support in amd_special_default_mtrr().
The number of variable MTRRs for Hygon is 2 as AMD's.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/m
The ideal_nops for Hygon Dhyana CPU should be p6_nops.
Reviewed-by: Borislav Petkov
Signed-off-by: Pu Wen
---
arch/x86/kernel/alternative.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index b9d5e7c..184e9a0 100644
Signed-off-by: Pu Wen
---
arch/x86/kernel/amd_nb.c | 47 +--
arch/x86/pci/amd_bus.c | 6 --
include/linux/pci_ids.h | 2 ++
3 files changed, 47 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index
Add Hygon Dhyana support to the APIC subsystem as it use modern APIC.
When running on 32 bit mode, bigsmp should be enabled if there are
more than 8 cores online.
Signed-off-by: Pu Wen
---
arch/x86/kernel/apic/apic.c | 13 +++--
arch/x86/kernel/apic/probe_32.c | 1 +
2 files
The Hygon Dhyana CPU use no delay in smp_quirk_init_udelay(),
and return in mwait_play_dead() as AMD does.
Reviewed-by: Borislav Petkov
Signed-off-by: Pu Wen
---
arch/x86/kernel/smpboot.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/smpboot.c b/arch
registers and event selection registers), so add Hygon Dhyana
support to get bit offset in the similar way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/events/amd/core.c | 4
arch/x86/events/amd/uncore.c | 20 +---
arch/x86/events/core.c
The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. To make MCE working on Hygon platforms, add vendor
checking for Hygon Dhyana to share the code path of AMD family 17h.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/mce.h| 2 ++
arch/x86
The Hygon Dhyana CPU has the same speculative execution as AMD family
17h, so share AMD spectre mitigation code for Hygon Dhyana.
Also Hygon Dhyana is not affected by meltdown vulnerability as AMD,
so add the exception for Hygon Dhyana.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/bugs.c
The Hygon Dhyana CPU has the SVM feature as AMD family 17h does.
So enable the KVM infrastructure support to it.
Reviewed-by: Borislav Petkov
Signed-off-by: Pu Wen
---
arch/x86/include/asm/kvm_emulate.h | 4
arch/x86/include/asm/virtext.h | 5 +++--
arch/x86/kvm/emulate.c
The Hygon Dhyana CPU has NONSTOP TSC feature, so enable the ACPI
driver support to it.
Acked-by: Rafael J. Wysocki
Signed-off-by: Pu Wen
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b
Tool cpupower is useful to get CPU frequency information and monitor
power stats on Hygon Dhyana platforms. So add Hygon Dhyana support to
it by checking vendor and family to share the code path of AMD family
17h.
Signed-off-by: Pu Wen
---
tools/power/cpupower/utils/cpufreq-info.c
To make AMD64 EDAC and MCE drivers working on Hygon platforms, add
support for Hygon Dhyana CPU by using the code path of AMD family
17h.
Signed-off-by: Pu Wen
---
drivers/edac/amd64_edac.c | 8 +++-
drivers/edac/mce_amd.c| 4 +++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff
As the Hygon Dhyana CPU support ACPI P-States feature, and there is
SMBus device(PCI device ID 0x790b) on Hygon platform, so add Hygon
Dhyana support to the cpufreq driver by using the code path of AMD
family 17h.
Acked-by: Rafael J. Wysocki
Signed-off-by: Pu Wen
---
drivers/cpufreq/acpi
fixed. So the workaround is not
needed for Hygon Dhyana platforms any more, and the vendor checking
for Hygon will be removed in next version of patch.
Thanks,
Pu Wen
on of the vendor tests. The
other stuff you can drop.
That's reasonable. To avoid the confusion, will only leave the vendor
testing for Hygon and drop the other changes, which also minimize the
code modification.
--
Regards,
Pu Wen
--
Regards,
Pu Wen
efine PCI_DEVICE_ID_HYGON_18H_DF_F0 0x1460
>> +#define PCI_DEVICE_ID_HYGON_18H_DF_F6 0x1466
>
> As in the previous patch - use the AMD defines.
Will remove them in next version of patches.
--
Regards,
Pu Wen
On 2018/9/11 2:06, Borislav Petkov wrote:
On Mon, Sep 10, 2018 at 09:16:03PM +0800, Pu Wen wrote:
The Hygon Dhyana CPU have a special magic MSR way to force WB for
From the last review round:
Also, it is "The ... CPU has a special..."
Please take your time and incorporate *a
rds are used with the tendency to explain what the patch do,
actually they are not needed and will be removed.
--
Regards,
Pu Wen
vides that functionality."
Thanks for the detailed correction. Will improve the description and
remove unneeded sentences in next version of patch.
--
Regards,
Pu Wen
MD. Switching to AUTO
select\n");
+ pr_err("retpoline,amd selected but CPU is not AMD or Hygon.
Switching to AUTO select\n");
Didn't we say, no user-visible changes pls?
Sorry for the incomplete modification. Will revert the pr_err string.
--
Regards,
Pu Wen
Dhyana CPU always uses modern APIC,
so the function modern_apic will always return true for Hygon Dhyana.
I will remove this change in next version of patch.
With it removed:
Reviewed-by: Borislav Petkov
--
Regards,
Pu Wen
into an endless loop.
To fix this problem, add a new enum type CTYPE_MAX to limit the maximum
cpuid accessing.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/cacheinfo.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu
The tool perf is useful for the performance analysis on the Hygon Dhyana
platform. But right now there is no Hygon support for it to analyze the
KVM guest os data. So add Hygon Dhyana support to it by checking vendor
string to share the code path of AMD.
Signed-off-by: Pu Wen
---
tools/perf
The tool perf is useful for the performance analysis on the Hygon Dhyana
platform. But right now there is no Hygon support for it to analyze the
KVM guest os data. So add Hygon Dhyana support to it by checking vendor
string to share the code path of AMD.
Signed-off-by: Pu Wen
---
tools/perf
Tool cpupower is useful to get CPU frequency information and monitor
power stats on Hygon Dhyana platform. So add Hygon Dhyana support to
it by checking vendor and family to share the code path of AMD family
17h.
Signed-off-by: Pu Wen
Acked-by: Shuah Khan (Samsung OSG)
---
tools/power/cpupower
support
"With this bit, the kernel..."
Dhyana also find num_cache_leaves via CPUID leaf 0x801d, so
"... also discovers num_cache_leaves ..."
Thanks for the correction.
Regards,
Pu Wen
With that:
Reviewed-by: Borislav Petkov
p;
+ !(boot_cpu_data.x86_vendor == X86_VENDOR_HYGON))
or:
+ if ((boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+boot_cpu_data.x86 < 0x0f) &&
+ (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON))
Which statement is better?
Thanks,
Pu Wen
gt; this email
I cannot reproduce this panic on Hygon Dhyana platform. I tired lkp-tests
both in Ubuntu 16.04 (with gcc-5) and Ubuntu 18.04 (with gcc-7).
What kind of host do you use to run the qemu? A Intel one or AMD one?
Thanks,
Pu Wen
ds;
The PANIC will be eliminated.
The PANIC will also be eliminated by adding AMD vendor checking in
amd_gart_present:
+ if(boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+ return false;
To prevent the function return true on non AMD platform.
Thanks,
Pu Wen
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