On 2014/5/4 19:37, Zhou Wang wrote:
On 2014/4/23 19:51, Zhou Wang wrote:
set ARCH_NR_GPIO for Hisilicon Soc hip04, which has 4 GPIO
controllers with 32 GPIOs each.
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
---
arch/arm/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git
On 2014/4/23 19:51, Zhou Wang wrote:
set ARCH_NR_GPIO for Hisilicon Soc hip04, which has 4 GPIO
controllers with 32 GPIOs each.
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
---
arch/arm/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm
On 2014/4/23 19:51, Zhou Wang wrote:
Hisilicon Soc hip04 has four gpio controllers, each one has 32
gpios and can be configured to be an interrupt controller.
The gpio controllers are compatible with the snps,dw-apb-gpio
driver. This patch add the corresponding device tree nodes.
Signed-off
This series add the support for the GPIOs of Hisilicon Soc hip04. We use
the dwapb GPIO driver here.
The second patch is based on hip04.dtsi[1] which is upstreaming now.
[1] http://article.gmane.org/gmane.linux.ports.arm.kernel/317491
Zhou Wang (2):
ARM: hip04: set ARCH_NR_GPIO to 128
ARM
set ARCH_NR_GPIO for Hisilicon Soc hip04, which has 4 GPIO
controllers with 32 GPIOs each.
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
---
arch/arm/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2961627..bb00e65 100644
--- a/arch/arm
Hisilicon Soc hip04 has four gpio controllers, each one has 32
gpios and can be configured to be an interrupt controller.
The gpio controllers are compatible with the snps,dw-apb-gpio
driver. This patch add the corresponding device tree nodes.
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
On 2014年07月09日 15:08, Jerome FORISSIER wrote:
On 30-Jun-14 10:03, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm
On 2014年07月15日 18:58, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 836 ++
3 files changed, 842 insertions
On 2014年07月15日 18:58, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi-nand.txt | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt
Hi Randy
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index abb42ca..e63fc61 100644
--- a/arch/arm/boot/dts/hip04.dtsi
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 847 ++
3 files changed, 853 insertions(+)
create mode 100644 drivers/mtd/nand/hisi_nand.c
tested it on hisilicon hip04-d01
board.
[1] ssh://g...@git.linaro.org/landing-teams/working/hisilicon/kernel.git
Zhou Wang (3):
mtd: hisilicon: add device tree node for nand controller
mtd: hisilicon: add a new nand controller driver for hisilicon hip04
Soc
mtd: hisilicon: add device
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi-nand.txt | 38
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/hisi
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 681267a..6ff48eb 100644
--- a/arch/arm/boot/dts/hip04.dtsi
mtd_info in
struct hinfc_host directly.
- rewrite some unclear lines in device tree binding document, correct some
code style error.
[1] ssh://g...@git.linaro.org/landing-teams/working/hisilicon/kernel.git
Zhou Wang (3):
mtd: hisilicon: add device tree node for nand controller
mtd: hisilicon
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 836 ++
3 files changed, 842 insertions(+)
create mode 100644 drivers/mtd/nand/hisi_nand.c
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi-nand.txt | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/hisi
On 2014年06月30日 17:00, Arnd Bergmann wrote:
Overall a very nice driver. I didn't find any real bugs, but a few things
that could be changed for readability and micro-optimizations:
On Monday 30 June 2014 16:03:28 Zhou Wang wrote:
+#define hinfc_read(_host, _reg)readl(_host-iobase
On 2014年06月30日 17:45, Ivan Khoronzhuk wrote:
On 06/30/2014 11:03 AM, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 847
Zhou Wang (2):
mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc
mtd: hisilicon: add device tree binding documentation
.../devicetree/bindings/mtd/hisi504-nand.txt | 40 +
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig|5 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/hisi504_nand.c | 836 +++
3 files changed, 842 insertions(+)
create mode 100644 drivers/mtd/nand
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi504-nand.txt | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd
On 2014年10月24日 19:46, Haojian Zhuang wrote:
On Thu, Oct 23, 2014 at 10:04 PM, Zhou Wang wangzhou@gmail.com wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig|5 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/hisi504_nand.c
Hisilicon Soc hip04 has four GPIO controllers, each one has 32
GPIOs and can be configured to be an interrupt controller.The GPIO
controllers are compatible with the snps,dw-apb-gpio driver.
This patch add the corresponding device tree nodes.
Signed-off-by: Zhou Wang wangzhou@gmail.com
Set ARCH_NR_GPIO for Hisilicon Soc Hip04, which has 4 GPIO
controllers with 32 GPIOs each.
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
arch/arm/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 89c4b5c..26aae1e 100644
--- a/arch/arm
This series add the support for the GPIOs of Hisilicon Soc hip04. Hip04 uses
synopsis' GPIO IP, and we use the dwapb GPIO driver here. This series add the
corresponding dts.
As the hip04 basic dts has been merged in 3.18 mainline kernel, I just resend
this patchset for review.
Zhou Wang (2
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig|5 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/hisi504_nand.c | 845 +++
3 files changed, 851 insertions(+)
create mode 100644 drivers/mtd/nand
.
- rewrite some unclear lines in device tree binding document, correct some
code style error.
Link on v2:
- https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg750071.html
Link on v1:
- https://lkml.org/lkml/2014/7/15/198
Zhou Wang (2):
mtd: hisilicon: add a new NAND controller driver
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi504-nand.txt | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd
On 2014年10月28日 22:22, Frans Klaver wrote:
On Tue, Oct 28, 2014 at 11:53 AM, Zhou Wang wangzhou@gmail.com wrote:
+
+static int hisi_nfc_probe(struct platform_device *pdev)
+{
+ int ret = 0, irq, buswidth, flag, max_chips = HINFC504_MAX_CHIP;
+ struct device *dev = pdev-dev
.html
Link on v1:
- https://lkml.org/lkml/2014/7/15/198
Zhou Wang (2):
mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc
mtd: hisilicon: add device tree binding documentation
.../devicetree/bindings/mtd/hisi504-nand.txt | 40 +
drivers/mtd/nand/Kconfig
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig|5 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/hisi504_nand.c | 846 +++
3 files changed, 852 insertions(+)
create mode 100644 drivers/mtd/nand
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi504-nand.txt | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd
On 2014年11月30日 17:08, Brian Norris wrote:
On Tue, Nov 04, 2014 at 08:46:59PM +0800, Zhou Wang wrote:
This patchset adds the support for NAND controller of hisilicon hip04 Soc.
The NAND controller IP was developed by hisilicon and needs a new driver to
support it. This patchset is based on v3.18
On 2014年11月30日 16:56, Brian Norris wrote:
On Tue, Nov 04, 2014 at 08:47:01PM +0800, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi504-nand.txt | 40
1 file changed, 40 insertions(+)
create mode 100644
On 2014年11月30日 17:35, Brian Norris wrote:
On Tue, Nov 04, 2014 at 08:47:00PM +0800, Zhou Wang wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
This driver mostly looks good. A few comments.
---
drivers/mtd/nand/Kconfig|5 +
drivers/mtd/nand/Makefile |1
On 2014年12月01日 17:25, Brian Norris wrote:
I forgot to mention these comments:
On Tue, Nov 04, 2014 at 08:47:00PM +0800, Zhou Wang wrote:
+static int hisi_nfc_remove(struct platform_device *pdev)
+{
+ struct hinfc_host *host = platform_get_drvdata(pdev);
+ struct mtd_info *mtd
On 2014年11月30日 17:01, Brian Norris wrote:
One more thing:
On Tue, Nov 04, 2014 at 08:47:01PM +0800, Zhou Wang wrote:
diff --git a/Documentation/devicetree/bindings/mtd/hisi504-nand.txt
b/Documentation/devicetree/bindings/mtd/hisi504-nand.txt
new file mode 100644
index 000..c8b3988
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
---
.../bindings/arm/hisilicon/hisilicon.txt | 17 +
.../devicetree/bindings/pci/hisilicon-pcie.txt | 44 ++
2 files c
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: liudongdong <liudongdo...@huawei.com>
---
drivers/pci/host/Kconfig | 8 ++
drivers
This patch reverts commit f4c55c5a3f7f ("PCI: designware: Program ATU with
untranslated address") based on 1/8 in this series. we delete *_mod_base in
pcie-designware. This was discussed in [1]
[1] http://www.spinics.net/lists/arm-kernel/msg436779.html
Signed-off-by: Zhou Wa
This patch uses the new of_pci_get_host_bridge_resources
API in place of the PCI OF DT parser
For reference see previous suggestions from Gabriele[1]
[1] http://www.spinics.net/lists/linux-pci/msg42194.html
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele P
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabr
rt*" pointer.
This patch solves the issue by removing "align_resource" from "pci_sys_data"
struct and defining a static global function pointer in "bios32.c"
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Zhou Wang <wangzh...
for every designware user even if is only
applicable to DRA7xx.
This patch moves the calculation of the bus addresses to the DRA7xx
driver and is needed to allow the rework of designware to use
the new DT parsing API.
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
s.infradead.org/pipermail/linux-arm-kernel/2015-July/359741.html
Zhou Wang (6):
PCI: designware: Replace DT PCI ranges parse with
of_pci_get_host_bridge_resources
PCI: designware: Add ARM64 support
PCI: designware: Remove *_mod_base
PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05
Do
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..944a229 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8047,6 +8047,13 @@ S: Maintained
F: Documentation/devi
On 2015/10/23 2:46, Bjorn Helgaas wrote:
> Hi Zhou,
>
> This looks pretty good to me; just a mask question and add a printk.
>
> On Fri, Oct 16, 2015 at 06:23:39PM +0800, Zhou Wang wrote:
>> This patch adds PCIe host support for HiSilicon SoC Hip05.
On 2015/10/23 0:35, Bjorn Helgaas wrote:
> Hi Gabriele,
>
> On Thu, Oct 22, 2015 at 07:21:41AM +, Gabriele Paoloni wrote:
>>> -Original Message-
>>> From: Bjorn Helgaas [mailto:helg...@kernel.org]
>
#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
#define
On 2015/10/23 2:28, Bjorn Helgaas wrote:
> Hi Zhou,
>
> On Fri, Oct 16, 2015 at 06:23:38PM +0800, Zhou Wang wrote:
>> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
>> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw
On 2015/10/28 3:19, Rob Herring wrote:
> On Mon, Oct 26, 2015 at 6:35 AM, Zhou Wang <wangzh...@hisilicon.com> wrote:
>> This patch adds related DTS binding document for HiSilicon PCIe host driver.
>>
>> Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
>
>
On 2015/10/28 6:32, Bjorn Helgaas wrote:
> Hi Zhou,
>
> On Mon, Oct 26, 2015 at 07:35:42PM +0800, Zhou Wang wrote:
>> This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
>> use PCIe IP core from Synopsys, So this driver is based on designware PCIe
&
for every designware user even if is only
applicable to DRA7xx.
This patch moves the calculation of the bus addresses to the DRA7xx
driver and is needed to allow the rework of designware to use
the new DT parsing API.
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
er-host bridge
align_resource() methods), but the pci_sys_data->align_resource pointer was
used only by Marvell (see mvebu_pcie_enable()), so this would only be a
problem if we had a system with a combination of Marvell and other host
bridges
[bhelgaas: changelog]
Signed-off-by: Gabriele Paoloni <gab
779.html
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Arnd Bergmann <a...@arndb.de>
Tested-by: James Morse <james.mo...@arm.com>
Tested-by: Gabriel Fernandez <gabriel.fernan...@st.com>
Tes
This patch uses the new of_pci_get_host_bridge_resources
API in place of the PCI OF DT parser
For reference see previous suggestions from Gabriele[1]
[1] http://www.spinics.net/lists/linux-pci/msg42194.html
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele P
42539.html
Link of v2:
- http://www.spinics.net/lists/linux-pci/msg41844.html
Link of RFC v1:
- http://www.spinics.net/lists/linux-pci/msg41305.html
Link of RFC:
- http://www.spinics.net/lists/linux-pci/msg40434.html
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/359741.htm
nware: Remove *_mod_base".
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Arnd Bergmann <a...@arndb.de>
Tested-by: James Morse <james.mo...@arm.com>
Tested-by: Gabriel Fernandez <gabriel.
This patch adds PCIe host support for HiSilicon SoC Hip05, related DT binding
document and maintainer update.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: liudongdong <liudongdo...@huawei.com>
Ack
n.
>
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
>
Hi Arnd,
Many thanks, it looks good to me. so
Acked-by: Zhou Wang <wangzh...@hisilicon.com>
Regards,
Zhou
> diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
> index 35457ecd8e70..163671a4f798 10064
On 2015/10/15 5:56, Arnd Bergmann wrote:
> On Wednesday 14 October 2015 17:44:11 Zhou Wang wrote:
>> On 2015/10/14 17:06, Arnd Bergmann wrote:
>>> On Wednesday 14 October 2015 16:59:03 Zhou Wang wrote:
>>>>
>>>> Hi Arnd,
>>>>
>>>>
On 2015/10/13 23:00, Arnd Bergmann wrote:
> On Tuesday 13 October 2015 14:49:07 Gabriele Paoloni wrote:
>>> On Monday 12 October 2015 16:35:45 Bjorn Helgaas wrote:
> +{
> + u64 addr;
> + struct device_node *msi_node;
> + struct resource res;
> + struct
On 2015/10/14 17:06, Arnd Bergmann wrote:
> On Wednesday 14 October 2015 16:59:03 Zhou Wang wrote:
>>
>> Hi Arnd,
>>
>> In Hip05 PCIe host, it uses GITS_TRANSLATER's address to get TLP package
>> which contains MSI address and MSI data, and then combine BDF and M
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: liudongdong <liudongdo...@huawei.com>
---
drivers/pci/host/Kconfig | 8 ++
drivers
for every designware user even if is only
applicable to DRA7xx.
This patch moves the calculation of the bus addresses to the DRA7xx
driver and is needed to allow the rework of designware to use
the new DT parsing API.
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..944a229 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8047,6 +8047,13 @@ S: Maintained
F: Documentation/devi
rt*" pointer.
This patch solves the issue by removing "align_resource" from "pci_sys_data"
struct and defining a static global function pointer in "bios32.c"
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Zhou Wang <wangzh...
of RFC:
- http://www.spinics.net/lists/linux-pci/msg40434.html
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/359741.html
Zhou Wang (4):
PCI: designware: Add ARM64 support
PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05
Documentation: DT: Add HiSilicon PCIe host bindin
don't have
ARM32 PCIe related board to do test. It will be appreciated if someone could
help to test it.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Arnd Bergmann <a...@arndb.de>
Tested-by: James Morse
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
---
.../bindings/arm/hisilicon/hisilicon.txt | 17 +
.../devicetree/bindings/pci/hisilicon-pcie.txt | 44 ++
2 files c
On 2015/10/13 5:35, Bjorn Helgaas wrote:
> [+cc Arnd, Rob]
>
> Hi Zhou,
>
> I have a few minor comments and two questions: one about the fact
> all the config accesses are 32 bits, and another about the use of the
> "msi-parent" node.
>
> On Sat, Oct 10
don't have
ARM32 PCIe related board to do test. It will be appreciated if someone could
help to test it.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Arnd Bergmann <a...@arndb.de>
Tested-by: James Morse
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..944a229 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8047,6 +8047,13 @@ S: Maintained
F: Documentation/devi
for every designware user even if is only
applicable to DRA7xx.
This patch moves the calculation of the bus addresses to the DRA7xx
driver and is needed to allow the rework of designware to use
the new DT parsing API.
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
rt*" pointer.
This patch solves the issue by removing "align_resource" from "pci_sys_data"
struct and defining a static global function pointer in "bios32.c"
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Zhou Wang <wangzh...
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: liudongdong <liudongdo...@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.w...@h
net/lists/linux-pci/msg41305.html
Link of RFC:
- http://www.spinics.net/lists/linux-pci/msg40434.html
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/359741.html
Zhou Wang (4):
PCI: designware: Add ARM64 support
PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05
Do
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
---
.../bindings/arm/hisilicon/hisilicon.txt | 17 +
.../devicetree/bindings/pci/hisilicon-pcie.txt | 44 ++
2 files c
On 2017/1/10 5:45, Rafael J. Wysocki wrote:
> On Mon, Jan 9, 2017 at 4:39 AM, Zhou Wang <wangzh...@hisilicon.com> wrote:
>> On 2017/1/4 15:00, Zhou Wang wrote:
>>> The configuration data provided by an MCFG region (ie PCI segment and
>>> bus range) may span multi
On 2017/1/12 5:37, Bjorn Helgaas wrote:
> On Wed, Jan 04, 2017 at 03:00:06PM +0800, Zhou Wang wrote:
>> The configuration data provided by an MCFG region (ie PCI segment and
>> bus range) may span multiple host bridges.
>>
>> Current code in pci_mcfg_lookup() carries
On 2017/1/3 14:39, Tomasz Nowicki wrote:
> On 22.12.2016 10:07, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segment.
>>
>>
On 2017/1/3 20:00, Lorenzo Pieralisi wrote:
> On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segm
On 2016/12/22 17:07, Zhou Wang wrote:
> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
> each
> host bridge should be in the coverage of bus range of related PCIe segment.
>
> This patch will support this kind of scenario:
>
> MCFG:
>
.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
Reviewed-by: Tomasz Nowicki <t...@semihalf.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieral...@arm.com>
---
drivers/acpi/pci_mcfg.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/pci_mcf
On 2017/1/4 15:00, Zhou Wang wrote:
> The configuration data provided by an MCFG region (ie PCI segment and
> bus range) may span multiple host bridges.
>
> Current code in pci_mcfg_lookup() carries out an exact match of host
> bridge bus range start value against the MCFG regi
:
bus range: 0x00~0x1f.
segment: 0.
host bridge 2:
bus range: 0x20~0x4f.
segment: 0.
Signed-off-by: Zhou Wang <wangzh...@hisilicon.com>
---
drivers/acpi/pci_mcfg.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
On 2017/3/21 23:48, Jingoo Han wrote:
> (+cc: Joao Pinto, Zhou Wang, Gabriele Paoloni)
>
> On Tuesday, March 21, 2017 10:32 AM, Arnd Bergmann wrote:
>>
>> Without PCI_HOST_COMMON support enabled, we get a link error:
>>
>> drivers/pci/dwc/built-in.o: In func
On 2017/3/22 16:00, Arnd Bergmann wrote:
> On Mar 22, 2017 04:27, "Zhou Wang" <wangzh...@hisilicon.com
> <mailto:wangzh...@hisilicon.com>> wrote:
>
> On 2017/3/21 23:48, Jingoo Han wrote:
> > (+cc: Joao Pinto, Zhou Wang, Gabriele Paoloni)
>
On 2017/4/26 18:06, Lorenzo Pieralisi wrote:
> The introduction of pci_bus_find_numa_node(pci_bus) allows at PCI
> host bridge registration to detect the NUMA node for a given
> struct pci_bus.dev. Implement an ACPI method that, through
> the struct pci_bus.bridge ACPI companion, retrieve and
On 2017/5/15 17:17, Lorenzo Pieralisi wrote:
> On Mon, May 15, 2017 at 02:13:47PM +0800, Zhou Wang wrote:
>> On 2017/4/26 18:06, Lorenzo Pieralisi wrote:
>>> The introduction of pci_bus_find_numa_node(pci_bus) allows at PCI
>>> host bridge registration to detec
On 2014年07月09日 15:08, Jerome FORISSIER wrote:
On 30-Jun-14 10:03, Zhou Wang wrote:
Signed-off-by: Zhou Wang
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
On 2014年06月30日 17:00, Arnd Bergmann wrote:
Overall a very nice driver. I didn't find any real bugs, but a few things
that could be changed for readability and micro-optimizations:
On Monday 30 June 2014 16:03:28 Zhou Wang wrote:
+#define hinfc_read(_host, _reg)readl(_host->iob
On 2014年06月30日 17:45, Ivan Khoronzhuk wrote:
On 06/30/2014 11:03 AM, Zhou Wang wrote:
Signed-off-by: Zhou Wang
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 847
++
3 files changed
Signed-off-by: Zhou Wang
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index abb42ca..e63fc61 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts
Signed-off-by: Zhou Wang
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 847 ++
3 files changed, 853 insertions(+)
create mode 100644 drivers/mtd/nand/hisi_nand.c
diff --git a/drivers/mtd
tested it on hisilicon hip04-d01
board.
[1] ssh://g...@git.linaro.org/landing-teams/working/hisilicon/kernel.git
Zhou Wang (3):
mtd: hisilicon: add device tree node for nand controller
mtd: hisilicon: add a new nand controller driver for hisilicon hip04
Soc
mtd: hisilicon: add device
Signed-off-by: Zhou Wang
---
.../devicetree/bindings/mtd/hisi-nand.txt | 38
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/hisi-nand.txt
b/Documentation
Signed-off-by: Zhou Wang
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 681267a..6ff48eb 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts
mtd_info in
struct hinfc_host directly.
- rewrite some unclear lines in device tree binding document, correct some
code style error.
[1] ssh://g...@git.linaro.org/landing-teams/working/hisilicon/kernel.git
Zhou Wang (3):
mtd: hisilicon: add device tree node for nand controller
mtd: hisilicon
Signed-off-by: Zhou Wang
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 836 ++
3 files changed, 842 insertions(+)
create mode 100644 drivers/mtd/nand/hisi_nand.c
diff --git a/drivers/mtd
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