Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate

[Heiko Stuebner]

Am Dienstag, 13. März 2018, 21:37:19 CET schrieb Derek Basehore:
> We need this rate to generate 100, 200, and 228.57MHz from the same
> PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
> and external display.
> 
> Signed-off-by: Derek Basehore 

applied for 4.17

Thanks
Heiko

Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate

[Doug Anderson]

Hi,

On Tue, Mar 13, 2018 at 1:37 PM, Derek Basehore  wrote:
> We need this rate to generate 100, 200, and 228.57MHz from the same
> PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
> and external display.
>
> Signed-off-by: Derek Basehore 
> ---
>  drivers/clk/rockchip/clk-rk3399.c | 1 +
>  1 file changed, 1 insertion(+)

Looks good to me.  I spent a little bit of time poking at this and I
agreed it's the best way to make 1.6 GHz in
.  Lin Huang at Rockchip also said:

> yes, we also use this setting for 1.6GHz in our internal branch.

...and they seem to agree this is a sane setting.  Thus:

Reviewed-by: Douglas Anderson 

[PATCH] clk: rockchip: Add 1.6GHz PLL rate

[Derek Basehore]

We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
and external display.

Signed-off-by: Derek Basehore 
---
 drivers/clk/rockchip/clk-rk3399.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 6847120b61cd..3e57c6eef93d 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE(165600, 1, 69, 1, 1, 1, 0),
RK3036_PLL_RATE(163200, 1, 68, 1, 1, 1, 0),
RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+   RK3036_PLL_RATE(16, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
-- 
2.16.2.660.g709887971b-goog