Re: [PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
On Sun, 2018-03-18 at 07:48 -0500, Rob Herring wrote: > On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote: > > Add two properties of ref_clk and coefficient used by U2 slew rate > > calibrate which may vary on different SoCs > > > > Signed-off-by: Chunfeng Yun > > --- > > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > index 41e09ed..0d34b2b 100644 > > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > > - reg : offset and length of register shared by multiple > > ports, > > exclude port's private register. It is needed on mt2701 > > and mt8173, but not on mt2712. > > + - mediatek,src-ref-clk-mhz: frequency of reference clock for slew > > rate > > + calibrate > > + - mediatek,src-coef : coefficient for slew rate calibrate, depends > > on > > + SoC process > > What are valid values? This is one cell? Yes, one cell, integer type. If need, I'll send a new patch Thanks > > > > > Required properties (port (child) node): > > - reg : address and length of the register set for the port. > > -- > > 1.9.1 > >
Re: [PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote: > Add two properties of ref_clk and coefficient used by U2 slew rate > calibrate which may vary on different SoCs > > Signed-off-by: Chunfeng Yun > --- > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > index 41e09ed..0d34b2b 100644 > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > - reg : offset and length of register shared by multiple > ports, > exclude port's private register. It is needed on mt2701 > and mt8173, but not on mt2712. > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate > + calibrate > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on > + SoC process What are valid values? This is one cell? > > Required properties (port (child) node): > - reg: address and length of the register set for the port. > -- > 1.9.1 >
Re: [PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
On Wed, 2018-03-14 at 00:21 +0100, Matthias Brugger wrote: > > On 03/12/2018 06:25 AM, Chunfeng Yun wrote: > > Add two properties of ref_clk and coefficient used by U2 slew rate > > calibrate which may vary on different SoCs > > > > Signed-off-by: Chunfeng Yun > > Reviewed-by: Matthias Brugger > Thanks again > > --- > > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > index 41e09ed..0d34b2b 100644 > > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > > - reg : offset and length of register shared by multiple > > ports, > > exclude port's private register. It is needed on mt2701 > > and mt8173, but not on mt2712. > > + - mediatek,src-ref-clk-mhz: frequency of reference clock for slew > > rate > > + calibrate > > + - mediatek,src-coef : coefficient for slew rate calibrate, depends > > on > > + SoC process > > > > Required properties (port (child) node): > > - reg : address and length of the register set for the port. > >
Re: [PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
On 03/12/2018 06:25 AM, Chunfeng Yun wrote: > Add two properties of ref_clk and coefficient used by U2 slew rate > calibrate which may vary on different SoCs > > Signed-off-by: Chunfeng Yun Reviewed-by: Matthias Brugger > --- > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > index 41e09ed..0d34b2b 100644 > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > - reg : offset and length of register shared by multiple > ports, > exclude port's private register. It is needed on mt2701 > and mt8173, but not on mt2712. > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate > + calibrate > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on > + SoC process > > Required properties (port (child) node): > - reg: address and length of the register set for the port. >
[PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
Add two properties of ref_clk and coefficient used by U2 slew rate calibrate which may vary on different SoCs Signed-off-by: Chunfeng Yun --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 41e09ed..0d34b2b 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): - reg : offset and length of register shared by multiple ports, exclude port's private register. It is needed on mt2701 and mt8173, but not on mt2712. + - mediatek,src-ref-clk-mhz: frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process Required properties (port (child) node): - reg : address and length of the register set for the port. -- 1.9.1
