On 11/08/17 21:14, Borislav Petkov wrote:
> On Mon, Aug 07, 2017 at 01:46:41PM +1200, Chris Packham wrote:
>> Some integrated Armada XP SoCs use a reduced pin count so the width of
>> the SDRAM interface is smaller than the traditional discrete SoCs. This
>> means that the definition of "full" and
On Mon, Aug 07, 2017 at 01:46:41PM +1200, Chris Packham wrote:
> Some integrated Armada XP SoCs use a reduced pin count so the width of
> the SDRAM interface is smaller than the traditional discrete SoCs. This
> means that the definition of "full" and "half" width is further reduced.
>
> Signed-of
Some integrated Armada XP SoCs use a reduced pin count so the width of
the SDRAM interface is smaller than the traditional discrete SoCs. This
means that the definition of "full" and "half" width is further reduced.
Signed-off-by: Chris Packham
---
drivers/edac/armada_xp_edac.c | 3 +++
1 file c
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