Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround

2016-10-16 Thread Robert Jarzmik
Robert Jarzmik writes: > diff --git a/drivers/net/ethernet/smsc/smc91x.h > b/drivers/net/ethernet/smsc/smc91x.h > index ea8465467469..dff165ed106d 100644 > --- a/drivers/net/ethernet/smsc/smc91x.h > +++ b/drivers/net/ethernet/smsc/smc91x.h And there is also the specific case of ARCH=MN10300, wh

Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround

2016-10-15 Thread Robert Jarzmik
Sorry David, I just noticed you weren't in the "To:" of this serie, but I won't forget you for the v3 I need to release anyway (https://lkml.org/lkml/2016/10/15/104). Robert Jarzmik writes: > + lp->half_word_align4 = > + machine_is_mainstone() || machine_is_stargate2() || > +

Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround

2016-10-13 Thread Robert Jarzmik
David Miller writes: > From: Robert Jarzmik > Date: Sun, 9 Oct 2016 22:33:45 +0200 > >> Writes to u16 has a special handling on 3 PXA platforms, where the >> hardware wiring forces these writes to be u32 aligned. >> >> This patch isolates this handling for PXA platforms as before, but >> enabl

Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround

2016-10-13 Thread David Miller
From: Robert Jarzmik Date: Sun, 9 Oct 2016 22:33:45 +0200 > Writes to u16 has a special handling on 3 PXA platforms, where the > hardware wiring forces these writes to be u32 aligned. > > This patch isolates this handling for PXA platforms as before, but > enables this "workaround" to be set up

Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround

2016-10-09 Thread Robert Jarzmik
Andy Shevchenko writes: >> +#define SMC_outw(lp, v, a, r) \ >> + _SMC_outw_align4((v), (a), (r), \ >> +IS_BUILTIN(CONFIG_ARCH_PXA) && ((r) & 2) &&\ >> +lp->half_word_

Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround

2016-10-09 Thread Andy Shevchenko
On Sun, Oct 9, 2016 at 11:33 PM, Robert Jarzmik wrote: > Writes to u16 has a special handling on 3 PXA platforms, where the > hardware wiring forces these writes to be u32 aligned. > > This patch isolates this handling for PXA platforms as before, but > enables this "workaround" to be set up dynam