On Mon, Mar 19, 2018 at 10:14:19AM +0800, Chen-Yu Tsai wrote:
> On Mon, Mar 19, 2018 at 3:07 AM, Mylène Josserand
> wrote:
> > Hello Mark,
> >
> > Please, excuse me for this late answer and thank you for the review!
> >
> > On Wed, 7 Mar 2018 12:18:33 +
> > Marc
On Mon, Mar 19, 2018 at 10:14:19AM +0800, Chen-Yu Tsai wrote:
> On Mon, Mar 19, 2018 at 3:07 AM, Mylène Josserand
> wrote:
> > Hello Mark,
> >
> > Please, excuse me for this late answer and thank you for the review!
> >
> > On Wed, 7 Mar 2018 12:18:33 +
> > Marc Zyngier wrote:
> >
> >> On
On Sun, Mar 18, 2018 at 08:07:15PM +0100, Mylène Josserand wrote:
> Hello Mark,
>
> Please, excuse me for this late answer and thank you for the review!
>
> On Wed, 7 Mar 2018 12:18:33 +
> Marc Zyngier wrote:
>
> > On 23/02/18 13:37, Mylène Josserand wrote:
> > > On
On Sun, Mar 18, 2018 at 08:07:15PM +0100, Mylène Josserand wrote:
> Hello Mark,
>
> Please, excuse me for this late answer and thank you for the review!
>
> On Wed, 7 Mar 2018 12:18:33 +
> Marc Zyngier wrote:
>
> > On 23/02/18 13:37, Mylène Josserand wrote:
> > > On Cortex-A7, the CNTVOFF
Hi Mylène,
On 18/03/18 19:07, Mylène Josserand wrote:
> Hello Mark,
>
> Please, excuse me for this late answer and thank you for the review!
No worries.
>
> On Wed, 7 Mar 2018 12:18:33 +
> Marc Zyngier wrote:
>
>> On 23/02/18 13:37, Mylène Josserand wrote:
>>> On
Hi Mylène,
On 18/03/18 19:07, Mylène Josserand wrote:
> Hello Mark,
>
> Please, excuse me for this late answer and thank you for the review!
No worries.
>
> On Wed, 7 Mar 2018 12:18:33 +
> Marc Zyngier wrote:
>
>> On 23/02/18 13:37, Mylène Josserand wrote:
>>> On Cortex-A7, the CNTVOFF
On Mon, Mar 19, 2018 at 3:07 AM, Mylène Josserand
wrote:
> Hello Mark,
>
> Please, excuse me for this late answer and thank you for the review!
>
> On Wed, 7 Mar 2018 12:18:33 +
> Marc Zyngier wrote:
>
>> On 23/02/18 13:37, Mylène Josserand
On Mon, Mar 19, 2018 at 3:07 AM, Mylène Josserand
wrote:
> Hello Mark,
>
> Please, excuse me for this late answer and thank you for the review!
>
> On Wed, 7 Mar 2018 12:18:33 +
> Marc Zyngier wrote:
>
>> On 23/02/18 13:37, Mylène Josserand wrote:
>> > On Cortex-A7, the CNTVOFF register from
Hello Mark,
Please, excuse me for this late answer and thank you for the review!
On Wed, 7 Mar 2018 12:18:33 +
Marc Zyngier wrote:
> On 23/02/18 13:37, Mylène Josserand wrote:
> > On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
>
> Only on A7?
Hello Mark,
Please, excuse me for this late answer and thank you for the review!
On Wed, 7 Mar 2018 12:18:33 +
Marc Zyngier wrote:
> On 23/02/18 13:37, Mylène Josserand wrote:
> > On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
>
> Only on A7? Is that specific to
On 23/02/18 13:37, Mylène Josserand wrote:
> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
Only on A7? Is that specific to your platform?
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
On 23/02/18 13:37, Mylène Josserand wrote:
> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
Only on A7? Is that specific to your platform?
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
On 23/02/18 16:17, Chen-Yu Tsai wrote:
> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
> wrote:
>> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
>> It should be done by the bootloader but it is currently not the case,
>> even for boot CPU
On 23/02/18 16:17, Chen-Yu Tsai wrote:
> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
> wrote:
>> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
>> It should be done by the bootloader but it is currently not the case,
>> even for boot CPU because this SoC is booting in
Hello,
On Mon, 5 Mar 2018 09:31:14 +0100
Maxime Ripard wrote:
> On Mon, Mar 05, 2018 at 08:51:48AM +0100, Mylène Josserand wrote:
> > > >> > diff --git a/arch/arm/mach-sunxi/sunxi.c
> > > >> > b/arch/arm/mach-sunxi/sunxi.c
> > > >> > index 5e9602ce1573..4bb041492b54
Hello,
On Mon, 5 Mar 2018 09:31:14 +0100
Maxime Ripard wrote:
> On Mon, Mar 05, 2018 at 08:51:48AM +0100, Mylène Josserand wrote:
> > > >> > diff --git a/arch/arm/mach-sunxi/sunxi.c
> > > >> > b/arch/arm/mach-sunxi/sunxi.c
> > > >> > index 5e9602ce1573..4bb041492b54 100644
> > > >> > ---
On Mon, Mar 05, 2018 at 08:51:48AM +0100, Mylène Josserand wrote:
> > >> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> > >> > index 5e9602ce1573..4bb041492b54 100644
> > >> > --- a/arch/arm/mach-sunxi/sunxi.c
> > >> > +++ b/arch/arm/mach-sunxi/sunxi.c
> > >> > @@ -37,8
On Mon, Mar 05, 2018 at 08:51:48AM +0100, Mylène Josserand wrote:
> > >> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> > >> > index 5e9602ce1573..4bb041492b54 100644
> > >> > --- a/arch/arm/mach-sunxi/sunxi.c
> > >> > +++ b/arch/arm/mach-sunxi/sunxi.c
> > >> > @@ -37,8
Hello,
On Mon, 26 Feb 2018 18:25:10 +0800
Chen-Yu Tsai wrote:
> On Mon, Feb 26, 2018 at 6:12 PM, Maxime Ripard
> wrote:
> > On Sat, Feb 24, 2018 at 12:17:13AM +0800, Chen-Yu Tsai wrote:
> >> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
> >>
Hello,
On Mon, 26 Feb 2018 18:25:10 +0800
Chen-Yu Tsai wrote:
> On Mon, Feb 26, 2018 at 6:12 PM, Maxime Ripard
> wrote:
> > On Sat, Feb 24, 2018 at 12:17:13AM +0800, Chen-Yu Tsai wrote:
> >> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
> >> wrote:
> >> > On Cortex-A7, the CNTVOFF
On Mon, Feb 26, 2018 at 6:12 PM, Maxime Ripard
wrote:
> On Sat, Feb 24, 2018 at 12:17:13AM +0800, Chen-Yu Tsai wrote:
>> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
>> wrote:
>> > On Cortex-A7, the CNTVOFF register from arch timer is
On Mon, Feb 26, 2018 at 6:12 PM, Maxime Ripard
wrote:
> On Sat, Feb 24, 2018 at 12:17:13AM +0800, Chen-Yu Tsai wrote:
>> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
>> wrote:
>> > On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
>> > It should be done by the bootloader
On Sat, Feb 24, 2018 at 12:17:13AM +0800, Chen-Yu Tsai wrote:
> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
> wrote:
> > On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
> > It should be done by the bootloader but it is currently not the
On Sat, Feb 24, 2018 at 12:17:13AM +0800, Chen-Yu Tsai wrote:
> On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
> wrote:
> > On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
> > It should be done by the bootloader but it is currently not the case,
> > even for boot CPU
On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
wrote:
> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
>
On Fri, Feb 23, 2018 at 9:37 PM, Mylène Josserand
wrote:
> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
> It leads to an random offset
On Fri, Feb 23, 2018 at 02:37:42PM +0100, Mylène Josserand wrote:
> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
> It leads to an random
On Fri, Feb 23, 2018 at 02:37:42PM +0100, Mylène Josserand wrote:
> On Cortex-A7, the CNTVOFF register from arch timer is uninitialized.
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
> It leads to an random
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