On 9 August 2017 10:35:39 BST, Harvey Hunt wrote:
>From: John Crispin
>
>Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
>The driver is trivial and only sets up power and host mode.
>
>Signed-off-by: John Crispin
>Signed-off-by: Harvey Hunt
>Cc: linux-kernel@vger.kernel.org
>Cc: linux-media...@lists.infradead.org
>---
>Changes in V4
>* Remove Allwinner from comment
>* Depend on COMPILE_TEST
>
>Changes in V3
>* Separate DT bindings
>* Update Kconfig text
>* Modify John's email address
>* Rebase onto v4.13-rc3
>
>Changes in V2
>* remove refcounting
>* drop empty functions
>* dont use static globals
>* use explicit compatible strings
>
> drivers/phy/Kconfig | 8 ++
> drivers/phy/Makefile | 1 +
>drivers/phy/phy-ralink-usb.c | 173
>+++
> 3 files changed, 182 insertions(+)
> create mode 100644 drivers/phy/phy-ralink-usb.c
>
>diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>index c1807d4..8fb5260 100644
>--- a/drivers/phy/Kconfig
>+++ b/drivers/phy/Kconfig
>@@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
> help
> Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
>
>+config PHY_RALINK_USB
>+ tristate "Ralink USB PHY driver"
>+ select GENERIC_PHY
>+ depends on RALINK || COMPILE_TEST
given that the driver includes a asm/mach-ralink header, the COMPILE_TEST bit
may break x86 allmodconfig?
maybe the header should be moved out of arch/mips or it should depend on MIPS
only (so a mips allmodconfig catches it, but cant be enabled on x86 even with
COMPILE_TEST=y)
cheers
James
>+ help
>+This option enables support for the Ralink USB PHY found inside
>+RT3352, MT7620, MT7628 and MT7688.
>+
> config PHY_XGENE
> tristate "APM X-Gene 15Gbps PHY support"
> depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
>diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>index f252201..60ed30b 100644
>--- a/drivers/phy/Makefile
>+++ b/drivers/phy/Makefile
>@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) +=
>phy-lpc18xx-usb-otg.o
> obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
> obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
>+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
>
> obj-$(CONFIG_ARCH_SUNXI) += allwinner/
> obj-$(CONFIG_ARCH_MESON) += amlogic/
>diff --git a/drivers/phy/phy-ralink-usb.c
>b/drivers/phy/phy-ralink-usb.c
>new file mode 100644
>index 000..14a254a
>--- /dev/null
>+++ b/drivers/phy/phy-ralink-usb.c
>@@ -0,0 +1,173 @@
>+/*
>+ * Copyright (C) 2016 John Crispin
>+ *
>+ * Based on code from
>+ * Allwinner Technology Co., Ltd.
>+ *
>+ * This program is free software; you can redistribute it and/or
>modify
>+ * it under the terms of the GNU General Public License as published
>by
>+ * the Free Software Foundation; either version 2 of the License, or
>+ * (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ */
>+
>+#include
>+#include
>+#include
>+#include
>+#include
>+#include
>+#include
>+#include
>+#include
>+#include
>+
>+#include
>+
>+#define RT_SYSC_REG_SYSCFG1 0x014
>+#define RT_SYSC_REG_CLKCFG1 0x030
>+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
>+
>+#define RT_RSTCTRL_UDEV BIT(25)
>+#define RT_RSTCTRL_UHST BIT(22)
>+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
>+
>+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
>+#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
>+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
>+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
>+
>+#define USB_PHY_UTMI_8B60MBIT(1)
>+#define UDEV_WAKEUP BIT(0)
>+
>+struct ralink_usb_phy {
>+ struct reset_control*rstdev;
>+ struct reset_control*rsthost;
>+ u32 clk;
>+ struct phy *phy;
>+};
>+
>+static int ralink_usb_phy_power_on(struct phy *_phy)
>+{
>+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
>+ u32 t;
>+
>+ /* enable the phy */
>+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
>+
>+ /* setup host mode */
>+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
>+
>+ /* deassert the reset lines */
>+ reset_control_deassert(phy->rsthost);
>+ reset_control_deassert(phy->rstdev);
>+
>+ /*
>+ * The SDK kernel had a delay of 100ms. however on device
>+ * testing showed that 10ms is enough
>+ */
>+ mdelay(10);
>+
>+ /* print some status info */
>+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
>+ dev_info(&phy->phy->dev, "remo
