to ask you to give me some feedback about the patch
series, before I finialize it.
Thanks in advance!
Philipp
Philipp Rossak (5):
[media] rc: update sunxi-ir driver to get base frequency from
devicetree
[media] dt: bindings: Update binding documentation for sunxi IR
controller
ARM
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Other than the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t-ba
The ir interface is like the H3 at 0x01f02000 located and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new requiered property for the base clock frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 --
1 file chan
This patch updates the sunxi-ir driver to set the ir base clock from
devicetree.
This is neccessary since there are different ir recievers on the
market, that operate with different frequencys. So this value needs to
be set depending on the attached receiver.
Signed-off-by: Philipp Rossak <e
The CIR Pin of the A83T is located at PL12
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 19acae1b4089..5edb64
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1 file changed, 3 inse
inal. If the property is not available in
the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunx
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..feffca
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
Hey Andi,
thanks for the feedback. I will fix that in the next version of this
patch series!
On 18.12.2017 03:44, Andi Shyti wrote:
Hi Philipp,
just a couple of small nitpicks.
+ u32 b_clk_freq;
[...]
+ /* Base clock frequency (optional) */
+ if
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1 file changed, 3 inse
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..06e96d
ency to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t:
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9
:49:10 +0100
Philipp Rossak <embe...@gmail.com> escreveu:
Hi Phillip,
This is not a full review of this patchset. I just want to point you
that you should keep supporting existing DT files.
This patch updates the sunxi-ir driver to set the ir base clock from
devicetree.
This is necc
@vger.kernel.org/msg123359.html
Philipp Rossak (5):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the ir pin for the A83T
arm: dts: sun8i: a83t: Add
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Other than the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t-ba
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a384b766f3dc..954c23
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 2 ++
1 file changed, 2 inse
the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..9bbe55a76860
The ir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git
On 05.01.2018 15:59, Maxime Ripard wrote:
Hi,
On Fri, Jan 05, 2018 at 12:02:53PM +, Sean Young wrote:
On Tue, Dec 19, 2017 at 09:07:41AM +0100, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..06e96d
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
vailable in
the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get ba
On 30.01.2018 18:46, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
On 13.02.2018 13:29, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
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