"ext Paul Walmsley" <[EMAIL PROTECTED]> writes:
> Hello,
>
> This patch series adds D2D (die-to-die) clockdomain handling into
> OMAP3 ES2+ builds. It seems the D2D clockdomain logic is still
> present on the chip and must be manually programmed to allow the
> CORE_D2D clockdomain to go inactive.
Hi,
On Thu, 2008-05-22 at 21:01 +0100, ext Russell King - ARM Linux wrote:
> Basically, what I'm trying to say is that ejecting any medium randomly
> from the system is _always_ going to result in problems of some nature.
> Some of which you can reduce the impact from, others are fairly terminal.
On Fri, May 23, 2008 at 01:16:39AM +0530, Syed Mohammed, Khasim wrote:
> > The obscene amount of noise here seems to be caused by ext2 being
> > extremely persistent. This is generally a good thing for your data
> > though. :)
> >
> > What is missing is a decent way for a block device to tell the u
* Kyungmin Park <[EMAIL PROTECTED]> [080520 22:57]:
> Fix compiler error at pm-debug
Thanks, pushing today.
Tony
>
> CC arch/arm/mach-omap2/pm-debug.o
> In file included from arch/arm/mach-omap2/pm-debug.c:30:
> arch/arm/mach-omap2/prm.h: In function `prm_rmw_reg_bits':
> arch/arm/mach-o
Hi Pierre,
> -Original Message-
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Pierre
> Ossman
> Sent: Thursday, May 22, 2008 12:02 AM
> To: Chikkature Rajashekar, Madhusudhan
> Cc: 'Russell King - ARM Linux'; linux-omap@vger.kernel.org; [EMAIL PROTECTED]
> Subject: Re: M
* Paul Walmsley <[EMAIL PROTECTED]> [080521 12:15]:
> Hi Tony,
>
> On Wed, 21 May 2008, Tony Lindgren wrote:
>
> > * Paul Walmsley <[EMAIL PROTECTED]> [080520 18:20]:
> > >
> > > Modify mach-omap2/irq.c to simplify the IRQ number-to-IRQ register and
> > > IRQ
> > > number-to-register bit calcu
Hello,
This patch series adds D2D (die-to-die) clockdomain handling into
OMAP3 ES2+ builds. It seems the D2D clockdomain logic is still
present on the chip and must be manually programmed to allow the
CORE_D2D clockdomain to go inactive.
For this to work, the pm34xx.c code also had to be modifie
Convert iterators of the list of clockdomains in a powerdomain to use
pwrdm_for_each_clkdm(), rather than an open-coded for-loop.
This also fixes a bug when the D2D clockdomain is added to the 3430ES2
chip. The open-coded for-loop tested for a NULL pointer in pwrdm_clkdms[]
to determine when to e
The OMAP34xx ES2+ TRMs do not document the CLKTRCTRL_D2D bit, even
though the clockdomain logic remains on the chip, and must be
programmed appropriately for the CORE clockdomain to go inactive.
Thanks to Rajendra Najak <[EMAIL PROTECTED]> and Richard Woodruff
<[EMAIL PROTECTED]> of TI for providi
If you do not have a "c" as the first character in the permissions, then
your device file is not a true device file, but just a file. You should
delete that file (ttyS1) and create the device file:
mknod /dev/ttyS1 c 4 65
mknod /dev/ttyS2 c 4 66
Steve
mohammed shareef wrote:
hi,
i have cha
> -Original Message-
> From: Pierre Ossman [mailto:[EMAIL PROTECTED]
> Sent: Thursday, May 22, 2008 12:02 AM
> To: Madhusudhan Chikkature Rajashekar
> Cc: 'Russell King - ARM Linux'; linux-omap@vger.kernel.org;
> [EMAIL PROTECTED]
> Subject: Re: MMC/SD cards hotplug scenario
>
> On We
While trying to make H4 USB work I had the following issues,
attached are patches to fix those:
- Fix the H4 board config for the wiring of the ISP1301
transceiver. The platform config had 4 wire configuration but
the driver has the 3 wire mode hard-coded. It's also possible
to set the ISP13
On Thu, May 22, 2008 at 12:53 PM, mohammed shareef <[EMAIL PROTECTED]> wrote:
> hi arun/all,
>
> when i do cat for interrupts i get:
>
> # cat /proc/interrupts
> CPU0
> 19: 0 MPU DMA
> 20: 0 MPU DMA
> 21: 0 MPU DMA
> 22: 0
On Thu, 22 May 2008 12:53:11 +0530, "mohammed shareef"
<[EMAIL PROTECTED]> wrote:
> hi arun/all,
>
> when i do cat for interrupts i get:
>
> # cat /proc/interrupts
>CPU0
> 19: 0 MPU DMA
> 20: 0 MPU DMA
> 21: 0 MPU DMA
> 22:
hi arun/all,
when i do cat for interrupts i get:
# cat /proc/interrupts
CPU0
19: 0 MPU DMA
20: 0 MPU DMA
21: 0 MPU DMA
22: 0 MPU DMA
23: 0 MPU DMA
24: 0 MPU DMA
25:
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