OMAP3430/3630 has a Silicon bug because of which SDRC is released from
IDLE even before Core DPLL has locked. This leads to undefined behaviour
of SDRC DLL. This patch has workaround for the same.
Description of WA for 3430:
Initialization:
Disable DPLL3 automatic mode by default. Issue
Fix for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have glitches when their output value is updated.
28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock
is switched from internal to external.
Workaround requires the TWL DCDCs to use
Updated subject line with patch version (v2).
-Original Message-
From: Lesly A M [mailto:lesl...@ti.com]
Sent: Friday, April 09, 2010 4:03 PM
To: linux-omap@vger.kernel.org
Cc: Lesly A M; Nishanth Menon; David Derrick; Samuel Ortiz
Subject: [PATCH] MFD: TWL4030: changes for TRITON
Hello Kan-Ru,
On 04/07/10 08:34, Kan-Ru Chen wrote:
This patch corrects the DVI-D output setup of Devkit8000
Devkit8000 has different DVI reset pin with the BeagleBoard. On Devkit8000
the TWL4030 GPIO_7 is assigned to do the job.
Signed-off-by: Kan-Ru Chen ka...@0xlab.org
---
Hello all,
I've got a custom OMAP3503 board with 256Mbytes of LPDDR memory
(single die, x32-bit) that i've got working with x-loader and u-
boot. However, when i load the Linux kernel (2.6.32 git), it randomly produces
the following errors:
1) Hangs midway through the
Menon, Nishanth had written, on 04/08/2010 12:54 PM, the following:
From: Deepak K deepa...@ti.com
[...]
Cc: Govindraj R govindraj.r...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Tero Kristo tero.kri...@nokia.com
Signed-off-by: Deepak K deepa...@ti.com
Signed-off-by: Nishanth
Hi Nishanth
My comments below.
Regards
Deepak
-Original Message-
From: Menon, Nishanth
Sent: Friday, April 09, 2010 12:00 PM
To: linux-omap
Cc: Kattungal, Deepak; Raja, Govindraj; Kevin Hilman; Tero Kristo
Subject: Re: [PM][PATCH 2/4] OMAP3: Serial: Errata i202: fix for MDR1 access
From: Deepak K deepa...@ti.com
Original patch:
http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=42d4a342c009bd9727c100abc8a4bc3063c22f0c
Errata i202 (OMAP3430 - 1.12, OMAP3630 - 1.6):
UART module MDR1 register access can cause a dummy underrun
condition which could result in a freeze in
