On Thu, 12 Sep 2013 17:57:00 +0200, Alexander Holler hol...@ahsoftware.de
wrote:
Am 12.09.2013 17:19, schrieb Stephen Warren:
IRQs, DMA channels, and GPIOs are all different things. Their bindings
are defined independently. While it's good to define new types of
bindings consistently
On 17/09/13 22:40, Mike Turquette wrote:
I hope that the existing CLK_SET_RATE_PARENT flag could help you get
the frequency you need; it causes a call to clk_set_rate(leaf_clk,
target_rate) to walk up the chain of parents and configure rates as
needed.
Hmm, I'm not quite sure what that does,
On Wednesday 18 September 2013 03:49:42 Felipe Balbi wrote:
On Tue, Sep 17, 2013 at 09:28:42PM +0200, Pali Rohár wrote:
On Tuesday 17 September 2013 18:08:35 Felipe Balbi wrote:
On Tue, Sep 17, 2013 at 06:05:15PM +0200, Pali Rohár wrote:
On Tuesday 17 September 2013 17:48:59 you wrote:
On Wednesday 18 September 2013 01:24:17 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [130710 06:06]:
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
This file will be gone as soon as we're moving to device
tree based booting. So let's do this in
Hi Tony,
On 18/09/2013 02:02, Tony Lindgren wrote:
* Luca Coelho l...@coelho.fi [130916 23:35]:
On Tue, 2013-09-17 at 09:26 +0300, Luca Coelho wrote:
Both patches look good to me, though I didn't have the time to retest
them.
Actually I don't even have a Blaze device anymore, so I can't
On Wed, Sep 18, 2013 at 10:20 AM, Pali Rohár pali.ro...@gmail.com wrote:
On Wednesday 18 September 2013 03:49:42 Felipe Balbi wrote:
On Tue, Sep 17, 2013 at 09:28:42PM +0200, Pali Rohár wrote:
On Tuesday 17 September 2013 18:08:35 Felipe Balbi wrote:
On Tue, Sep 17, 2013 at 06:05:15PM
Hi Tony,
Please pull few fixes for OMAP DTS.
Thanks,
Benoit
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
On 16.09.2013 17:14, Nishanth Menon wrote:
On 10:49-20130916, Aida Mynzhasova wrote:
On 24.08.2013 18:02, Aida Mynzhasova wrote:
This patch adds required definitions and structures for clockdomain
initialization, so omap3xxx_clockdomains_init() was substituted by
new ti81xx_clockdomains_init()
Hi Benoit,
2013/9/18 Benoit Cousson bcous...@baylibre.com:
Hi Tony,
Please pull few fixes for OMAP DTS.
Thanks,
Benoit
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
Some omapdss panels are connected to outputs/encoders(HDMI/DSI/DPI) that require
regulators. The output's connect op tries to get a regulator which may not exist
yet because it might get registered later in the kernel boot.
omapdrm currently ignores those panels which return a non zero value when
On Wednesday 18 September 2013 04:38 PM, Archit Taneja wrote:
Some omapdss panels are connected to outputs/encoders(HDMI/DSI/DPI) that require
regulators. The output's connect op tries to get a regulator which may not exist
yet because it might get registered later in the kernel boot.
omapdrm
On Tue, Sep 17, 2013 at 9:07 PM, Felipe Balbi ba...@ti.com wrote:
has anyone ever successfully using gpio-pcf857x.c driver with 16-bit
gpio expanders ? We're having some issues here where toggling the last
gpio pin (gpio 15) on a PCF8575 device causes platform to hang and I
can't come up with
The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.
The ratio registers are missing for a sys-clk of 20MHZ which is used
by DRA7 socs. So because of
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other
Hi,
On Tuesday 17 September 2013 10:31 PM, Nishanth Menon wrote:
CNTFREQ isn't pre-programmed on DRA7 just like O5, so provide the
timer frequency via DT. Without a valid value arch_timer_init results
in div0 crash.
Cc: R Sricharan r.sricha...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc:
On 09/18/2013 04:40 AM, Aida Mynzhasova wrote:
On 16.09.2013 17:14, Nishanth Menon wrote:
On 10:49-20130916, Aida Mynzhasova wrote:
On 24.08.2013 18:02, Aida Mynzhasova wrote:
This patch adds required definitions and structures for clockdomain
initialization, so omap3xxx_clockdomains_init()
Hi Enric,
On 10/09/2013 17:38, Enric Balletbo Serra wrote:
2013/9/10 Enric Balletbo i Serra eballe...@gmail.com:
Add pinmux configuration for MCBSP2 connected to the TDM interface. With
this configuration the Headset modules works as expected.
Signed-off-by: Enric Balletbo i Serra
On 18/09/13 14:08, Archit Taneja wrote:
Some omapdss panels are connected to outputs/encoders(HDMI/DSI/DPI) that
require
regulators. The output's connect op tries to get a regulator which may not
exist
yet because it might get registered later in the kernel boot.
omapdrm currently
Hi Enric
On 18/09/2013 12:24, Enric Balletbo Serra wrote:
Hi Benoit,
2013/9/18 Benoit Cousson bcous...@baylibre.com:
Hi Tony,
Please pull few fixes for OMAP DTS.
Thanks,
Benoit
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16
Hi Tony,
Please pull few fixes for OMAP DTS. This take #2 contains one more fix I missed
from Enric.
Thanks,
Benoit
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
omap_get_control_dev() is being deprecated as it doesn't support
multiple instances. As control device is present only from OMAP4
onwards which supports DT only, we use phandles to get the
reference to the control device.
As we don't support non-DT boot, we just bail out on probe
if device node
Split USB2 PHY and USB3 PHY into separate omap-control-usb
nodes. Get rid of ti,type property.
CC: Benoit Cousson bcous...@baylibre.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 20
1 files changed, 12 insertions(+), 8 deletions(-)
diff
Hi,
This patchset does the following:
* Get rid of omap_control_usb platform data as we support DT only.
* Restructure and add support for new PHY types. We now support the follwing
four types
TYPE_OTGHS - if it has otghs_control mailbox register (e.g. on OMAP4)
TYPE_USB2 - if it has Power
The OTG_SS controller driver manages the OTG_SS clock. The phy driver
needs to manage the PHY's functional clock. So correct the clock name.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/usb/phy/phy-omap-usb2.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git
usb_otg_ss_refclk960m is an optional functional clock to the
UBS_OTG_SS module. So manage it in the driver.
Also update device tree binding information.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt |4
drivers/usb/dwc3/dwc3-omap.c
omap_get_control_dev() is being deprecated as it doesn't support
multiple instances. As control device is present only from OMAP4
onwards which supports DT only, we use phandles to get the
reference to the control device.
Also get rid of ti,has-mailbox property as it is redundant and
we can
omap_get_control_dev() is being deprecated as it doesn't support
multiple instances. As control device is present only from OMAP4
onwards which supports DT only, we use phandles to get the
reference to the control device.
As we don't support non-DT boot, we just bail out on probe
if device node
This function was preventing us from supporting multiple
instances. Get rid of it. Since we support DT boots only,
users can get the control device phandle from the DT node.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/usb/phy/phy-omap-control.c | 31 ++-
omap-control device is present from OMAP4 onwards which
support device tree boots only. So get rid of platform data.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/usb/phy/phy-omap-control.c | 12 +++-
include/linux/usb/omap_control_usb.h |4
2 files changed, 3
Split otghs_ctrl and USB2 PHY power-down into separate
omap-control-usb nodes. Get rid of ti,type property.
Also get rid of ti,has-mailbox property from usb_otg_hs
node and provide the ctrl-module phandle.
CC: Benoit Cousson bcous...@baylibre.com
Signed-off-by: Roger Quadros rog...@ti.com
---
Add support for new device types and in the process rid of ti,type
device tree property. The correct type of device will be determined
from the compatible string instead.
Introduce a compatible string for each device type. At the moment
we support 4 types OTGHS, USB2, PIPE3 (e.g. USB3) and
On 16:50-20130918, Sricharan R wrote:
The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.
The ratio registers are missing for a sys-clk of 20MHZ
On 16:53-20130918, Sricharan R wrote:
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file
On 09/18/2013 06:33 AM, Sricharan R wrote:
Hi,
On Tuesday 17 September 2013 10:31 PM, Nishanth Menon wrote:
CNTFREQ isn't pre-programmed on DRA7 just like O5, so provide the
timer frequency via DT. Without a valid value arch_timer_init results
in div0 crash.
Cc: R Sricharan
On Sun 2013-09-08 02:02:52, Aaro Koskinen wrote:
Hi,
On Fri, Sep 06, 2013 at 10:34:05PM +0200, Pali Rohár wrote:
--- /dev/null
+++ b/arch/arm/mach-omap2/board-rx51-camera.c
[...]
Ping, can you review this patch v2?
I don't think Tony will accept any new board stuff for RX-51/N900.
On Wednesday 18 September 2013 06:11 PM, Tomi Valkeinen wrote:
On 18/09/13 14:08, Archit Taneja wrote:
Some omapdss panels are connected to outputs/encoders(HDMI/DSI/DPI) that require
regulators. The output's connect op tries to get a regulator which may not exist
yet because it might get
On Wednesday 18 September 2013 07:33 AM, Sricharan R wrote:
Hi,
On Tuesday 17 September 2013 10:31 PM, Nishanth Menon wrote:
CNTFREQ isn't pre-programmed on DRA7 just like O5, so provide the
timer frequency via DT. Without a valid value arch_timer_init results
in div0 crash.
Cc: R
On Wednesday 18 September 2013 07:20 AM, Sricharan R wrote:
The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.
The ratio registers are missing
On 18/09/13 16:17, Archit Taneja wrote:
On Wednesday 18 September 2013 06:11 PM, Tomi Valkeinen wrote:
On 18/09/13 14:08, Archit Taneja wrote:
Some omapdss panels are connected to outputs/encoders(HDMI/DSI/DPI)
that require
regulators. The output's connect op tries to get a regulator which
Hi!
So will you do that? Or it is needed to resend this one line
hunk again in new email again?
new patch, new email
Guys, WHY ARE YOU SO STUPID AND ARROGANT?
Sorry but, need to copy full isolated patch/hunk from one mail to
another is hassling. So what you want from me? Do
On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is
On Wednesday 18 September 2013 07:01 PM, Santosh Shilimkar wrote:
On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote
On 09/18/2013 08:31 AM, Santosh Shilimkar wrote:
On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
[...]
4, 0, 0, 0, 0, 0);
/*
+ * Configure the CNTFRQ register for the secondary cpu's which
+ * indicates the frequency
On Wednesday 18 September 2013 09:44 AM, Nishanth Menon wrote:
On 09/18/2013 08:31 AM, Santosh Shilimkar wrote:
On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
[...]
4, 0, 0, 0, 0, 0);
/*
+* Configure the CNTFRQ register
On Wednesday 18 September 2013 09:44 AM, Sricharan R wrote:
On Wednesday 18 September 2013 07:01 PM, Santosh Shilimkar wrote:
On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
The realtime counter called master counter, produces the count
used by the private timer peripherals in the
On Wednesday 18 September 2013 07:19 PM, Santosh Shilimkar wrote:
On Wednesday 18 September 2013 09:44 AM, Sricharan R wrote:
On Wednesday 18 September 2013 07:01 PM, Santosh Shilimkar wrote:
On Wednesday 18 September 2013 07:23 AM, Sricharan R wrote:
The realtime counter called master
Hi Thomas,
On Tuesday 17 September 2013 05:56 PM, Linus Walleij wrote:
On Fri, Sep 13, 2013 at 4:24 PM, Thomas Gleixner t...@linutronix.de wrote:
So why can't you make use of irq domains and have the whole routing
business implemented sanely?
What's needed is in gic_init_bases():
irq
OMAP5 ES1.0 was intended as a test chip and has major register level
differences w.r.t ES2.0 revision of the chip. All register defines,
dts support has been solely added for ES2.0 version of the chip.
Further, all ES1.0 chips and platforms are supposed to have been
removed from circulation.
On Wednesday 18 September 2013 10:05 AM, Nishanth Menon wrote:
OMAP5 ES1.0 was intended as a test chip and has major register level
differences w.r.t ES2.0 revision of the chip. All register defines,
dts support has been solely added for ES2.0 version of the chip.
Further, all ES1.0 chips and
On Wed, Sep 18, 2013 at 1:50 AM, Tony Lindgren t...@atomide.com wrote:
* Aaro Koskinen aaro.koski...@iki.fi [130907 16:10]:
Hi,
On Fri, Sep 06, 2013 at 10:34:05PM +0200, Pali Rohár wrote:
--- /dev/null
+++ b/arch/arm/mach-omap2/board-rx51-camera.c
[...]
Ping, can you review this patch
Hi!
So will you do that? Or it is needed to resend this one line
hunk again in new email again?
new patch, new email
Guys, WHY ARE YOU SO STUPID AND ARROGANT?
Sorry but, need to copy full isolated patch/hunk from one mail to
another is hassling. So what you want from
Hi!
gave feedback. If the sender doesn't want to take his feedback into
account and prefer to send pretty insulting emails instead that is his
choice but I would say that is this not the greatest approach to get
your code merged (to say the least).
Clearly not. But Pali found bug in
On Wed, Sep 18, 2013 at 4:22 PM, Pavel Machek pa...@ucw.cz wrote:
Hi!
So will you do that? Or it is needed to resend this one line
hunk again in new email again?
new patch, new email
Guys, WHY ARE YOU SO STUPID AND ARROGANT?
Sorry but, need to copy full isolated
Thomas,
On Friday 13 September 2013 10:55 AM, Santosh Shilimkar wrote:
On Friday 13 September 2013 10:24 AM, Thomas Gleixner wrote:
[...]
Before you dig into MSI, lets talk about irq domains first.
GIC implements a legacy irq domain, i.e. a linear domain of all
possible GIC interrupts with
On Wednesday 18 September 2013 07:22 PM, Sricharan R wrote:
Hi Thomas,
On Tuesday 17 September 2013 05:56 PM, Linus Walleij wrote:
On Fri, Sep 13, 2013 at 4:24 PM, Thomas Gleixner t...@linutronix.de wrote:
So why can't you make use of irq domains and have the whole routing
business
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other
On Wednesday 18 September 2013 15:16:44 Pavel Machek wrote:
On Sun 2013-09-08 02:02:52, Aaro Koskinen wrote:
Hi,
On Fri, Sep 06, 2013 at 10:34:05PM +0200, Pali Rohár wrote:
--- /dev/null
+++ b/arch/arm/mach-omap2/board-rx51-camera.c
[...]
Ping, can you review this patch
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other
Hi,
On Wed, Sep 18, 2013 at 04:35:37PM +0200, Pavel Machek wrote:
Hi!
gave feedback. If the sender doesn't want to take his feedback into
account and prefer to send pretty insulting emails instead that is his
choice but I would say that is this not the greatest approach to get
your
On Wednesday 18 September 2013 09:23 PM, Sricharan R wrote:
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is
On Wednesday 18 September 2013 15:57:13 Javier Martinez Canillas
wrote:
to split the patch in two since the patch was solving
two separate issues
My patch does not solving *two* issues. It is *one* regression
and both parts of patch are needed for fixing it. Read commit
message again. It
On Wed, Sep 18, 2013 at 05:56:12PM +0200, Pali Rohár wrote:
On Wednesday 18 September 2013 15:57:13 Javier Martinez Canillas
wrote:
to split the patch in two since the patch was solving
two separate issues
My patch does not solving *two* issues. It is *one* regression
and both parts of
On 18.09.2013 15:56, Nishanth Menon wrote:
On 09/18/2013 04:40 AM, Aida Mynzhasova wrote:
On 16.09.2013 17:14, Nishanth Menon wrote:
On 10:49-20130916, Aida Mynzhasova wrote:
On 24.08.2013 18:02, Aida Mynzhasova wrote:
This patch adds required definitions and structures for clockdomain
On Wednesday 18 September 2013 18:36:49 Felipe Balbi wrote:
On Wed, Sep 18, 2013 at 05:56:12PM +0200, Pali Rohár wrote:
On Wednesday 18 September 2013 15:57:13 Javier Martinez
Canillas
wrote:
to split the patch in two since the patch was solving
two separate issues
My patch
On Wed, Sep 18, 2013 at 06:43:49PM +0200, Pali Rohár wrote:
On Wednesday 18 September 2013 18:36:49 Felipe Balbi wrote:
On Wed, Sep 18, 2013 at 05:56:12PM +0200, Pali Rohár wrote:
On Wednesday 18 September 2013 15:57:13 Javier Martinez
Canillas
wrote:
to split the patch in two
More power supply drivers depends on vbus events and without it they not
working. Power supply drivers using usb_register_notifier, so to deliver
events it is needed to call atomic_notifier_call_chain.
So without atomic notifier power supply driver isp1704 not retrieving
vbus status and reporting
twl-phy.notifier is not initalized
Signed-off-by: Pali Rohár pali.ro...@gmail.com
diff --git a/drivers/usb/phy/phy-twl4030-usb.c
b/drivers/usb/phy/phy-twl4030-usb.c
index 8f78d2d..efe6155 100644
--- a/drivers/usb/phy/phy-twl4030-usb.c
+++ b/drivers/usb/phy/phy-twl4030-usb.c
@@ -705,6 +705,8 @@
On Wednesday 18 September 2013 13:16:27 Linus Walleij wrote:
On Tue, Sep 17, 2013 at 9:07 PM, Felipe Balbi ba...@ti.com wrote:
has anyone ever successfully using gpio-pcf857x.c driver with 16-bit
gpio expanders ? We're having some issues here where toggling the last
gpio pin (gpio 15) on a
* Pali Rohár pali.ro...@gmail.com [130918 01:41]:
I'm not very happy. I sent this patch 6 months ago and only now
you commented that needs rework again. This patch is needed
because all thumb-2 userspace binaries crashing. I want to have
working support for Nokia N900 and not always
Hi,
On Wed, Sep 18, 2013 at 07:18:04PM +0200, Laurent Pinchart wrote:
On Wednesday 18 September 2013 13:16:27 Linus Walleij wrote:
On Tue, Sep 17, 2013 at 9:07 PM, Felipe Balbi ba...@ti.com wrote:
has anyone ever successfully using gpio-pcf857x.c driver with 16-bit
gpio expanders ? We're
* Pali Rohár pali.ro...@gmail.com [130918 09:08]:
On Wednesday 18 September 2013 15:16:44 Pavel Machek wrote:
On Sun 2013-09-08 02:02:52, Aaro Koskinen wrote:
Hi,
On Fri, Sep 06, 2013 at 10:34:05PM +0200, Pali Rohár wrote:
--- /dev/null
+++
* Javier Martinez Canillas martinez.jav...@gmail.com [130918 07:20]:
Hi Tony,
I don't know if OMAP2+ DT will happen soon as you said. At least I
know about a big issue we had with GPIO pins not being auto-requested
when are mapped as IRQ. You can refer to [1] for the latest approach
and
* Benoit Cousson bcous...@baylibre.com [130918 02:12]:
Hi Tony,
On 18/09/2013 02:02, Tony Lindgren wrote:
* Luca Coelho l...@coelho.fi [130916 23:35]:
On Tue, 2013-09-17 at 09:26 +0300, Luca Coelho wrote:
Both patches look good to me, though I didn't have the time to retest
them.
* Pali Rohár pali.ro...@gmail.com [130918 11:21]:
On Wednesday 18 September 2013 19:18:17 Tony Lindgren wrote:
Hmm hasn't there been pending comments until recently on your
patches?
Since 10.07.2013 I do not have any emails for patch 2/2. If I
missed something from you, please
* Daniel Mack zon...@gmail.com [130909 02:06]:
On 08.09.2013 13:23, Mugunthan V N wrote:
This patch series adds the support for configuring GMII_SEL register
of control module to select the phy mode type and also to configure
the clock source for RMII phy mode whether to use internal clock
* Phil Carmody phil.carm...@partner.samsung.com [130909 06:25]:
Signed-off-by: Phil Carmody phil.carm...@partner.samsung.com
Thanks applying into omap-for-v3.12/fixes.
Tony
arch/arm/mach-omap2/mux34xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hello,
On Wednesday 18 September 2013 19:18:17 Tony Lindgren wrote:
* Pali Rohár pali.ro...@gmail.com [130918 01:41]:
I'm not very happy. I sent this patch 6 months ago and only
now you commented that needs rework again. This patch is
needed because all thumb-2 userspace binaries crashing.
* Sekhar Nori nsek...@ti.com [130916 05:33]:
On Friday 13 September 2013 09:07 PM, Tony Lindgren wrote:
* Sekhar Nori nsek...@ti.com [130913 03:18]:
Get rid of TI specific binding ti,non-removable in favour of the
generic binding present for the same purpose.
Looks like there's a
Hello Tony,
here is new v3 patch. I just only moved functions rx51_secure_dispatcher and
rx51_secure_update_aux_cr to omap-secure.c and added header to omap-secure.h
Because I only moved two functions to other source file I tested only
compilation.
It is OK now?
diff --git
* Sebastian Reichel s...@debian.org [130915 13:56]:
This patch adds an OMAP SSI driver to the HSI framework.
Thanks for working on this.
+config OMAP_SSI
+ tristate OMAP SSI hardware driver
+ depends on ARCH_OMAP HSI
+ default n
+ ---help---
+ SSI is a legacy
* Pali Rohár pali.ro...@gmail.com [130918 12:29]:
Hello Tony,
here is new v3 patch. I just only moved functions rx51_secure_dispatcher and
rx51_secure_update_aux_cr to omap-secure.c and added header to omap-secure.h
Because I only moved two functions to other source file I tested only
Closed and signed Nokia X-Loader bootloader stored in RX-51 nand does not set
IBE bit in ACTLR and starting kernel in non-secure mode. So direct write to
ACTLR by our kernel does not working and the code for ARM errata 430973 in
commit 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 that sets IBE bit is
This driver provides kernel-side support for the Random Number
Generator hardware found on OMAP34xx processors.
Signed-off-by: Pali Rohár pali.ro...@gmail.com
Signed-off-by: Juha Yrjola juha.yrj...@solidboot.com
---
drivers/char/hw_random/Kconfig | 13 +++
Signed-off-by: Pali Rohár pali.ro...@gmail.com
---
arch/arm/mach-omap2/board-rx51.c | 10 ++
arch/arm/mach-omap2/omap-secure.c | 11 +++
arch/arm/mach-omap2/omap-secure.h |1 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm/mach-omap2/board-rx51.c
This two patches adding support for OMAP3 ROM Random Number Generator on Nokia
N900.
Pali Rohár (2):
hwrng: OMAP3 ROM Random Number Generator support
RX-51: Add support for OMAP3 ROM Random Number Generator
arch/arm/mach-omap2/board-rx51.c | 10 +++
On Wed, 2013-09-18 at 22:05 +0200, Pali Rohár wrote:
This driver provides kernel-side support for the Random Number
Generator hardware found on OMAP34xx processors.
[]
diff --git a/drivers/char/hw_random/omap3-rom-rng.c
b/drivers/char/hw_random/omap3-rom-rng.c
trivial note:
It produces
* Pali Rohár pali.ro...@gmail.com [130918 13:15]:
Signed-off-by: Pali Rohár pali.ro...@gmail.com
Description please, then also add a note that this makes
sense to do as a platform device at least until we have
some ARM generic way to deal with SMC calls.
arch/arm/mach-omap2/board-rx51.c |
Hi,
On Wed, Sep 18, 2013 at 10:05:56PM +0200, Pali Rohár wrote:
+ if (IS_ERR(rng_clk)) {
+ printk(KERN_ERR %s: unable to get RNG clock\n,
+omap3_rom_rng_name);
+ return IS_ERR(rng_clk);
This should be PTR_ERR().
A.
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The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
tags/omap-for-v3.12/fixes-signed
for you to fetch changes up to
On Wed, Sep 18, 2013 at 01:59:02PM -0700, Tony Lindgren wrote:
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
On Wed, Sep 18, 2013 at 01:59:02PM -0700, Tony Lindgren wrote:
The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f:
Linux 3.12-rc1 (2013-09-16 16:17:51 -0400)
are available in the git repository at:
Without max_current data in board file lp5523 driver does not change current.
Signed-off-by: Pali Rohár pali.ro...@gmail.com
---
arch/arm/mach-omap2/board-rx51-peripherals.c |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c
On Wed, 18 Sep 2013, Sricharan R wrote:
On Wednesday 18 September 2013 07:22 PM, Sricharan R wrote:
Hi Thomas,
On Tuesday 17 September 2013 05:56 PM, Linus Walleij wrote:
On Fri, Sep 13, 2013 at 4:24 PM, Thomas Gleixner t...@linutronix.de
wrote:
So why can't you make use of irq
* Pali Rohár pali.ro...@gmail.com [130918 15:02]:
Without max_current data in board file lp5523 driver does not change current.
Hmm is this a regression or are there other reasons to merge
this during the -rc cycle?
Regards,
Tony
Signed-off-by: Pali Rohár pali.ro...@gmail.com
---
On Wed, 18 Sep 2013, Santosh Shilimkar wrote:
On Friday 13 September 2013 10:55 AM, Santosh Shilimkar wrote:
On Friday 13 September 2013 10:24 AM, Thomas Gleixner wrote:
[...]
Before you dig into MSI, lets talk about irq domains first.
GIC implements a legacy irq domain, i.e. a
* Tony Lindgren t...@atomide.com [130918 11:00]:
* Benoit Cousson bcous...@baylibre.com [130918 02:12]:
Hi Tony,
On 18/09/2013 02:02, Tony Lindgren wrote:
* Luca Coelho l...@coelho.fi [130916 23:35]:
On Tue, 2013-09-17 at 09:26 +0300, Luca Coelho wrote:
Both patches look good to me,
On Wed, Sep 18, 2013 at 2:04 AM, Benoit Cousson bcous...@baylibre.com wrote:
Hi Tony,
On 18/09/2013 02:02, Tony Lindgren wrote:
* Luca Coelho l...@coelho.fi [130916 23:35]:
On Tue, 2013-09-17 at 09:26 +0300, Luca Coelho wrote:
Both patches look good to me, though I didn't have the time
On Wed, 2013-09-18 at 16:47 -0700, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [130918 11:00]:
* Benoit Cousson bcous...@baylibre.com [130918 02:12]:
Hi Tony,
On 18/09/2013 02:02, Tony Lindgren wrote:
* Luca Coelho l...@coelho.fi [130916 23:35]:
On Tue, 2013-09-17 at
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