Tony Lindgren t...@atomide.com writes:
Ping, looks like these are still pending. Probably should be
applied directly by the arm-soc maintainers.
If these should go through arm-soc, please resend to:a...@kernel.org so
they make it into our queue of stuff to be reviewed/applied.
Kevin
--
To
On 08/07/2015 03:17 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 02:35:45PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 12:55 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 10:41:57AM +0200, Sebastian Andrzej Siewior wrote:
This DMA driver is used by
On 08/07/2015 03:22 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 12:36:14PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 11:44 AM, Peter Ujfalusi wrote:
with a short testing audio did not broke (the only user of pause/resume)
Some comments embedded.
Cc:
On Fri, Aug 07, 2015 at 03:42:06PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 03:22 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 12:36:14PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 11:44 AM, Peter Ujfalusi wrote:
with a short testing audio did not
On Fri, Aug 07, 2015 at 02:35:45PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 12:55 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 10:41:57AM +0200, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to
On Fri, Aug 07, 2015 at 12:36:14PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 11:44 AM, Peter Ujfalusi wrote:
with a short testing audio did not broke (the only user of pause/resume)
Some comments embedded.
Cc: sta...@vger.kernel.org
Why stable? This is not fixing any
On Fri, Aug 07, 2015 at 03:22:56PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 03:17 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 02:35:45PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 12:55 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at
The 8250-omap driver requires the DMA-engine driver to support the pause
command in order to properly turn off programmed RX transfer before the
driver stars manually reading from the FIFO.
The lacking support of the requirement has been discovered recently. In
order to stay safe here we disable
On 6 August 2015 at 23:33, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
On Thu, Aug 6, 2015 at 3:51 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Aug 06, 2015 at 05:55:23PM +0530, Vignesh R
The OMAP GPMC module has certain registers dedicated for NAND
access and some NAND bits mixed with other GPMC functionality.
For the NAND dedicated registers we have the struct gpmc_nand_regs.
The NAND driver needs to access NAND specific bits from the
following non-dedicated registers
1)
Hi Tony,
On 08/07/2015 06:36 AM, Tony Lindgren wrote:
* Linus Walleij linus.wall...@linaro.org [150716 01:38]:
On Wed, Jun 24, 2015 at 4:54 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Add missed spin_unlock_irqrestore in
On 8/6/2015 23:33, Russell King - ARM Linux wrote:
On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
Irrespective of the dummy bytes.
What if the spi device is not a FLASH ROM, but some other device,
which receives a data packet that accidentally looks like an m25p80 READ
On 05/08/15 17:18, Kishon Vijay Abraham I wrote:
Hi Roger,
On Wednesday 05 August 2015 01:55 PM, Roger Quadros wrote:
On 05/08/15 11:23, Roger Quadros wrote:
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off
On 05/08/15 15:24, Tomeu Vizoso wrote:
...if there isn't one already.
If for some reason the GPMC device hasn't been probed yet, gpmc_base is
going to be NULL. Because there's no context yet to be saved, just turn
these functions into no-ops until that device gets probed.
Unable to handle
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 122
The WAIT pins support falling edge interrupts so add irqchip
support to the gpiochip model.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 111 +
1 file changed, 111 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
TODO: For now only dra7-evm and omap3-beagle are fixed.
Once series is reviewed I'll update this patch to
fix all omap boards.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c
Manage NAND interrupts here using the GPMC IRQ ops.
This causes performance in prefetch-irq mode to be increased
from
[ 38.252811] mtd_speedtest: eraseblock write speed is 5576 KiB/s
[ 39.265259] mtd_speedtest: eraseblock read speed is 8192 KiB/s
to
[ 35.666446] mtd_speedtest: eraseblock
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mtd/nand/omap2.c | 26 ++
1 file changed,
On 08/07/2015 01:08 PM, Michal Suchanek wrote:
Now since the description is clearer it's obvious that ti-qspi cannot
work fully mmapped as fsl-qspi does because the setup has to be done
over normal spi access and using non-m25p80 devices on the same bus is
a requirement.
The place where
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the DMA controller starts the transfer shortly after.
Before we can manually purge
On Thursday 06 August 2015 03:21 PM, Tony Lindgren wrote:
* Alexandre Belloni alexandre.bell...@free-electrons.com [150806 02:50]:
On 06/08/2015 at 12:36:54 +0300, Grygorii Strashko wrote :
Pls, correct me if I'm not right. Is below what you propose?
Doard dts:
/ {
rtc_32k_ext_clk:
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 2 +-
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros rog...@ti.com
---
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros rog...@ti.com
---
.../bindings/{bus/ti-gpmc.txt = memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros rog...@ti.com
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros rog...@ti.com
---
include/linux/omap-gpmc.h | 134 --
include/linux/platform_data/gpmc-omap.h | 139
2 files changed,
Hi,
We do a couple of things in this series which result in
cleaner device tree implementation, faster perfomance and
multi-platform support. As an added bonus we get new GPI/Interrupt pins
for use in the system.
- Establish a custom interface between NAND and GPMC driver. This is
needed because
Hi Lee / Samuel,
On 03/08/15 17:40, Roger Quadros wrote:
Some palmas based chip variants do not have OTG based ID logic.
For these variants we rely on GPIO based USB ID detection.
These chips do have VBUS comparator for VBUS detection so we
continue to use the old way of detecting VBUS.
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mtd/nand/omap2.c | 29 +---
Partitions which are defined in the som file can not be deleted in the
board file.
Signed-off-by: Matthias Klein matthias.kl...@optimeas.de
---
arch/arm/boot/dts/am335x-phycore-som.dtsi | 37 -
arch/arm/boot/dts/am335x-wega.dtsi| 45 +++
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c |
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 50 ++
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops-nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mtd/nand/omap2.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
On Fri, Aug 07, 2015 at 10:41:57AM +0200, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the
Fix omap_dss_find_output_by_port_node() port parameter refcount
decrementation. The only user of dss_of_port_get_parent_device()
function is omap_dss_find_output_by_port_node() and it assumes the
refcount of the port parameter is not decremented by the call.
Signed-off-by: Jyri Sarha
On 7 August 2015 at 10:25, Martin Sperl mar...@sperl.org wrote:
On 8/6/2015 23:33, Russell King - ARM Linux wrote:
On Thu, Aug 06, 2015 at 06:14:00PM +0200, Geert Uytterhoeven wrote:
Irrespective of the dummy bytes.
What if the spi device is not a FLASH ROM, but some other device,
which
On 08/07/2015 11:44 AM, Peter Ujfalusi wrote:
On 08/07/2015 11:41 AM, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX
Hi,
On 06/08/15 21:41, Jyri Sarha wrote:
The only user of dss_of_port_get_parent_device() function is
omap_dss_find_output_by_port_node() and it assumes the refcount of the
port parameter is not decremented by the call.
The subject of the patch should contain dss-of, not of-dss. Although
On Fri, Aug 7, 2015 at 12:16 PM, Yegor Yefremov
yegorsli...@googlemail.com wrote:
On Thu, Aug 6, 2015 at 4:21 PM, Felipe Balbi ba...@ti.com wrote:
HI,
On Thu, Aug 06, 2015 at 09:40:26AM +0200, Yegor Yefremov wrote:
I performed a stress test with several FT4232H chips connected to a
how many
On 06/08/15 21:41, Jyri Sarha wrote:
Signed-off-by: Jyri Sarha jsa...@ti.com
Please always fill in the patch description. In simplest cases it may be
the same as in the subject.
---
drivers/video/fbdev/omap2/dss/dss-of.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On 08/07/2015 11:41 AM, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the DMA controller
On Thu, Aug 6, 2015 at 4:21 PM, Felipe Balbi ba...@ti.com wrote:
HI,
On Thu, Aug 06, 2015 at 09:40:26AM +0200, Yegor Yefremov wrote:
I performed a stress test with several FT4232H chips connected to a
how many ?
# lsusb -t
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=musb-hdrc/1p, 480M
Fix node refcount leak in omapdss_of_get_next_port().
Signed-off-by: Jyri Sarha jsa...@ti.com
---
drivers/video/fbdev/omap2/dss/dss-of.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/video/fbdev/omap2/dss/dss-of.c
b/drivers/video/fbdev/omap2/dss/dss-of.c
index 928ee63..ab6ef16
Changes since the first version:
- Fix commit descriptions and subject according to Tomi's comments
I found couple of refcounting issues related to OMAP DSS of-node
handling. Second patch should fix the ERROR: Bad of_node_put() on
/encoder@0/ports/port@1 -problem.
In the long run it would make
On Fri, Aug 07, 2015 at 05:36:05PM +0200, Sebastian Andrzej Siewior wrote:
+ /*
+ * We do not allow DMA_MEM_TO_DEV transfers to be paused.
+ * According to RMK the OMAP hardware might prefetch bytes from
+ * memory into its FIFO and not send
On Fri, Aug 07, 2015 at 06:20:44PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 06:07 PM, Peter Hurley wrote:
If we look at what 8250-dma.c is doing:
if (dma-rx_running) {
dmaengine_pause(dma-rxchan);
It's 8250-dma.c which is silently
On Fri, Aug 07, 2015 at 11:08:48AM -0400, Peter Hurley wrote:
[ + Greg KH ]
On 08/07/2015 09:57 AM, Russell King - ARM Linux wrote:
As it is something that the driver has _not_ supported, you are clearly
adding a feature to an existing driver. It's not a bug fix.
If something else
Hi Peter,
On Friday 07 August 2015 05:18 PM, Peter Robinson wrote:
On Wed, Aug 5, 2015 at 11:00 AM, Tony Lindgren t...@atomide.com wrote:
* Grygorii Strashko grygorii.stras...@ti.com [150729 02:01]:
On 07/27/2015 03:16 PM, Kishon Vijay Abraham I wrote:
pbias device creation got broken once
On 08/07/2015 09:25 AM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 03:22:56PM +0200, Sebastian Andrzej Siewior wrote:
For TX-transfers, I would need to update the start-address so the
transfers begins where it stopped. However based on your concern I
can't really assume that the
On 08/07/2015 06:07 PM, Peter Hurley wrote:
If we look at what 8250-dma.c is doing:
if (dma-rx_running) {
dmaengine_pause(dma-rxchan);
It's 8250-dma.c which is silently _ignoring_ the return code, failing
to check that the operation it requested
On Fri, Aug 07, 2015 at 05:44:03PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 05:29 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 11:08:48AM -0400, Peter Hurley wrote:
[ + Greg KH ]
On 08/07/2015 09:57 AM, Russell King - ARM Linux wrote:
As it is something that
On 08/06/2015 11:38 PM, Ryan wrote:
Hi,
I am using a 4460 Based custom board i want to debug linux using
Trace32. Could anyone share the cmm files required for debugging
omap4460.
I also request you to share any related documentation for debugging
omap using trace32.
You need to talk
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the DMA controller starts the transfer shortly after.
Before we can manually purge
On 08/07/2015 11:29 AM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 11:08:48AM -0400, Peter Hurley wrote:
[ + Greg KH ]
On 08/07/2015 09:57 AM, Russell King - ARM Linux wrote:
As it is something that the driver has _not_ supported, you are clearly
adding a feature to an existing
* Russell King - ARM Linux | 2015-08-07 17:26:48 [+0100]:
On Fri, Aug 07, 2015 at 05:36:05PM +0200, Sebastian Andrzej Siewior wrote:
+/*
+ * We do not allow DMA_MEM_TO_DEV transfers to be paused.
+ * According to RMK the OMAP hardware might prefetch bytes
On Fri, Aug 07, 2015 at 02:21:59PM -0400, Peter Hurley wrote:
[ + Heikki ]
On 08/07/2015 12:33 PM, Russell King - ARM Linux wrote:
What you have is a race condition in the code you a responsible for
maintaining, caused by poorly implemented code. Fix it, rather than
whinging about
On Fri, Aug 07, 2015 at 01:23:20PM -0400, Peter Hurley wrote:
The omap-serial driver which doesn't use dma is still the preferred
stable driver for omap, for the moment.
One of the main features of the 8250_omap integration was the addition
of dma support. Without it, 8250_omap is ttyO in
On 08/07/2015 12:39 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 05:44:03PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 05:29 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 11:08:48AM -0400, Peter Hurley wrote:
[ + Greg KH ]
On 08/07/2015 09:57 AM,
On Fri, Aug 07, 2015 at 10:41:57AM +0200, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the
[ + Heikki ]
On 08/07/2015 12:33 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 12:07:11PM -0400, Peter Hurley wrote:
On 08/07/2015 11:29 AM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 11:08:48AM -0400, Peter Hurley wrote:
[ + Greg KH ]
On 08/07/2015 09:57 AM,
On Fri, Aug 07, 2015 at 07:55:48PM +0200, Sebastian Andrzej Siewior wrote:
/*
* We do not allow DMA_MEM_TO_DEV transfers to be paused.
* From the AM572x TRM, 16.1.4.18 Disabling a Channel During Transfer:
* When a channel is disabled during a transfer, the channel undergoes
* an abort,
Hi,
On Thursday 06 August 2015 12:18 PM, Tony Lindgren wrote:
* Kishon Vijay Abraham I kis...@ti.com [150805 08:03]:
Hi,
On Wednesday 05 August 2015 04:13 PM, Tony Lindgren wrote:
* Kishon Vijay Abraham I kis...@ti.com [150730 00:49]:
Patch series implements voltage switching and tuning for
[ + Greg KH ]
On 08/07/2015 09:57 AM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 03:42:06PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015 03:22 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 12:36:14PM +0200, Sebastian Andrzej Siewior wrote:
On 08/07/2015
On 08/07/2015 05:29 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 11:08:48AM -0400, Peter Hurley wrote:
[ + Greg KH ]
On 08/07/2015 09:57 AM, Russell King - ARM Linux wrote:
As it is something that the driver has _not_ supported, you are clearly
adding a feature to an existing
On Fri, Aug 07, 2015 at 12:07:11PM -0400, Peter Hurley wrote:
On 08/07/2015 11:29 AM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 11:08:48AM -0400, Peter Hurley wrote:
[ + Greg KH ]
On 08/07/2015 09:57 AM, Russell King - ARM Linux wrote:
As it is something that the driver
In 8250-omap I learned it the hard way that ignoring the return code
of dmaengine_pause() might be bad because the underlying DMA driver
might not support the function at all and so not doing what one is
expecting.
This patch adds the __must_check annotation as suggested by Russell King.
#1 is something that can go stable and disables RX-DMA should it
notice that it does not work.
#2 adds the anotation as suggest by Russell.
#3 adds the missing feature to omap-dma so dmaengine_pause() works. Once
this is merged, the warning from #1 disappears.
--
To unsubscribe from this
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the DMA controller starts the transfer shortly after.
Before we can manually purge
On 08/07/2015 01:44 PM, Peter Ujfalusi wrote:
Cc: sta...@vger.kernel.org
Why stable? This is not fixing any bugs since the PAUSE was not allowed for
non cyclic transfers.
Hmmm. The DRA7x was using pause before for UART. I just did not see it
coming that it was not allowed here. John made a
On 08/07/2015 01:36 PM, Sebastian Andrzej Siewior wrote:
On 08/07/2015 11:44 AM, Peter Ujfalusi wrote:
On 08/07/2015 11:41 AM, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the
On Wed, Aug 5, 2015 at 11:00 AM, Tony Lindgren t...@atomide.com wrote:
* Grygorii Strashko grygorii.stras...@ti.com [150729 02:01]:
On 07/27/2015 03:16 PM, Kishon Vijay Abraham I wrote:
pbias device creation got broken once SCM cleanup got merged.
This patch series re-enables device creation
On 08/07/2015 12:55 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 10:41:57AM +0200, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that
On 08/07/2015 04:00 PM, Sebastian Andrzej Siewior wrote:
The 8250-omap driver requires the DMA-engine driver to support the pause
command in order to properly turn off programmed RX transfer before the
driver stars manually reading from the FIFO.
The lacking support of the requirement has been
On 08/07/2015 04:00 PM, Sebastian Andrzej Siewior wrote:
In 8250-omap I learned it the hard way that ignoring the return code
of dmaengine_pause() might be bad because the underlying DMA driver
might not support the function at all and so not doing what one is
expecting.
This patch adds the
On 08/07/2015 02:32 PM, Russell King - ARM Linux wrote:
On Fri, Aug 07, 2015 at 02:21:59PM -0400, Peter Hurley wrote:
[ + Heikki ]
On 08/07/2015 12:33 PM, Russell King - ARM Linux wrote:
What you have is a race condition in the code you a responsible for
maintaining, caused by poorly
83 matches
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