Paul Walmsley p...@pwsan.com writes:
On Thu, 26 Nov 2009, Thara Gopinath wrote:
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath th...@ti.com
Cc: Kevin Hilman
On Thu, 26 Nov 2009, Thara Gopinath wrote:
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath th...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Thanks Thara, will
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath th...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
arch/arm/mach-omap2/powerdomain.c |6 ++
: Re: [PATCH V2] OMAP3: PM: Fix for MPU power domain MEM BANK
position
Hi Thara,
I regret the delay. A comment:
On Fri, 28 Aug 2009, Thara Gopinath wrote:
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from
Hi Thara,
I regret the delay. A comment:
On Fri, 28 Aug 2009, Thara Gopinath wrote:
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Indeed. What do you think about a slightly different approach:
Thara Gopinath th...@ti.com writes:
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath th...@ti.com
---
Patch refresh issue.
arch/arm/mach-omap2/powerdomain.c | 19
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath th...@ti.com
---
Patch refresh issue.
arch/arm/mach-omap2/powerdomain.c | 19 +++
1 files changed, 19
