On Thu, Apr 23, 2015 at 07:17:28AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [150423 03:26]:
However, I don't think anyone is willing to say that they have a
solution to this problem - obviously, you can't build OMAP as a
non-multiplatform kernel anymore,
On Fri, Apr 24, 2015 at 10:54:29AM +0200, Matthijs van Duin wrote:
On 23 April 2015 at 12:25, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
And you can't detect whether you're running in secure mode or not.
If not, you get an undefined instruction exception, which you could trap.
On 23 April 2015 at 12:25, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
And you can't detect whether you're running in secure mode or not.
If not, you get an undefined instruction exception, which you could trap.
This may not be convenient, but can't detect is an overstatement.
* Russell King - ARM Linux li...@arm.linux.org.uk [150423 03:26]:
On Mon, Apr 20, 2015 at 04:40:32PM -0700, Tony Lindgren wrote:
* Sebastian Reichel s...@kernel.org [150417 11:43]:
On Thu, Apr 16, 2015 at 09:08:58AM -0700, Tony Lindgren wrote:
* Sebastian Reichel s...@kernel.org [150415
On Mon, Apr 20, 2015 at 04:40:32PM -0700, Tony Lindgren wrote:
* Sebastian Reichel s...@kernel.org [150417 11:43]:
On Thu, Apr 16, 2015 at 09:08:58AM -0700, Tony Lindgren wrote:
* Sebastian Reichel s...@kernel.org [150415 09:32]:
Hi,
On Thu, Apr 09, 2015 at 02:48:43PM +0100,
* Sebastian Reichel s...@kernel.org [150417 11:43]:
On Thu, Apr 16, 2015 at 09:08:58AM -0700, Tony Lindgren wrote:
* Sebastian Reichel s...@kernel.org [150415 09:32]:
Hi,
On Thu, Apr 09, 2015 at 02:48:43PM +0100, Russell King - ARM Linux wrote:
On Thu, Apr 09, 2015 at 12:06:58AM
On Thu, Apr 16, 2015 at 09:08:58AM -0700, Tony Lindgren wrote:
* Sebastian Reichel s...@kernel.org [150415 09:32]:
Hi,
On Thu, Apr 09, 2015 at 02:48:43PM +0100, Russell King - ARM Linux wrote:
On Thu, Apr 09, 2015 at 12:06:58AM +0100, Russell King - ARM Linux wrote:
On Tue, Apr 07,
* Sebastian Reichel s...@kernel.org [150415 09:32]:
Hi,
On Thu, Apr 09, 2015 at 02:48:43PM +0100, Russell King - ARM Linux wrote:
On Thu, Apr 09, 2015 at 12:06:58AM +0100, Russell King - ARM Linux wrote:
On Tue, Apr 07, 2015 at 08:22:08AM -0700, Tony Lindgren wrote:
Works for me. The
On 10 April 2015 at 00:37, Grazvydas Ignotas nota...@gmail.com wrote:
May I ask how do you perform the smc call?
A point worth mentioning is that TI advises that r1-r4 may be
clobbered in general, and at least on GP dm814x and am335x devices r4
is in fact clobbered, even though it is normally a
Hi,
On Thu, Apr 09, 2015 at 02:48:43PM +0100, Russell King - ARM Linux wrote:
On Thu, Apr 09, 2015 at 12:06:58AM +0100, Russell King - ARM Linux wrote:
On Tue, Apr 07, 2015 at 08:22:08AM -0700, Tony Lindgren wrote:
Works for me. The above needs the following fix folded in to build:
On Fri, Apr 10, 2015 at 1:44 AM, Tony Lindgren t...@atomide.com wrote:
* Grazvydas Ignotas nota...@gmail.com [150409 15:37]:
On Tue, Apr 7, 2015 at 5:23 AM, Tony Lindgren t...@atomide.com wrote:
* Matthijs van Duin matthijsvand...@gmail.com [150406 11:15]:
On 6 April 2015 at 19:42, Tony
* Grazvydas Ignotas nota...@gmail.com [150410 15:06]:
On Fri, Apr 10, 2015 at 1:44 AM, Tony Lindgren t...@atomide.com wrote:
* Grazvydas Ignotas nota...@gmail.com [150409 15:37]:
On Tue, Apr 7, 2015 at 5:23 AM, Tony Lindgren t...@atomide.com wrote:
* Matthijs van Duin
On Thu, Apr 09, 2015 at 08:09:19AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [150409 06:49]:
On Thu, Apr 09, 2015 at 12:06:58AM +0100, Russell King - ARM Linux wrote:
On Tue, Apr 07, 2015 at 08:22:08AM -0700, Tony Lindgren wrote:
Works for me. The
* Russell King - ARM Linux li...@arm.linux.org.uk [150409 06:49]:
On Thu, Apr 09, 2015 at 12:06:58AM +0100, Russell King - ARM Linux wrote:
On Tue, Apr 07, 2015 at 08:22:08AM -0700, Tony Lindgren wrote:
Works for me. The above needs the following fix folded in to build:
---
On Thu, Apr 09, 2015 at 12:06:58AM +0100, Russell King - ARM Linux wrote:
On Tue, Apr 07, 2015 at 08:22:08AM -0700, Tony Lindgren wrote:
Works for me. The above needs the following fix folded in to build:
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -532,7 +532,7 @@
* Russell King - ARM Linux li...@arm.linux.org.uk [150408 16:09]:
On Tue, Apr 07, 2015 at 08:44:05AM -0700, Tony Lindgren wrote:
And then on top of that patch, we can fix the sefaulting issues with the
following, what do you guys think?
Has this change been tested on OMAP secure parts?
On Tue, Apr 07, 2015 at 08:22:08AM -0700, Tony Lindgren wrote:
Works for me. The above needs the following fix folded in to build:
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -532,7 +532,7 @@ __v7_ca9mp_proc_info:
__v7_ca8_proc_info:
.long 0x410fc080
.long
On Tue, Apr 07, 2015 at 08:44:05AM -0700, Tony Lindgren wrote:
And then on top of that patch, we can fix the sefaulting issues with the
following, what do you guys think?
Has this change been tested on OMAP secure parts?
8
From: Tony Lindgren t...@atomide.com
Date: Tue,
On Mon, Apr 06, 2015 at 10:42:45AM -0700, Tony Lindgren wrote:
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150406 10:15]:
On 6.04.2015 18:40, Tony Lindgren wrote:
Oops sorry, wrong numbers for errata above.. s/458693/430973/, here's
a better version:
1. For cortex-a8 revisions
On Mon, Apr 06, 2015 at 08:14:30PM +0200, Matthijs van Duin wrote:
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150406 10:15]:
Why custom function, if IBE bit is zero, BTB invalidate instruction is a
NOP. Do you think that mcr p15, 0, r2, c7, c5, 6 executed as a NOP will
put so much
* Matthijs van Duin matthijsvand...@gmail.com [150406 20:50]:
On 7 April 2015 at 04:23, Tony Lindgren t...@atomide.com wrote:
Oops, sorry user error.. I was trying to clear IBE as a banked register
like L2 enable bit and of course it did not get cleared.. Clearing it
with a smc call really
* Russell King - ARM Linux li...@arm.linux.org.uk [150407 06:58]:
On Mon, Apr 06, 2015 at 10:42:45AM -0700, Tony Lindgren wrote:
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150406 10:15]:
On 6.04.2015 18:40, Tony Lindgren wrote:
Oops sorry, wrong numbers for errata above..
* Tony Lindgren t...@atomide.com [150407 08:27]:
* Russell King - ARM Linux li...@arm.linux.org.uk [150407 06:58]:
Well, one thing we can do is to tweak the proc-v7*.S such that we detect
Cortex-A8 separately, and only execute the BTB flush for CA8 processors
if the errata is enabled.
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150406 10:15]:
On 6.04.2015 18:40, Tony Lindgren wrote:
Oops sorry, wrong numbers for errata above.. s/458693/430973/, here's
a better version:
1. For cortex-a8 revisions affected by 430973, we can do a custom
cpu_v7_switch_mm function
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150406 10:15]:
Why custom function, if IBE bit is zero, BTB invalidate instruction is a
NOP. Do you think that mcr p15, 0, r2, c7, c5, 6 executed as a NOP will
put so much overhead, that it deserves a custom function?
Executing them as nop is
Hi,
On Sun, Apr 05, 2015 at 03:52:10PM +0200, Pali Rohár wrote:
So I suggest to enable the IBE bit in the kernel (that part is
already done) *and* in u-boot.
-- Sebastian
Yes. Code for both (U-Boot and linux kernel) exists and are
already included.
In linux kernel code is since
* Matthijs van Duin matthijsvand...@gmail.com [150406 11:15]:
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150406 10:15]:
Why custom function, if IBE bit is zero, BTB invalidate instruction is a
NOP. Do you think that mcr p15, 0, r2, c7, c5, 6 executed as a NOP will
put so much overhead,
Hi,
On Mon, Apr 06, 2015 at 07:23:13PM -0700, Tony Lindgren wrote:
I'm now thinking the kernel should just always set the 430973 specific
cpu_v7_switch_mm for all cortex-a8 if IBE bit is set. That avoids
the whole mess of early SoC detection and smc calls. And if IBE bit
is not set, then we
On 7 April 2015 at 04:23, Tony Lindgren t...@atomide.com wrote:
Oops, sorry user error.. I was trying to clear IBE as a banked register
like L2 enable bit and of course it did not get cleared.. Clearing it
with a smc call really clears it. And in that case my test case seems to
work reliably
* Matthijs van Duin matthijsvand...@gmail.com [150405 16:53]:
Cortex-A8 errata doc states in its workaround for erratum 430973:
By default, the BTB Invalidate instruction is treated as a NOP on Cortex-A8.
However, it is possible to enable the BTB Invalidate instruction such that
it
* Sebastian Reichel s...@kernel.org [150405 06:40]:
Hi,
On Sun, Apr 05, 2015 at 06:13:47AM +0200, Matthijs van Duin wrote:
On 4 April 2015 at 00:52, Tony Lindgren t...@atomide.com wrote:
Right, it affects n900 for sure. My point is that it also seems to
affect 37xx versions not listed
* Tony Lindgren t...@atomide.com [150406 08:24]:
* Matthijs van Duin matthijsvand...@gmail.com [150405 16:53]:
Cortex-A8 errata doc states in its workaround for erratum 430973:
By default, the BTB Invalidate instruction is treated as a NOP on
Cortex-A8.
However, it is possible to
On 6.04.2015 18:40, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150406 08:24]:
* Matthijs van Duin matthijsvand...@gmail.com [150405 16:53]:
Cortex-A8 errata doc states in its workaround for erratum 430973:
By default, the BTB Invalidate instruction is treated as a NOP on
Cortex-A8 errata doc states in its workaround for erratum 430973:
By default, the BTB Invalidate instruction is treated as a NOP on Cortex-A8.
However, it is possible to enable the BTB Invalidate instruction such that it
actually does a full invalidate of the BTB by setting the IBE bit (bit 6)
On 5.04.2015 19:50, Matthijs van Duin wrote:
On 5 April 2015 at 09:23, Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com wrote:
Though I wonder why SMC is needed to write ACR on non-HS devices. A simple
MRC should suffice, unless I miss something.
Public-world access to ACR varies per bit:
bit 1
On Fri, Apr 03, 2015 at 02:21:48PM -0500, Robert Nelson wrote:
And yes, for armhf userland one gets random oopses at least on the
Nokia N900. AFAIK this is not true for all ARMv7 processors
(especially non omaps), though.
http://www.spinics.net/lists/linux-omap/msg108511.html
See
Hi,
On Sun, Apr 05, 2015 at 03:26:14PM +0200, Pali Rohár wrote:
Yes so it seems, and the bootloaders should really set it.
It's also disabled for multiplatform builds.
These are now done in u-boot as of: v2015.04-rc4
On Sunday 05 April 2015 15:00:45 Sebastian Reichel wrote:
On Fri, Apr 03, 2015 at 02:21:48PM -0500, Robert Nelson wrote:
And yes, for armhf userland one gets random oopses at
least on the Nokia N900. AFAIK this is not true for all
ARMv7 processors (especially non omaps), though.
Hi,
On Sun, Apr 05, 2015 at 06:13:47AM +0200, Matthijs van Duin wrote:
On 4 April 2015 at 00:52, Tony Lindgren t...@atomide.com wrote:
Right, it affects n900 for sure. My point is that it also seems to
affect 37xx versions not listed to suffer from this issue.
They shouldn't... erratum
On Sunday 05 April 2015 15:45:28 Sebastian Reichel wrote:
Hi,
On Sun, Apr 05, 2015 at 03:26:14PM +0200, Pali Rohár wrote:
Yes so it seems, and the bootloaders should really set
it. It's also disabled for multiplatform builds.
These are now done in u-boot as of: v2015.04-rc4
On 5.04.2015 07:13, Matthijs van Duin wrote:
I would actually suggest clearing IBE if it set on Cortex-A8 r2 or
later processors and a secure monitor call is available to do so
(there is on the DM814x and AM335x, dunno about the 37xx), also for
performance reasons: BTB invalidates are quite
On 5 April 2015 at 18:50, Matthijs van Duin matthijsvand...@gmail.com wrote:
MRC
I mean MCR of course
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On 5 April 2015 at 09:23, Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com wrote:
Though I wonder why SMC is needed to write ACR on non-HS devices. A simple
MRC should suffice, unless I miss something.
Public-world access to ACR varies per bit:
bit 1 (L2EN) is documented as banked, but at least on
On 4 April 2015 at 00:52, Tony Lindgren t...@atomide.com wrote:
Right, it affects n900 for sure. My point is that it also seems to
affect 37xx versions not listed to suffer from this issue.
They shouldn't... erratum 430973 only affected Cortex-A8 r1, and the
dm37xx should have an r3p2 right?
A
* Sebastian Reichel s...@kernel.org [150403 09:37]:
Hi,
On Wed, Apr 01, 2015 at 12:47:36PM -0700, Tony Lindgren wrote:
OK I think debian is using v3.16 kernel
Yes. It will be used for Debian jessie (not yet released) and the
N900 related drivers are enabled in the armmp flavour.
Hi,
On Wed, Apr 01, 2015 at 12:47:36PM -0700, Tony Lindgren wrote:
OK I think debian is using v3.16 kernel
Yes. It will be used for Debian jessie (not yet released) and the
N900 related drivers are enabled in the armmp flavour. Unfortunately
it does not work together with thumb using
And yes, for armhf userland one gets random oopses at least on the
Nokia N900. AFAIK this is not true for all ARMv7 processors
(especially non omaps), though.
http://www.spinics.net/lists/linux-omap/msg108511.html
See also 5c86c5339c56 (ARM: omap2plus_defconfig: Enable ARM erratum
Hi!
Maybe an option would be to provide two cpu_v7_switch_mm
implementations (one with the errata and one without). Then
the system can start with the simple implementation. Once
the boot as progressed far enough to know, that the hardware
is affected by the errata, it could switch to the
Hi
On 3.04.2015 19:35, Sebastian Reichel wrote:
Maybe an option would be to provide two cpu_v7_switch_mm
implementations (one with the errata and one without). Then
the system can start with the simple implementation. Once
the boot as progressed far enough to know, that the hardware
is
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150403 15:08]:
Hi
On 3.04.2015 19:35, Sebastian Reichel wrote:
Maybe an option would be to provide two cpu_v7_switch_mm
implementations (one with the errata and one without). Then
the system can start with the simple implementation. Once
* Ivaylo Dimitrov ivo.g.dimitrov...@gmail.com [150403 15:47]:
Hi,
We should first verify the same bug happens with armel also.
I just verified the CPU load in the background makes armhf
apps segfault without $subject workaround enabled.
If the segfaulting does not happen with armel,
Hi,
We should first verify the same bug happens with armel also.
I just verified the CPU load in the background makes armhf
apps segfault without $subject workaround enabled.
If the segfaulting does not happen with armel, then chances
it's some kind of neon related issue and the fix can be
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