Hi,
On 05/10/13 05:51, Javier Martinez Canillas wrote:
IGEPv2 board has both an DVI and TFP410 video interfaces but
DSS support for DeviceTree has not yet landed in mainline so
is necessary to init the displays using legacy platform code.
Signed-off-by: Javier Martinez Canillas
Hi Tony,
On 09/10/13 00:11, Tony Lindgren wrote:
* Javier Martinez Canillas javier.marti...@collabora.co.uk [131004 20:00]:
IGEPv2 board has both an DVI and TFP410 video interfaces but
DSS support for DeviceTree has not yet landed in mainline so
is necessary to init the displays using legacy
Some temporary issues with my mua so forgive any artifacts in this email.
On Oct 9, 2013, at 12:14 AM, Hebbar, Gururaja gururaja.heb...@ti.com wrote:
On Wednesday 09 October 2013 09:58 AM, Joel Fernandes wrote:
On 10/01/2013 10:04 AM, Daniel Mack wrote:
This patch makes the edma driver resume
On Wednesday 09 October 2013 11:33 AM, Fernandes, Joel wrote:
Some temporary issues with my mua so forgive any artifacts in this email.
On Oct 9, 2013, at 12:14 AM, Hebbar, Gururaja gururaja.heb...@ti.com
wrote:
On Wednesday 09 October 2013 09:58 AM, Joel Fernandes wrote:
On 10/01/2013
* Daniel Mack | 2013-10-01 15:31:08 [+0200]:
Patch #1 restores more registers on resume time.
Patch #2 is a cosmetic cleanup that emerged while digging through the
driver and gaining a basic idea of how it's implemented. Nothing fancy.
I'm fine with those two.
Patch #3, however, gives me
On Tue, 8 Oct 2013, Roger Quadros wrote:
Add hwmod data for High Speed USB host and TLL modules
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Roger Quadros rog...@ti.com
Thanks, queued.
- Paul
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Hi Roger,
On Thu, 21 Mar 2013, Roger Quadros wrote:
+Paul
On 03/21/2013 03:48 PM, Roger Quadros wrote:
If the bootloader doesn't configure USB DPLL (e.g. in u-boot,
disable CONFIG_USB_EHCI_OMAP), then we get all sorts of problems
like
- division by zero errors at boot [1]
- USB
On 10/09/2013 10:05 AM, Paul Walmsley wrote:
Hi Roger,
On Thu, 21 Mar 2013, Roger Quadros wrote:
+Paul
On 03/21/2013 03:48 PM, Roger Quadros wrote:
If the bootloader doesn't configure USB DPLL (e.g. in u-boot,
disable CONFIG_USB_EHCI_OMAP), then we get all sorts of problems
like
-
Hi Tony,
On 10/08/2013 01:06 PM, Roger Quadros wrote:
This reverts commit 741532c4a995be11815cb72d4d7a48f442a22fea.
The proper clock reference is provided in device tree so we
no longer need this.
Could you please Ack this one? I think it is best if it goes through Benoit's
tree.
cheers,
On Tue, 17 Sep 2013, Suman Anna wrote:
Add the missing sysc configuration to the AM335 spinlock hwmod
data. This ensures that smart-idle is enabled whenever the module
is enabled by the driver.
Signed-off-by: Suman Anna s-a...@ti.com
Thanks, queued. You can omit this one from future
On Tue, 17 Sep 2013, Suman Anna wrote:
Add the hwmod data for the spinlock IP in OMAP5 SoC.
This is needed to be able to enable the OMAP spinlock
support for OMAP5.
Signed-off-by: Suman Anna s-a...@ti.com
Thanks, queued. You can omit this one from future reposts of this series.
- Paul
AM43x has 224 interrupts and 7 banks, make it as maximum values. Keep
default values as earlier, if am43x is detected, update interrupts and
banks accordingly.
Also AM43x has only one cpu, ensure that clearing bitmask at wakeupgen
is done only for the single existing cpu, existing code assumes
Hi Tony,
On Wednesday 09 October 2013 02:54 AM, Tony Lindgren wrote:
* Afzal Mohammed af...@ti.com [130905 04:03]:
-#define MAX_NR_REG_BANKS5
-#define MAX_IRQS160
+/* maximum value correspond to that of AM43x */
+#define MAX_NR_REG_BANKS7
+#define MAX_IRQS
On 09.10.2013 08:41, Sebastian Andrzej Siewior wrote:
* Daniel Mack | 2013-10-01 15:31:08 [+0200]:
Patch #1 restores more registers on resume time.
Patch #2 is a cosmetic cleanup that emerged while digging through the
driver and gaining a basic idea of how it's implemented. Nothing fancy.
Hi Benoît, Rajendra,
On Tue, 20 Aug 2013, Rajendra Nayak wrote:
Now that we have DT bindings to specify which devices on the SoC should not
be reset or idled, get rid of the same information existing as part of the
hwmod data files and pass this info from DT instead.
For GPMC, the
On 10/09/2013 09:23 AM, Daniel Mack wrote:
Ok, thank you very much for the update :) I can of course test
alternative patches if you have any.
Could you actually reproduce the issue I described by sending your board
to suspend?
No, I don't have mem, just freeze. I try to test if this is a
On 09.10.2013 09:28, Sebastian Andrzej Siewior wrote:
On 10/09/2013 09:23 AM, Daniel Mack wrote:
Ok, thank you very much for the update :) I can of course test
alternative patches if you have any.
Could you actually reproduce the issue I described by sending your board
to suspend?
No, I
On 10/09/2013 08:02 AM, Tomi Valkeinen wrote:
Hi Tony,
On 09/10/13 00:11, Tony Lindgren wrote:
* Javier Martinez Canillas javier.marti...@collabora.co.uk [131004 20:00]:
IGEPv2 board has both an DVI and TFP410 video interfaces but
DSS support for DeviceTree has not yet landed in mainline so
On Wednesday 09 October 2013 12:54 PM, Paul Walmsley wrote:
Hi Benoît, Rajendra,
On Tue, 20 Aug 2013, Rajendra Nayak wrote:
Now that we have DT bindings to specify which devices on the SoC should not
be reset or idled, get rid of the same information existing as part of the
hwmod data
Hi everyone,
On 09.10.2013 08:18, Gururaja Hebbar wrote:
On Wednesday 09 October 2013 11:33 AM, Fernandes, Joel wrote:
Some temporary issues with my mua so forgive any artifacts in this
email.
On Oct 9, 2013, at 12:14 AM, Hebbar, Gururaja
gururaja.heb...@ti.com wrote:
On Wednesday 09
On 10/09/2013 08:00 AM, Tomi Valkeinen wrote:
Hi,
Hi Tomi, thanks a lot for your feedback.
On 05/10/13 05:51, Javier Martinez Canillas wrote:
IGEPv2 board has both an DVI and TFP410 video interfaces but
DSS support for DeviceTree has not yet landed in mainline so
is necessary to init the
On 09/10/13 10:44, Javier Martinez Canillas wrote:
I can't do it yet because the two are still needed for different boot paths.
Once the board DTS has all the hardware support that is currently available on
the board file I'll delete the board file but until then I can't remove
anything
On 10/09/2013 09:47 AM, Tomi Valkeinen wrote:
On 09/10/13 10:44, Javier Martinez Canillas wrote:
I can't do it yet because the two are still needed for different boot paths.
Once the board DTS has all the hardware support that is currently available
on
the board file I'll delete the board
Ticket Number: 7PWYZ2008
Ballot Number: BT:12052008/20
Draw:#1471
Special Notification to you,You are receiving this email because you have just
been picked for a total grand prize of One Million Dollars in the top 10
winners of the Coca-Cola Consumer`s Award for the year 2013: kindly send
Hi Jyri,
On 10/08/2013 10:36 PM, Jyri Sarha wrote:
@@ -407,6 +442,25 @@
#include tps65910.dtsi
+mcasp1 {
+ pinctrl-names = default;
+ pinctrl-0 = am335x_evm_audio_pins;
+
+ status = okay;
+
+ op-mode = 0; /* MCASP_IIS_MODE
Hi Rajendra,
On 09/10/2013 09:37, Rajendra Nayak wrote:
On Wednesday 09 October 2013 12:54 PM, Paul Walmsley wrote:
Hi Benoît, Rajendra,
On Tue, 20 Aug 2013, Rajendra Nayak wrote:
Now that we have DT bindings to specify which devices on the SoC should not
be reset or idled, get rid of the
On 10/08/2013 10:36 PM, Jyri Sarha wrote:
This patch adds a second tuple to reg property. The new property tuple
describes the memory location for data port registers mapped trough
L3 bus on am33xx. The both property tuples are named accordingly in
the reg-names property.
Signed-off-by:
On 03/10/13 21:45, Richard Röjfors wrote:
There is currently a copy and paste error where the hdmi vsync timings are not
compared correctly, this patch fixes this.
Signed-off-by: Richard Röjfors richard.rojf...@gmail.com
---
diff --git a/drivers/video/omap2/dss/hdmi.c
On Wednesday 09 October 2013 01:49 PM, Benoit Cousson wrote:
Hi Rajendra,
On 09/10/2013 09:37, Rajendra Nayak wrote:
On Wednesday 09 October 2013 12:54 PM, Paul Walmsley wrote:
Hi Benoît, Rajendra,
On Tue, 20 Aug 2013, Rajendra Nayak wrote:
Now that we have DT bindings to specify which
Now that display information and setup is made from dss-common
there is no need to have this code in the board file.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- None, this is a new patch added for v3.
arch/arm/mach-omap2/board-igep0020.c |
Hi Tony,
This is a third version of the patch-set that adds legacy display init
for IGEPv2 boards that is needed to have display working when using DT.
You said to already had queued v2 on your omap-for-v3.13/quirk branch
but there were a few issues pointed out by Tomi Valkeinen that I addresed
IGEPv2 board has both an DVI and TFP410 video interfaces but
DSS support for DeviceTree has not yet landed in mainline so
is necessary to init the displays using legacy platform code.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- Don't mix
On 09/10/13 12:19, Javier Martinez Canillas wrote:
Now that display information and setup is made from dss-common
there is no need to have this code in the board file.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- None, this is a new
Changes in v2:
* Patches are split in such a way that DT and hwmod changes are kept in
seperate patches so they can be pulled in by Benoit and Paul seperately.
* Binding names are slightly updated to address the concern from Tony and
Benoit [1]
* Added a patch [5/5] to prevent GPIO reset on
Now that we have DT bindings to specify which devices should not
be reset and idled during init, make hwmod extract the information
(and store them in internal flags) from Device tree.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 23 ---
Do not reset GPIO0 at boot-up because GPIO0 is used
on AM335x EVM-SK to control VTT regulators on DDR3.
Without this EVM-SK boards fail to boot-up because
of DDR3 corruption.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/boot/dts/am335x-evmsk.dts |4
1 file changed, 4
For modules/IPs/hwmods which do not have
-1- sys-class-reset()
and
-2- hardreset lines
and
-3- No way to do an ocp reset (no sysc control)
the flag 'HWMOD_INIT_NO_RESET' is not much useful.
Cleanup all such instances across various hwmod data files.
Signed-off-by: Rajendra Nayak rna...@ti.com
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to
With DT bindings to specify which devices should not be idled and reset
at init being in place, and the corresponding dtsi files for am33xx/omap4
and omap5 updated using those bindings, we can now clean up hwmod internal
flags for HWMOD_INIT_NO_RESET and HWMOD_INIT_NO_IDLE which were infact used
This patch fixes MCSPI FIFO buffer support when transmit-and-receive
(full duplex) mode is used. In this mode FIFO can be used for RX or
for TX or for both directions. If FIFO used for both directions the buffer
is split into two 32-byte buffers - one for each direction.
Also for full duplex mode
From: Jyri Sarha jsa...@ti.com
This patch adds a second tuple to reg property. The new property tuple
describes the memory location for data port registers mapped trough
L3 bus on am33xx. The both property tuples are named accordingly in
the reg-names property.
Signed-off-by: Hebbar, Gururaja
From: Darren Etheridge detheri...@ti.com
Adds sound, tlv320aic3106, mcasp1, and am335x_evm_audio_pin nodes.
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Jyri Sarha jsa...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 51
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/cclock44xx_data.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On 10/07/2013 11:25 AM, Balaji T K wrote:
Add mmc2 dt node to dra7-evm board
and model eMMC vcc as fixed regulator.
Signed-off-by: Balaji T K balaj...@ti.com
---
Rebase to for_3.13/dts
and removed ti,non-removable
arch/arm/boot/dts/dra7-evm.dts | 13 +
1 files changed,
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.
I believe the same issue is there for other dpll4_mx_ck clocks, but as
I'm not familiar with them,
Set CLK_SET_RATE_PARENT flag for dss1_alwon_fck_3430es2,
dss1_alwon_fck_3430es1 and dpll4_m4x2_ck so that the DSS's fclk can be
configured without the need to get the parent's parent of the fclk.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/cclock3xxx_data.c | 14
On 10/07/2013 11:25 AM, Balaji T K wrote:
Add mmc1 dt node to dra7-evm board.
Input for ldo1 regulator is controlled by gpio 5 of pcf8575 chip (0x21)
on i2c1 bus. When dt support for gpio-pcf857x is available, input supply
will be modelled as cascaded regulator.
Signed-off-by: Balaji T K
Santosh,
On Wednesday 09 October 2013 03:35 AM, Santosh Shilimkar wrote:
On Tuesday 08 October 2013 05:45 PM, Tony Lindgren wrote:
* Sricharan R r.sricha...@ti.com [131003 03:27]:
On Wednesday 18 September 2013 09:32 PM, Sricharan R wrote:
--- a/arch/arm/boot/dts/omap5.dtsi
+++
On Wednesday 09 October 2013 06:45 PM, Sricharan R wrote:
Santosh,
On Wednesday 09 October 2013 03:35 AM, Santosh Shilimkar wrote:
On Tuesday 08 October 2013 05:45 PM, Tony Lindgren wrote:
* Sricharan R r.sricha...@ti.com [131003 03:27]:
On Wednesday 18 September 2013 09:32 PM, Sricharan R
On Wednesday 09 October 2013 09:16 AM, Sricharan R wrote:
On Wednesday 09 October 2013 06:45 PM, Sricharan R wrote:
Santosh,
On Wednesday 09 October 2013 03:35 AM, Santosh Shilimkar wrote:
On Tuesday 08 October 2013 05:45 PM, Tony Lindgren wrote:
* Sricharan R r.sricha...@ti.com [131003
On Wednesday 09 October 2013 09:15 AM, Sricharan R wrote:
Santosh,
On Wednesday 09 October 2013 03:35 AM, Santosh Shilimkar wrote:
On Tuesday 08 October 2013 05:45 PM, Tony Lindgren wrote:
* Sricharan R r.sricha...@ti.com [131003 03:27]:
On Wednesday 18 September 2013 09:32 PM, Sricharan R
On Wednesday 09 October 2013 06:47 PM, Santosh Shilimkar wrote:
On Wednesday 09 October 2013 09:15 AM, Sricharan R wrote:
Santosh,
On Wednesday 09 October 2013 03:35 AM, Santosh Shilimkar wrote:
On Tuesday 08 October 2013 05:45 PM, Tony Lindgren wrote:
* Sricharan R r.sricha...@ti.com
On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
I wouldn't touch this file right now, as we are trying to move the clock
data over to DT. Legacy boot support
On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.
I believe the same issue is there for other
On Wednesday 09 October 2013 09:20 AM, Sricharan R wrote:
On Wednesday 09 October 2013 06:47 PM, Santosh Shilimkar wrote:
On Wednesday 09 October 2013 09:15 AM, Sricharan R wrote:
Santosh,
On Wednesday 09 October 2013 03:35 AM, Santosh Shilimkar wrote:
On Tuesday 08 October 2013 05:45 PM,
On 09/10/13 16:22, Tero Kristo wrote:
On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.
I believe
On 09/10/13 16:22, Tero Kristo wrote:
On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
I wouldn't touch this file right now, as we are trying to move the clock
On 10/09/2013 04:33 PM, Tomi Valkeinen wrote:
On 09/10/13 16:22, Tero Kristo wrote:
On 10/09/2013 04:12 PM, Tomi Valkeinen wrote:
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables
On Mon, Oct 7, 2013 at 7:35 PM, Tony Lindgren t...@atomide.com wrote:
Hi Linus W,
Any comments on the pinctrl patches 3 - 5 in this series?
Yes, after good explanations to my whimsical questions only this:
Acked-by: Linus Walleij linus.wall...@linaro.org
I guess you'll take these patches
Hi Rob,
On Monday 07 October 2013 03:08 PM, Archit Taneja wrote:
With the new omapdss device model. The user(omapdrm/omapfb) of a omap_dss_device
has to call connect() to use the device. A connect() call can request to defer
probe if the device(or the previous entities in the chain) have
On 10/09/2013 02:38 AM, Daniel Mack wrote:
Hi everyone,
On 09.10.2013 08:18, Gururaja Hebbar wrote:
On Wednesday 09 October 2013 11:33 AM, Fernandes, Joel wrote:
Some temporary issues with my mua so forgive any artifacts in this
email.
On Oct 9, 2013, at 12:14 AM, Hebbar, Gururaja
On 10/09/2013 01:18 AM, Gururaja Hebbar wrote:
On Wednesday 09 October 2013 11:33 AM, Fernandes, Joel wrote:
Some temporary issues with my mua so forgive any artifacts in this email.
On Oct 9, 2013, at 12:14 AM, Hebbar, Gururaja gururaja.heb...@ti.com
wrote:
On Wednesday 09 October 2013
From: Darren Etheridge detheri...@ti.com
Adds sound, tlv320aic3106, mcasp1, and am335x_evm_audio_pin nodes.
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Jyri Sarha jsa...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 51
* Javier Martinez Canillas javier.marti...@collabora.co.uk [131009 00:45]:
On 10/09/2013 08:02 AM, Tomi Valkeinen wrote:
Hi Tony,
On 09/10/13 00:11, Tony Lindgren wrote:
* Javier Martinez Canillas javier.marti...@collabora.co.uk [131004
20:00]:
IGEPv2 board has both an DVI and
On Wed, 9 Oct 2013, Rajendra Nayak wrote:
For modules/IPs/hwmods which do not have
-1- sys-class-reset()
and
-2- hardreset lines
and
-3- No way to do an ocp reset (no sysc control)
the flag 'HWMOD_INIT_NO_RESET' is not much useful.
Cleanup all such instances across various hwmod data
On Wed, 9 Oct 2013, Rajendra Nayak wrote:
Now that we have DT bindings to specify which devices should not
be reset and idled during init, make hwmod extract the information
(and store them in internal flags) from Device tree.
Signed-off-by: Rajendra Nayak rna...@ti.com
Thanks, queued.
-
* Tomi Valkeinen tomi.valkei...@ti.com [131009 02:35]:
On 09/10/13 12:19, Javier Martinez Canillas wrote:
Now that display information and setup is made from dss-common
there is no need to have this code in the board file.
Signed-off-by: Javier Martinez Canillas
On Thu, 29 Aug 2013, Lokesh Vutla wrote:
Add RNG hwmod data for AM33xx SoC.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Thanks, queued.
- Paul
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More majordomo info
* Linus Walleij linus.wall...@linaro.org [131009 06:51]:
On Mon, Oct 7, 2013 at 7:35 PM, Tony Lindgren t...@atomide.com wrote:
Hi Linus W,
Any comments on the pinctrl patches 3 - 5 in this series?
Yes, after good explanations to my whimsical questions only this:
Acked-by: Linus
* Roger Quadros rog...@ti.com [131009 00:19]:
Hi Tony,
On 10/08/2013 01:06 PM, Roger Quadros wrote:
This reverts commit 741532c4a995be11815cb72d4d7a48f442a22fea.
The proper clock reference is provided in device tree so we
no longer need this.
Could you please Ack this one? I think
Hi Rajendra,
On 09/10/2013 12:11, Rajendra Nayak wrote:
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are
Hi all,
Version 8 has basically just some cosmetic changes + 2 functional ones.
Functional changes:
- patch #1: added support for am3-dpll-j-type-clock
- patch #20: added support for is_enabled op to APLL
- patch #34: fixed a typo in dpll_core_ck compatible string
Cosmetic fixes:
- new DT
This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific
This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
.../devicetree/bindings/clock/ti/dpll.txt | 83 +++
ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
Documentation/devicetree/bindings/clock/ti/mux.txt | 67
This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses composite clock type to implement the actual functionality.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
-
From: Roger Quadros rog...@ti.com
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock.h |1 -
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony
clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c |1 +
DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.
Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.
This patch also changes
Clock tree DT data is now included from base dra7.dtsi file.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/dra7.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
Initializes clock data from device tree.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/io.c
This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/omap5.dtsi | 14 +
clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/clk/ti/Makefile |1 +
If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony
From: J Keerthy j-keer...@ti.com
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren
From: J Keerthy j-keer...@ti.com
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
From: J Keerthy j-keer...@ti.com
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/io.c | 13 -
1 file
AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/Makefile |1 -
This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/am33xx-clocks.dtsi | 640
Clock tree data is now included from base am4372.dtsi file.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/am4372.dtsi |7 +++
1 file changed, 7 insertions(+)
diff --git
From: J Keerthy j-keer...@ti.com
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: J Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tested-by: Nishanth Menon n...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/clock3xxx.h |
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