On 5/4/2011 10:34 PM, Will Deacon wrote:
Hi Santosh,
On Wed, 2011-05-04 at 12:02 +0100, Santosh Shilimkar wrote:
Will,
Can you queue this patch part of your series please?
Yes, providing that Russell is happy to pull the IRQ stuff (fasteoi,
Tegra changes and this) from me.
Thanks.
Regards
On Wed, May 4, 2011 at 10:08 PM, Cousson, Benoit b-cous...@ti.com wrote:
(Cc folks with some DVFS interest)
Hi Colin,
On Fri, 22 Apr 2011, Colin Cross wrote:
Now that we are approaching a common clock management implementation,
I was thinking it might be the right place to put a common
On Thu, 5 May 2011, Cousson, Benoit wrote:
Those kinds of exceptions are somehow the rules for an OMAP4 device.
Most scalable devices are using some internal dividers or even internal
PLL to control the scalable clock rate (DSS, HSI, MMC, McBSP... the
OMAP4430 Data Manual [1] is providing
On Wed, 4 May 2011, Colin Cross wrote:
Imagine a chip where a clock can feed devices A, B, and C. If the
devices are always clocked at the same rate, and can't gate their
clocks, the minimum voltage that can be applied to a rail is
determined ONLY by the rate of the clock.
That's not so --
On Wed, May 4, 2011 at 11:35 PM, Paul Walmsley p...@pwsan.com wrote:
On Wed, 4 May 2011, Colin Cross wrote:
Imagine a chip where a clock can feed devices A, B, and C. If the
devices are always clocked at the same rate, and can't gate their
clocks, the minimum voltage that can be applied to a
This is to add support for HDMI audio on OMAP4 chips. This work has two
parts: DSS implementation and ASoC implementation. This set of patches
presents the DSS implementation. The approach is to utilize the DSS
HDMI driver to act as an ASoC codec. Then, functionality and data
structures are added
CTS and N parameters are used to regenerate the audio clock from
the TMDS clock at the HDMI sink. In OMAP4430 ES1.0 version
the calculation of the CTS parameter is done by the HDMI IP
(hardware mode) while in others it must be done by the HDMI driver
(software mode). A DSS feature is used to
Create a separate DSS features structure for OMAP4430 ES1.0. This
structure is used to expose features only present in such
silicon version. Specifically, this is required to handle how
the HDMI IP calculates the CTS parameter for audio clock
regeneration packets. OMAP4430 ES1.0 is the only one
Add functionality for relevant audio configuration. Functions to
configure the audio FIFO and DMA as well as functions for the audio
core and Audio Info frame are included. This functionality is to
be used by the ASoC HDMI audio codec.
Signed-off-by: Ricardo Neri ricardo.n...@ti.com
---
Implement an ASoC Codec Driver to handle audio configuration. The
implementation offers an interface for audio configuration and
control to be exposed to ALSA while hidding the HDMI details.
The ASoC driver supports the Basic Audio configuration as described
in CEA-861-D: 2-channel linear PCM
Add enurations and structures for audio configuration. This includes
enumerations for the Audio InfoFrame, I2S, audio FIFO and audio core.
Signed-off-by: Ricardo Neri ricardo.n...@ti.com
---
drivers/video/omap2/dss/hdmi.h | 220 +++-
1 files changed, 218
Hi,
Tony and John: What would be the appropriate path for this patch?
Cheers, Ilkka
On Apr 13, 2011 Krishnamoorthy, Balaji T wrote:
On Wed, Mar 16, 2011 at 9:37 PM, Ilkka Koskinen
ilkka.koski...@nokia.com wrote:
The driver is accessing to i2c bus in interrupt handler.
Therefore, it should
From: Srinath.R srin...@mistralsolutions.com
Replaced gpio_request()/gpio_direction_output() with gpio_request_one() in
am3517_crane_init.
Signed-off-by: Srinath.R srin...@mistralsolutions.com
---
arch/arm/mach-omap2/board-am3517crane.c | 10 ++
1 files changed, 2 insertions(+), 8
Hi Srinath,
On 05/05/11 10:15, srin...@mistralsolutions.com wrote:
From: Srinath.R srin...@mistralsolutions.com
Replaced gpio_request()/gpio_direction_output() with gpio_request_one() in
am3517_crane_init.
This has been already done and waits for Tony to apply.
Please, see:
Added new color formats supported by OMAP4.
Signed-off-by: Amber Jain am...@ti.com
---
arch/arm/plat-omap/include/plat/display.h |5 ++
drivers/video/omap2/dss/dispc.c | 107 -
drivers/video/omap2/dss/dss_features.c| 43 +++-
cm-t3730 is basically the same board as cm-t35, but has DM3730 SoC
assembled and therefore some changes are required.
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
arch/arm/mach-omap2/Kconfig|2 +-
arch/arm/mach-omap2/board-cm-t35.c | 62
On Wed, 2011-05-04 at 20:01 +0530, Janorkar, Mayuresh wrote:
-Original Message-
From: Valkeinen, Tomi
Sent: Wednesday, May 04, 2011 12:28 AM
To: Janorkar, Mayuresh
Cc: linux-omap@vger.kernel.org; K, Mythri P
Subject: Re: [PATCH v2 5/7] OMAP: DSS: Adding initialization routine
On 05/05/11 11:53, Igor Grinberg wrote:
cm-t3730 is basically the same board as cm-t35, but has DM3730 SoC
assembled and therefore some changes are required.
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
arch/arm/mach-omap2/Kconfig|2 +-
Hi Elvis,
Thanks for the information..
On Wednesday 04 May 2011 04:44 PM, Elvis Dowson wrote:
Hi,
On May 4, 2011, at 12:59 PM, Mohamed Thalib H wrote:
Is boot logo not supported in OMAP3530?
There are two ways you can add a boot logo to your target platform (Overo or
BeagleBoard), one is
Hi,
On Wednesday 04 May 2011 07:33 PM, Jan Weitzel wrote:
Hello,
I am using drivers/usb/musb/omap2430.c for a board configured in
MUSB_OTG mode.
Is it correct that I need to load gadget driver to get it working as
host?
No. Host mode don't need gadget driver. Once OTG mode needs them.
I got
Simplify detection of the sglist feature and add a
define for the super block end event that occurs
with sglist transfers.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
CC: Venkatraman S svenk...@ti.com
CC: Madhusudhan C madhu...@ti.com
CC: Shilimkar Santosh santosh.shilim...@ti.com
CC:
From: Venkatraman S svenk...@ti.com
autoloading feature
Start to use the sDMA descriptor autoloading feature.
For large datablocks, the MMC driver has to repeatedly setup,
program and teardown the dma channel for each element of the
sglist received in omap_hsmmc_request.
By using descriptor
From: Venkatraman S svenk...@ti.com
Add sDMA driver support for descriptor autoloading feature.
Descriptor autoloading is OMAP sDMA v5 hardware capability that can be
exploited for scatter gather
scenarios, currently available in OMAP3630 and OMAP4430.
The feature works as described below.
Let the bootloader do all the pad configuration.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
arch/arm/mach-omap2/board-rm680.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-rm680.c
b/arch/arm/mach-omap2/board-rm680.c
index
From: Jarkko Lavinen jarkko.lavi...@nokia.com
Allow the bootloader do all the muxing.
Signed-off-by: Jarkko Lavinen jarkko.lavi...@nokia.com
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
arch/arm/mach-omap2/hsmmc.c |3 ++-
arch/arm/mach-omap2/hsmmc.h |1 +
2 files changed, 3
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
Move the min and max frequency constants to the definition block in the source
file.
Signed-off-by: Andy Shevchenko ext-andriy.shevche...@nokia.com
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
drivers/mmc/host/omap_hsmmc.c |6
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
There is similar piece of code in two functions which enables clock. Split this
code to omap_hsmmc_start_clock(). Re-use omap_hsmmc_stop_clock() in
omap_hsmmc_context_restore() as well.
Signed-off-by: Andy Shevchenko
The sDMA descriptor autoloading feature uses a fixed size
buffer to store descriptors for scatterlist segments.
That limits the scatterlist size to the maximum number
of descriptors that fit in the buffer. The driver must
set this limit for upper layers to obey.
Signed-off-by: Adrian Hunter
From: Sudhir Bera ext-sudhir.b...@nokia.com
In fact the no_off check here will not be hit because
'omap_hsmmc_disabled_to_sleep()' won't schedule a
deeper disable in the no_off case.
Signed-off-by: Sudhir Bera ext-sudhir.b...@nokia.com
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
There are two places where the same calculations are done. Let's split them to
separate function.
In addition the new function is simplified by usage DIV_ROUND_UP kernel macro.
Signed-off-by: Andy Shevchenko ext-andriy.shevche...@nokia.com
CERR and BADA were in the wrong place and there are only
32 not 35.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
drivers/mmc/host/omap_hsmmc.c | 19 +++
1 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
There are two pieces of code which similar, but not the same. Each of them
contains a bug.
The SYSCTL register should be read before write in the
omap_hsmmc_context_restore() to remain the state of the reserved bits.
Before set the clock
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
There are few places with the same functionality. This patch creates two
functions omap_hsmmc_set_bus_width() and omap_hsmmc_set_bus_mode() to do the
job.
Signed-off-by: Andy Shevchenko ext-andriy.shevche...@nokia.com
Signed-off-by: Adrian
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
Signed-off-by: Andy Shevchenko ext-andriy.shevche...@nokia.com
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
drivers/mmc/host/omap_hsmmc.c | 17 ++---
1 files changed, 6 insertions(+), 11 deletions(-)
diff --git
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
We should like to adjust MMC host controller clock whenever the OPP is changed.
OPP affects to L3/L4 bus frequency. Due to this we update the maximum frequency
limits before each upcoming request and when the divisor is calculated.
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
There are 3 new platform data methods which should help us to do a clock
switching when notification is happened or request is started.
The purpose of the patch is to avoid high frequency of MMC controller on low
OPPs due to an HW bug in OMAP
eMMC may have a hardware reset line connected to a gpio,
so pass it to the driver.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
arch/arm/mach-omap2/hsmmc.c |5 +
arch/arm/mach-omap2/hsmmc.h |1 +
arch/arm/plat-omap/include/plat/mmc.h |1 +
3 files
In the case of an I/O error, the DMA will have been
cleaned up in the MMC interrupt and the request
structure pointer will be null.
In that case, it is essential to check if the DMA
DMA is over before dereferencing host-mrq-data.
Oops as follows:
3[ 2293.695281] wl1271: ERROR sdio read failed
Go through the driver's set_power() functions rather than
calling regulator_enable/disable() directly because otherwise
pbias configuration for MMC1 is not done.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
drivers/mmc/host/omap_hsmmc.c | 17 -
1 files changed, 8
After a warm restart, an eMMC which cannot be powered off is
in an unknown state, so reset it to be sure it will initialize.
Signed-off-by: Adrian Hunter adrian.hun...@nokia.com
---
drivers/mmc/host/omap_hsmmc.c | 38 +-
1 files changed, 37 insertions(+), 1
On Thu, 2011-05-05 at 04:50 -0700, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [110505 04:33]:
On Wed, 2011-05-04 at 12:40 +0300, Tony Lindgren wrote:
Looks like we should first combine all this cut and paste data
for each board file into some common init function to
On Thu, May 5, 2011 at 2:51 PM, Adrian Hunter adrian.hun...@nokia.com wrote:
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
There are two pieces of code which similar, but not the same. Each of them
contains a bug.
The SYSCTL register should be read before write in the
On Thu, May 05, 2011 at 02:36:48PM +0300, Tomi Valkeinen wrote:
So currently we have REGULATOR_SUPPLY defines for each board in all the
board files which support display. It would be much better to have an
overrideable standard setup for the DSS powers, but this would require
dynamically
On Thu, 2011-05-05 at 04:50 -0700, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [110505 04:33]:
On Wed, 2011-05-04 at 12:40 +0300, Tony Lindgren wrote:
Looks like we should first combine all this cut and paste data
for each board file into some common init function to
Hello.
On 05-05-2011 15:51, Adrian Hunter wrote:
From: Sudhir Bera ext-sudhir.b...@nokia.com
In fact the no_off check here will not be hit because
'omap_hsmmc_disabled_to_sleep()' won't schedule a
deeper disable in the no_off case.
Signed-off-by: Sudhir Bera ext-sudhir.b...@nokia.com
On Thu, May 5, 2011 at 2:51 PM, Adrian Hunter adrian.hun...@nokia.com wrote:
From: Andy Shevchenko ext-andriy.shevche...@nokia.com
There are 3 new platform data methods which should help us to do a clock
switching when notification is happened or request is started.
The purpose of the patch
Hi Mythri,
Sorry for the late reply, I've only noticed this issue today.
On Thursday 10 March 2011 11:44:11 Mythri P K wrote:
Adding function to reset/set gamma table bit for TV interface
currentl only support for disabled is added.
Signed-off-by: Mythri P K mythr...@ti.com
---
On Wed, May 04, 2011 at 11:50:52PM -0700, Colin Cross wrote:
True, that was an oversimplificaiton. I meant the minimum voltage that
scales with clock frequencies only depends on the clock frequency, not
the device. Devices do need to be able to specify a higher minimum
voltage, and the
Hi Artem,
Can you please give a look on this patch?
This patch fixes is required for anyone who wants to use this driver
without using HW ECC.
-- Vimal
On Mon, May 2, 2011 at 4:40 PM, Kishore Kadiyala
kishore.kadiy...@ti.com wrote:
For prefetch engine, read and write got broken in commit
Govindraj govindraj...@gmail.com writes:
On Thu, May 5, 2011 at 2:13 AM, Kevin Hilman khil...@ti.com wrote:
Govindraj.R govindraj.r...@ti.com writes:
Acquire console lock before enabling and writing to console-uart
to avoid any recursive prints from console write.
for ex:
-- printk
Govindraj govindraj...@gmail.com writes:
[...]
... this is just putting back basically the same thing that was removed in
patch 1. IOW, this is now being checked for *every* PRCM wakeup, which
is no different than having it in the idle path.
I thought I understood that you had the SW IRQ
From: Jean Pihet j-pi...@ti.com
Rework of the OMAP2+ cpuidle code
v2: rework after comments on linux-omap ML:
- remove useless macros,
- replace the C-state common data fill-in helper macro by an inline
function, for better readability,
- update commits description.
v1:
- optimize the
From: Jean Pihet j-pi...@ti.com
- sleep_latency and wake_latency are not used, replace them by
exit_latency which is used by cpuidle. exit_latency simply is
the sum of sleep_latency and wake_latency,
- replace threshold by target_residency,
- changed the OMAP3 specific cpuidle code
From: Jean Pihet j-pi...@ti.com
The current implementation defines an internal structure and a
C-states array. Using those structures is redundant to the
structs used by the cpuidle framework.
This patch provides a clean-up of the internal struct, removes the
internal C-states array, stores the
From: Jean Pihet j-pi...@ti.com
- fix single and multi-lines comments format
- removed the omap3_idle_bm_check function and replaced the test
in omap3_enter_idle_bm by the equivalent code
- re-organize omap3_enter_idle_bm code path, assign local variables
only when needed
- reword some
From: Jean Pihet j-pi...@ti.com
The achievable power modes of the power domains in cpuidle
depends on the system wide 'enable_off_mode' knob in debugfs.
Upon changing enable_off_mode, do not change the C-states
'valid' field but instead dynamically restrict the power modes
when entering idle.
Hi Paul, Benoit,
I've started testing pm runtime with DSS, and I encountered a problem.
I'm using latest -rc5 as a base, and it looks like
omap_hwmod:_wait_target_ready() does not succeed for dss_core hwmod.
This causes _enable() to fail, but omap_device_enable_hwmods() does not
check the return
I've been working on getting the TI OMAPPSP-03.00.01.06 kernel to
properly suspend/resume on my DM37x board and all was going well until I
added OTG support to the kernel and on suspend, the IVA2 and CORE pwrdms
would not properly go into suspend. When comparing output from
On Thu, 2011-05-05 at 18:59 +0300, Tomi Valkeinen wrote:
Hi Paul, Benoit,
I've started testing pm runtime with DSS, and I encountered a problem.
I'm using latest -rc5 as a base, and it looks like
omap_hwmod:_wait_target_ready() does not succeed for dss_core hwmod.
This causes _enable() to
Hi Tomi,
On 5/5/2011 5:59 PM, Valkeinen, Tomi wrote:
Hi Paul, Benoit,
I've started testing pm runtime with DSS, and I encountered a problem.
I'm using latest -rc5 as a base, and it looks like
omap_hwmod:_wait_target_ready() does not succeed for dss_core hwmod.
This causes _enable() to fail,
Peter Barada peter.bar...@gmail.com writes:
I've been working on getting the TI OMAPPSP-03.00.01.06 kernel to
properly suspend/resume on my DM37x board and all was going well until
I added OTG support to the kernel and on suspend, the IVA2 and CORE
pwrdms would not properly go into suspend.
You were faster than me :-)
On 5/5/2011 7:02 PM, Valkeinen, Tomi wrote:
On Thu, 2011-05-05 at 18:59 +0300, Tomi Valkeinen wrote:
Hi Paul, Benoit,
I've started testing pm runtime with DSS, and I encountered a problem.
I'm using latest -rc5 as a base, and it looks like
On 05/05/2011 01:11 PM, Kevin Hilman wrote:
Peter Baradapeter.bar...@gmail.com writes:
I've been working on getting the TI OMAPPSP-03.00.01.06 kernel to
properly suspend/resume on my DM37x board and all was going well until
I added OTG support to the kernel and on suspend, the IVA2 and CORE
Govindraj.R govindraj.r...@ti.com writes:
For omap2 cpu_idle thread will not be available
Why not?
and uart_clock cutting happens only in suspend path.
Aren't clocks also cut after runtime PM autosuspend?
Prior to this patch the uart_clock was cut using prepare/resume
calls since these
Hi Jean,
jean.pi...@newoldbits.com writes:
From: Jean Pihet j-pi...@ti.com
The current implementation defines an internal structure and a
C-states array. Using those structures is redundant to the
structs used by the cpuidle framework.
This patch provides a clean-up of the internal
Peter Barada peter.bar...@gmail.com writes:
On 05/05/2011 01:11 PM, Kevin Hilman wrote:
Peter Baradapeter.bar...@gmail.com writes:
I've been working on getting the TI OMAPPSP-03.00.01.06 kernel to
properly suspend/resume on my DM37x board and all was going well until
I added OTG support to
On Mon, 2011-05-02 at 16:40 +0530, Kishore Kadiyala wrote:
For prefetch engine, read and write got broken in commit '2c01946c'.
We never hit a scenario of not getting 'gpmc_prefetch_enable'
call success.
When reading/writing a subpage with a non divisible by 4 ecc number
of bytes, the
On 05/05/2011 02:16 PM, Kevin Hilman wrote:
Peter Baradapeter.bar...@gmail.com writes:
On 05/05/2011 01:11 PM, Kevin Hilman wrote:
Peter Baradapeter.bar...@gmail.com writes:
I've been working on getting the TI OMAPPSP-03.00.01.06 kernel to
properly suspend/resume on my DM37x board and
Peter Barada peter.bar...@gmail.com writes:
On 05/05/2011 02:16 PM, Kevin Hilman wrote:
Peter Baradapeter.bar...@gmail.com writes:
On 05/05/2011 01:11 PM, Kevin Hilman wrote:
Peter Baradapeter.bar...@gmail.com writes:
I've been working on getting the TI OMAPPSP-03.00.01.06 kernel to
On 5/5/2011 8:11 AM, Colin Cross wrote:
On Wed, May 4, 2011 at 10:08 PM, Cousson, Benoitb-cous...@ti.com wrote:
(Cc folks with some DVFS interest)
Hi Colin,
On Fri, 22 Apr 2011, Colin Cross wrote:
Now that we are approaching a common clock management implementation,
I was thinking it might
Hello Avinash
On Mon, 2 May 2011, Avinash.H.M wrote:
The sequence of _ocp_softreset doesn't work for i2c. The i2c module has a
special sequence to reset the module. The sequence is
- Disable the I2C.
- Write to SOFTRESET bit.
- Enable the I2C.
- Poll on the RESETDONE bit.
The sequence
On Thu, May 5, 2011 at 2:08 PM, Cousson, Benoit b-cous...@ti.com wrote:
On 5/5/2011 8:11 AM, Colin Cross wrote:
On Wed, May 4, 2011 at 10:08 PM, Cousson, Benoitb-cous...@ti.com wrote:
(Cc folks with some DVFS interest)
Hi Colin,
On Fri, 22 Apr 2011, Colin Cross wrote:
Now that we are
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