This patch exports APIs to get base address for GIC
distributor, CPU interface, SCU and PL310 L2 Cache which
are used in OMAP4 PM code.
This was suggested by Kevin Hilman khil...@ti.com during
OMAP4 PM code review.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil
Initialise hardware supervised mode for all clockdomains if it's
supported. Initiate sleep transition for other clockdomains,
if they are not being used.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch
mode 100644
index 000..26e7bcc
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-secure.h
@@ -0,0 +1,40 @@
+/*
+ * omap-secure.h: OMAP Secure infrastructure header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar santosh.shilim...@ti.com
+ *
+ * This program
to OMAP3XXX / OMAP4XXX
secure RAM size requirements.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/include/mach/omap-secure.h |4 +++
arch/arm/mach-omap2/omap-secure.c | 29
arch/arm/plat-omap/common.c|3
- Version J
Section :
4.3.4.2 Power States of CPU0 and CPU1
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap-smp.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch
domain. During normal operation,
WakeupGen delivers external interrupts directly to the GIC.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/Makefile |2 +-
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
supervised
clockdomain mode isn't functional for all clockdomains
on OMAP4430 ES1.0 silicon so avoid the same.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reported-by: Kevin Hilman khil...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/pm44xx.c |5 +
1 files changed
Program non-boot CPUs to hit lowest supported power state
when it is off-lined using cpu hotplug framework.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/include/mach/omap4-common.h |7 +
arch/arm/mach-omap2/omap
This patch adds MPUSS(MPU Sub System) power domain
CSWR(Close Switch Retention) support to system wide suspend.
For both MPUSS RET support, CPUs are programmed to OFF state.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-omap2/omap-mpuss
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
retention (CSWR) is not supported by hardware design.
The CPUx OFF mode isn't supported on OMAP4430 ES1.0
CPUx sleep code is common for hotplug, suspend and CPUilde.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
and restored by hardware like WakeupGen.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/omap-wakeupgen.c | 130
arch/arm/mach-omap2/omap4-sar-layout.h | 15
2 files changed, 145 insertions(+), 0
When MPUSS hits off-mode e, L2 cache is lost. This patch adds L2X0
necessary maintenance operations and context restoration in the
low power code.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/include/mach/omap-secure.h |5
These notifiers can be used to isolate non-cpu specific PM
code from CPU idle code.
To start with, we can already leverage VFP handlers using notifier
chain for low power idle code. So use them.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch
with local timers marked with (mis)feature flag CLOCK_EVT_FEAT_C3STOP.
Then notify the clock events layer from idle code using
CLOCK_EVT_NOTIFY_BROADCAST_ENTER/EXIT).
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/cpuidle44xx.c |8
off mode, it eventually hits off state since memory
contents are lost.
Hence the MPUSS off mode independent state is not attempted without
device off mode. All the necessary infrastructure code for MPUSS
off mode is in place as part of this series.
Signed-off-by: Santosh Shilimkar santosh.shilim
-state latency profiling.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/Makefile |2 +-
arch/arm/mach-omap2/cpuidle44xx.c | 198 +
arch/arm/mach
dependencies.
Without this system locks up or randomly crashesh.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/pm44xx.c | 28
This patch adds SAR RAM support on OMAP4430. SAR RAM used to save
and restore the HW context in low power modes.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/include/mach/omap4-common.h |1 +
arch/arm/mach-omap2/omap4
OMAP interconnect drivers are used for the interconnect error handling.
Since they are bus driver, lets move it to newly created drivers/bus.
Cc: Arnd Bergmann a...@arndb.de
Cc: Tony Lindgren t...@atomide.com
Tested-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Santosh Shilimkar
...@github.com:SantoshShilimkar/linux.git for_3.7/omap5_arch_timer
for you to fetch changes up to 3c7c5dab44d6c8861bc86dab924353d8d40344f8:
ARM: OMAP5: Enable arch timer support (2012-09-19 13:00:37 +0530)
Santosh Shilimkar (2):
ARM: OMAP: Add
Tony,
On Friday 05 October 2012 03:34 AM, Tony Lindgren wrote:
Hi all,
Here are some more patches for early merging after -rc1 for v3.8
merge window to remove more plat includes for the ARM common
zImage support. These are based on top of current linux next +
kevin's cpufreq fixes.
Have
On Monday 08 October 2012 02:22 PM, Santosh Shilimkar wrote:
Tony,
On Friday 05 October 2012 03:34 AM, Tony Lindgren wrote:
Hi all,
Here are some more patches for early merging after -rc1 for v3.8
merge window to remove more plat includes for the ARM common
zImage support. These are based
On Thursday 11 October 2012 01:41 PM, Benoit Cousson wrote:
Hi Lokesh,
On 10/11/2012 08:16 AM, Lokesh Vutla wrote:
+ devicetree-discuss
Hi Benoit,
On Wednesday 10 October 2012 08:31 PM, Benoit Cousson wrote:
On 10/10/2012 02:05 PM, Lokesh Vutla wrote:
Device tree data for the EMIF sdram
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Lokesh. Looks fine to me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Tero, paul,
On Thursday 18 October 2012 02:07 PM, Tero Kristo wrote:
On Thu, 2012-10-18 at 06:48 +, Paul Walmsley wrote:
On Thu, 18 Oct 2012, Paul Walmsley wrote:
Here are some basic OMAP test results for Linux v3.7-rc1.
Logs and other details at
Paul !!
This series and part2 both looks good to me.
Sorry for not being able to help in some of these clean-ups
because of other work priorities as talked at LPC.
Feel free to add my ack for the whole series if you need one.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
--
To unsubscribe from
Mark,
On Saturday 20 October 2012 03:23 AM, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
This series updates the crypto omap-sham driver and supporting
infrastructure.
Notes:
a) Based on current k.o. c9623de (Merge branch 'v4l_for_linus'
of
the
value of UART sysconfig before and after the offmode entry to
see if the smart-idle/smart-idle wakeup setting getting disturbed
for some reason.
Below is the OMAP4 commit am referring to.
commit 5ae256dcd91bf308826a4ac19598b27ebb86a536
Author: Santosh Shilimkar santosh.shilim...@ti.com
Date: Fri
bogus state to be restored, leaving
GPIO debounce enabled which then prevented the CORE powerdomain from
transitioning.
Reported-by: Paul Walmsley p...@pwsan.com
Cc: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Kevin Hilman khil...@ti.com
---
Acked-by: Santosh Shilimkar santosh.shilim
On Wednesday 24 October 2012 05:32 PM, Grazvydas Ignotas wrote:
On Tue, Oct 23, 2012 at 9:09 PM, Kevin Hilman
khil...@deeprootsystems.com wrote:
From: Kevin Hilman khil...@ti.com
When debounce clocks are disabled, ensure that the banks
dbck_enable_mask is cleared also. Otherwise, context
On Wednesday 24 October 2012 07:49 PM, Kevin Hilman wrote:
Grazvydas Ignotas nota...@gmail.com writes:
On Tue, Oct 23, 2012 at 9:09 PM, Kevin Hilman
khil...@deeprootsystems.com wrote:
From: Kevin Hilman khil...@ti.com
When debounce clocks are disabled, ensure that the banks
dbck_enable_mask
On Thursday 25 October 2012 06:12 AM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [121024 17:36]:
* Santosh Shilimkar santosh.shilim...@ti.com [121017 06:35]:
(Looping Arnd and Olof)
On Wednesday 17 October 2012 06:58 PM, Lokesh Vutla wrote:
When building omap_l3_noc/smx drivers
On Thursday 25 October 2012 04:24 AM, Jon Hunter wrote:
On 10/24/2012 12:10 PM, Kevin Hilman wrote:
From: Kevin Hilman khil...@ti.com
When a GPIO bank is freed or shutdown, ensure that the banks
dbck_enable_mask is cleared also. Otherwise, context restore on
subsequent off-mode transition
---
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
just a cleanup patch trying to make exit path
more straightforward. No changes otherwise.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/i2c/busses/i2c-omap.c | 26 +-
1 file changed, 17 insertions(+), 9
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
In case we loop on IRQ handler until stat is
finally zero, we would end up in a situation
where all I2C transfers would misteriously
timeout because we were not calling complete()
in that situation.
Fix the issue by moving
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
on OMAP4+ we want to read IRQSTATUS_RAW register,
instead of IRQSTATUS. The reason being that IRQSTATUS
will only contain the bits which were enabled on
IRQENABLE_SET and that will break when we need to
poll for a certain bit which wasn't
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
Later patches will come adding support for
reporting amount of bytes transferred so that
client drivers can count how many bytes are
left to transfer.
This is useful mostly in case of NACKs when
client driver wants to know exactly which
On Thursday 25 October 2012 06:22 PM, Felipe Balbi wrote:
Hi,
On Thu, Oct 25, 2012 at 06:23:57PM +0530, Santosh Shilimkar wrote:
On Thursday 25 October 2012 05:55 PM, Felipe Balbi wrote:
on OMAP4+ we want to read IRQSTATUS_RAW register,
instead of IRQSTATUS. The reason being that IRQSTATUS
On Thursday 25 October 2012 06:41 PM, Jon Hunter wrote:
On 10/25/2012 02:00 AM, Santosh Shilimkar wrote:
On Thursday 25 October 2012 04:24 AM, Jon Hunter wrote:
On 10/24/2012 12:10 PM, Kevin Hilman wrote:
From: Kevin Hilman khil...@ti.com
When a GPIO bank is freed or shutdown, ensure
that we are aligned, so we can take this patch forward. Feel free
to add my ack in case you plan to refresh it.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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More
On Friday 26 October 2012 12:45 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [121024 23:34]:
On Thursday 25 October 2012 06:12 AM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [121024 17:36]:
* Santosh Shilimkar santosh.shilim...@ti.com [121017 06:35
On Friday 26 October 2012 01:18 PM, Bedia, Vaibhav wrote:
Hi,
Compiling the current linus/master (2ab3f29) using omap2plus_defconfig
throws up the following error
$make -j7 uImage
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
make[1]:
On Friday 26 October 2012 03:32 PM, Bedia, Vaibhav wrote:
On Fri, Oct 26, 2012 at 14:29:28, Shilimkar, Santosh wrote:
On Friday 26 October 2012 01:18 PM, Bedia, Vaibhav wrote:
Hi,
Compiling the current linus/master (2ab3f29) using omap2plus_defconfig
throws up the following error
$make -j7
On Saturday 27 October 2012 04:31 AM, Paul Walmsley wrote:
Hi Felipe
just two quick comments
On Thu, 25 Oct 2012, Felipe Balbi wrote:
if we allow compiler reorder our writes, we could
fall into a situation where dev-buf_len is reset
for no apparent reason.
This bug was found with a simple
On Saturday 27 October 2012 03:09 AM, Jon Hunter wrote:
On 10/26/2012 03:01 PM, Felipe Balbi wrote:
Hi,
On Fri, Oct 26, 2012 at 03:19:13PM +0200, Tim Niemeyer wrote:
Adds support for configuring the omap-gpio driver use autosuspend for
runtime power management. This can reduce the latency in
On Saturday 27 October 2012 05:33 PM, Constantine Shulyupin wrote:
From: Constantine Shulyupin co...@makelinux.com
Tested SD (MMC) and Ethernet smsc95xx on linux-3.7-rc2
Signed-off-by: Constantine Shulyupin co...@makelinux.com
--
kernel size is 2.3 MiB
---
On Saturday 27 October 2012 09:29 PM, Paul Walmsley wrote:
On Sat, 27 Oct 2012, Santosh Shilimkar wrote:
Another alternative, which I will recommend to just make use of the
read*/wrire* instead __raw versions. The barriers are taken care
already and driver point of view, it is transparent
+ Jon,
On Friday 26 October 2012 06:49 PM, Tim Niemeyer wrote:
Adds support for configuring the omap-gpio driver use autosuspend for
runtime power management. This can reduce the latency in using it by
not suspending the device immediately on idle. If another access takes
place before the
On Monday 29 October 2012 01:35 PM, Felipe Balbi wrote:
On Mon, Oct 29, 2012 at 12:17:08PM +0530, Santosh Shilimkar wrote:
+ Jon,
On Friday 26 October 2012 06:49 PM, Tim Niemeyer wrote:
Adds support for configuring the omap-gpio driver use autosuspend for
runtime power management. This can
On Tuesday 30 October 2012 01:33 AM, Felipe Balbi wrote:
Hi,
On Mon, Oct 29, 2012 at 01:53:37PM +0530, Santosh Shilimkar wrote:
Just to expand a bit, Out of 6 GPIO banks, GPIO1 bank is in always ON
domain where as remaing 5 are in peripheral domain. Letting individual
banks idle allowed you
On Wednesday 31 October 2012 04:07 PM, Kevin Hilman wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
[...]
Just to summaries, there are 3 things we are talking here.
Santosh, thanks for the summary. You are right on.
1. Delaying the idle with a timeout which $subject patch
On Thursday 01 November 2012 03:53 PM, Ivan Khoronzhuk wrote:
Replaces several flags bearing the same meaning. There is no need
to set flags due to different omap types here, it can be checked
in appropriate places as well.
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King
On Thursday 01 November 2012 09:50 PM, ivan.khoronzhuk wrote:
On 11/01/2012 01:35 PM, Santosh Shilimkar wrote:
On Thursday 01 November 2012 03:53 PM, Ivan Khoronzhuk wrote:
Replaces several flags bearing the same meaning. There is no need
to set flags due to different omap types here, it can
On Thursday 01 November 2012 10:36 PM, Nishanth Menon wrote:
On 22:05-20121101, Santosh Shilimkar wrote:
On Thursday 01 November 2012 09:50 PM, ivan.khoronzhuk wrote:
On 11/01/2012 01:35 PM, Santosh Shilimkar wrote:
On Thursday 01 November 2012 03:53 PM, Ivan Khoronzhuk wrote:
Replaces
Tony,
On Friday 02 November 2012 04:18 AM, Tony Lindgren wrote:
This file has only omap_init_consistent_dma_size()
left that can be moved to plat-omap/dma.c.
Signed-off-by: Tony Lindgren t...@atomide.com
---
arch/arm/plat-omap/Makefile |2 +-
arch/arm/plat-omap/common.c | 26
Tony,
On Friday 02 November 2012 04:18 AM, Tony Lindgren wrote:
This file has only omap_init_consistent_dma_size()
left that can be moved to plat-omap/dma.c.
Signed-off-by: Tony Lindgren t...@atomide.com
---
arch/arm/plat-omap/Makefile |2 +-
arch/arm/plat-omap/common.c | 26
On Friday 02 November 2012 02:19 PM, Tomi Valkeinen wrote:
On 2012-11-02 08:38, Santosh Shilimkar wrote:
Tony,
On Friday 02 November 2012 04:18 AM, Tony Lindgren wrote:
This file has only omap_init_consistent_dma_size()
left that can be moved to plat-omap/dma.c.
Signed-off-by: Tony Lindgren
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
From: Vaibhav Hiremath hvaib...@ti.com
The current OMAP timer code registers two timers -
one as clocksource and one as clockevent.
Actually OMAP also uses only one timer. The clocksource
is taken care by 32K syntimer till OMAP4 and by
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
On AM33XX, the mailbox module between the MPU and the
WKUP-M3 co-processor facilitates a one-way communication.
MPU uses the assigned mailbox sub-module to issue the
interrupt to the WKUP-M3 co-processor which then goes
and reads the the
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Mailbox IP on AM33XX, is the same as that present
in OMAP4. The single instance of Mailbox module
contains 8 sub-modules and facilitates communication
between MPU, PRUs and WKUP_M3.
The first mailbox sub-module is assigned for
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
The power management code for AM33XX is a late_initcall
and the PM features depend on the mailbox for IPC.
In preparation for this, convert the mailbox init to
a device_initcall.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Add the reset status offset for WKUP_M3 in the hwmod data
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
The hwmod data for OCMCRAM in AM33XX was commented out.
This data is needed by the power management code, hence
uncomment the same and register the OCP interface for it.
Why this data is needed by PM code ?
Regards
Santosh
--
To
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
The first entry for CPGMAC0 should be ADDR_MAP_ON_INIT
instead of ADDR_TYPE_RT to ensure the omap hwmod code
maps the memory space at init and writes to the SYSCONFIG
registers.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Get rid of some unnecessary header file inclusions
and also use __ASSEMBLER__ macros to allow the
various register offsets from PM assembly code
which be added in a subsequent patch.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
AM33XX has only one usable timer in the WKUP domain.
Currently the timer instance in WKUP domain is used
as the clockevent and the timer in non-WKUP domain
as the clocksource. The timer in WKUP domain can keep
running in suspend from a
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
AM335x supports various low power modes as documented
in section 8.1.4.3 of the AM335x TRM which is available
@ http://www.ti.com/litv/pdf/spruh73f
DeepSleep0 mode offers the lowest power mode with limited
wakeup sources without a system
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:24:14, Shilimkar, Santosh wrote:
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files
On Sunday 04 November 2012 08:55 PM, Bedia, Vaibhav wrote:
Hi Santosh,
On Sat, Nov 03, 2012 at 21:22:04, Shilimkar, Santosh wrote:
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
From: Vaibhav Hiremath hvaib...@ti.com
The current OMAP timer code registers two timers -
one as
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:24:14, Shilimkar, Santosh wrote:
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:33:47, Shilimkar, Santosh wrote:
[...]
+static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
+{
+ struct omap_mbox2_fifo *fifo =
+ ((struct omap_mbox2_priv *)mbox-priv)-tx_fifo;
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:40:37, Shilimkar, Santosh wrote:
[...]
+#if defined(CONFIG_SOC_AM33XX)
+ else if (soc_is_am33xx()) {
+ list = am33xx_mboxes;
+
+ list[0]-irq = platform_get_irq(pdev, 0);
+
On Tuesday 06 November 2012 12:59 AM, Kevin Hilman wrote:
Bedia, Vaibhav vaibhav.be...@ti.com writes:
On Mon, Nov 05, 2012 at 20:23:11, Shilimkar, Santosh wrote:
[...]
On OMAP the OCMC RAM is always clocked and doesn't need any special
clock enable. CM_L3_2_OCMC_RAM_CLKCTRL module mode
On Tuesday 06 November 2012 02:49 AM, Santosh Shilimkar wrote:
On Tuesday 06 November 2012 12:59 AM, Kevin Hilman wrote:
Bedia, Vaibhav vaibhav.be...@ti.com writes:
On Mon, Nov 05, 2012 at 20:23:11, Shilimkar, Santosh wrote:
[...]
On OMAP the OCMC RAM is always clocked and doesn't need any
On Monday 05 November 2012 11:10 PM, Kevin Hilman wrote:
+Santosh (to help with EMIF questions/comments)
On 11/02/2012 12:32 PM, Vaibhav Bedia wrote:
AM335x supports various low power modes as documented
in section 8.1.4.3 of the AM335x TRM which is available
@
On Monday 05 November 2012 11:33 PM, Kevin Hilman wrote:
Bedia, Vaibhav vaibhav.be...@ti.com writes:
On Sat, Nov 03, 2012 at 18:34:30, Kevin Hilman wrote:
[...]
Doesn't this also mean that you won't get timer wakeups
in idle? Or are you keeping the domain where the clockevent is
on during
+: Add prm and cm base init function.
Santosh Shilimkar (6):
ARM: OMAP4: Don't compile cm2xxx_3xxx.c for OMAP4 only builds.
ARM: OMAP2+: Clean up wrapping multiple objects in Makefile
ARM: OMAP4: Remove un-used WakeupGen register defines.
ARM: OMAP: dma: Make use of cpu_class_is_omap2
Since OMAP4 code base now makes use of OMAP4 specific PRCM functions,
cm2xxx_3xxx.c need not be compiled for OMAP4 only builds.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/Makefile |5 +
1 files changed, 1 insertions
Current OMAP code doesn't use any of the OMAP_WKG_ENB_SECURE_*
registers.
So remove those defines.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |8
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/arch
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Makefile | 160 -
1 files changed, 78 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 56ed62e..669e2b1 100644
cpu_class_is_omap2() contains all OMAP2+ devices. So update the DMA code
cpu checks accordingly so that there is no need to patch
the file for any future OMAP2+ devices.
In long run, all these attributes should come from hwmod dev_attr based
on DMA IP version.
Signed-off-by: Santosh Shilimkar
EMIF, GMPC and DMM driver can ioremap() the address
space as part of driver intialisation and there is
no need to have static IO mapping for them.
Hence remove the un-used static IP space and let
the respective drivers manage it as part if driver
init.
Signed-off-by: Santosh Shilimkar
All OMAP2PLUS arch based machines makes use of mach-omap2 directory.
So just add one entry so that there is no need to patch this file
for any OMAP2+ devices.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/Makefile |4 +---
1 files changed, 1 insertions(+), 3
: Paul Walmsley p...@pwsan.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/cminst44xx.c | 28 ++--
arch/arm/mach-omap2/common.c |1 +
arch/arm/mach-omap2/common.h |1
: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/mach-omap1/gpio15xx.c |2 --
arch/arm/mach-omap1/gpio16xx.c |5 -
arch/arm
khil...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
---
arch/arm/mach-omap2/gpio.c |2 ++
arch/arm
(), the bank-workaround_enabled check is
moved after context restore. Otherwise, it would prevent
context restore when bank-enabled_non_wakeup_gpios is 0.
Cc: Kevin Hilman khil...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous
on OMAP1710SDP.
Cc: Kevin Hilman khil...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Cousson, Benoit b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Tarun Kanti DebBarma (8):
gpio/omap: remove virtual_irq_start variable
gpio
On Friday 04 May 2012 05:33 AM, Greg KH wrote:
On Thu, May 03, 2012 at 06:38:23PM -0400, Paul Gortmaker wrote:
On Fri, Apr 27, 2012 at 8:24 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Add a driver for the EMIF SDRAM controller used in Texas Instrument SoCs
Hi Santosh,
Can you
On Saturday 05 May 2012 04:25 AM, Tony Lindgren wrote:
* R Sricharan r.sricha...@ti.com [120503 00:30]:
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,8 +17,10 @@
#include linux/kernel.h
#include linux/errno.h
#include linux/smp.h
+#include
Tony,
On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
The series adds minimal OMAP5 support.
OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
hence large part of the peripherals are re-used.
OMAP5432 is
for the devices used like debug console etc.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/boot/compressed/head.S |7 ++-
1 files changed, 6
-omap-dev.git
for_3.5/omap_misc_cleanup
R Sricharan (1):
ARM: OMAP2+: dma: Define dma capabilities register bitfields and use them.
Santosh Shilimkar (6):
ARM: OMAP4: Don't compile cm2xxx_3xxx.c for OMAP4 only builds.
ARM: OMAP2+: Clean up wrapping multiple objects in Makefile
On Tuesday 08 May 2012 04:33 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120502 02:51]:
This series has some miscellianeous clean up patches which help to add future
OMAP2+ device support with bit less changes. It is a preparatory series for
adding minimal OMAP5
On Tuesday 08 May 2012 03:56 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120507 02:53]:
Tony,
On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
The series adds minimal OMAP5 support.
OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
L2 cache
On Tuesday 08 May 2012 06:17 PM, Will Deacon wrote:
Hello,
On Thu, May 03, 2012 at 08:26:18AM +0100, R Sricharan wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off
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