Re: [RFC 6/9] clk: ti: add support for omap4 module clocks
On 01/04/2016 06:37 PM, Tony Lindgren wrote: * Russell King - ARM Linux [160104 06:43]: On Mon, Jan 04, 2016 at 03:27:57PM +0200, Tero Kristo wrote: On 01/04/2016 12:21 PM, Geert Uytterhoeven wrote: FWIW, there are small loops with just a cpu_relax() in various clock drivers under drivers/clk/shmobile/. Just did a quick profiling round, and the clk_enable/disable delay loops take anything from 0...1500ns, most typically consuming some 400-600ns. So, based on this, dropping the udelay and adding cpu_relax instead looks like a good change. I just verified that changing the udelay to cpu_relax works fine also, I just need to change the bail-out period to be something sane. Was that profiling done with lockdep/lock debugging enabled or disabled? omap2plus_defconfig, so lockdep was enabled. The profiling was done around the while {} block though, which should not have any locks within it (except for the SCM clocks, which may explain some of the higher latency numbers seen.) And also the thing to check from the hw folks is what all do these clkctrl bits really control. If they group together the OCP clock and an extra functional clock for some devices the delays could be larger. Does it matter really? The latencies are only imposed to the device in question, and lets face it, the same latencies are there already with the hwmod implementation. This series moves the implementation under clock driver with as less modifications as possible to avoid any problems. In general, I think we need to get rid of pm_runtime_irq_safe usage to allow clocks to sleep properly. The other option is to allow toggling pm_runtime_irq_safe but that probably gets super messy. That is something not to be done with this set though. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 6/9] clk: ti: add support for omap4 module clocks
On 01/04/2016 12:21 PM, Geert Uytterhoeven wrote: Hi Tero, On Mon, Jan 4, 2016 at 8:36 AM, Tero Kristo wrote: On 01/01/2016 07:48 AM, Michael Turquette wrote: Quoting Tero Kristo (2015-12-18 05:58:58) +static int _omap4_hwmod_clk_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 val; + int timeout = 0; + int ret; + + if (!clk->enable_bit) + return 0; + + if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, +"%s: could not enable %s's clockdomain %s: %d\n", +__func__, clk_hw_get_name(hw), +clk->clkdm_name, ret); + return ret; + } + } + + val = ti_clk_ll_ops->clk_readl(clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK; + val |= clk->enable_bit; + + ti_clk_ll_ops->clk_writel(val, clk->enable_reg); + + /* Wait until module is enabled */ + while (!_omap4_is_ready(val)) { + udelay(1); This should really be a .prepare callback if you plan to keep the delays in there. If this is changed to a .prepare, then all OMAP power management is effectively ruined as all clocks are going to be enabled all the time. hwmod core doesn't support .prepare/.enable at the moment that well, and changing that is going to be a big burden (educated guess, haven't checked this yet)... The call chain that comes here is: device driver -> pm_runtime -> hwmod_core -> hwmod_clk_enable / disable. The delay within this function should usually be pretty short, just to wait that the module comes up from idle. Does it take multiple µs? Perhaps even one µs is much longer than needed? I recall the discussions regarding the udelays within clk_enable/disable calls, but what is the preferred approach then? Typically clk_enable/disable just becomes a NOP if it is not allowed to wait for hardware to complete transitioning before exiting the function. FWIW, there are small loops with just a cpu_relax() in various clock drivers under drivers/clk/shmobile/. Just did a quick profiling round, and the clk_enable/disable delay loops take anything from 0...1500ns, most typically consuming some 400-600ns. So, based on this, dropping the udelay and adding cpu_relax instead looks like a good change. I just verified that changing the udelay to cpu_relax works fine also, I just need to change the bail-out period to be something sane. -Tero Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 6/9] clk: ti: add support for omap4 module clocks
On 01/01/2016 07:48 AM, Michael Turquette wrote: Hi Tero, Quoting Tero Kristo (2015-12-18 05:58:58) Previously, hwmod core has been used for controlling the hwmod level clocks. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with common clock framework. Add support for new clock type under the TI clock driver, which will be used to convert all the existing hwmdo clocks to. This helps to get rid of the clock related hwmod data from kernel and instead parsing this from DT. I'm really happy to see this series. Looks pretty good to me. +static int _omap4_hwmod_clk_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 val; + int timeout = 0; + int ret; + + if (!clk->enable_bit) + return 0; + + if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, +"%s: could not enable %s's clockdomain %s: %d\n", +__func__, clk_hw_get_name(hw), +clk->clkdm_name, ret); + return ret; + } + } + + val = ti_clk_ll_ops->clk_readl(clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK; + val |= clk->enable_bit; + + ti_clk_ll_ops->clk_writel(val, clk->enable_reg); + + /* Wait until module is enabled */ + while (!_omap4_is_ready(val)) { + udelay(1); This should really be a .prepare callback if you plan to keep the delays in there. If this is changed to a .prepare, then all OMAP power management is effectively ruined as all clocks are going to be enabled all the time. hwmod core doesn't support .prepare/.enable at the moment that well, and changing that is going to be a big burden (educated guess, haven't checked this yet)... The call chain that comes here is: device driver -> pm_runtime -> hwmod_core -> hwmod_clk_enable / disable. The delay within this function should usually be pretty short, just to wait that the module comes up from idle. I recall the discussions regarding the udelays within clk_enable/disable calls, but what is the preferred approach then? Typically clk_enable/disable just becomes a NOP if it is not allowed to wait for hardware to complete transitioning before exiting the function. -Tero Regards, Mike -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4] clk: ti: Add support for dm814x ADPLL
On 12/22/2015 05:27 PM, Tony Lindgren wrote: On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL. Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall levels to postcore_initcall". Also note that this patch does not implement clk_set_rate for the PLL, that will be posted later on when available. Cc: Michael Turquette Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren --- If no more comments, Tero can you please apply into an immutable branch against v4.4-rc1 that I can merge in too? Changes since v3: - We want to create the clkdev entry for all clocks, not just outputs - ti_adpll_wait_lock loops did not do the right thing - We want to use CLK_GET_RATE_NOCACHE in ti_adpll_init_dco I have just one comment below still, once that is addressed: Conditionally-acked-by: Tero Kristo Stephen / Michael, can you pick this up for next merge? I don't have anything else coming for the window this time, and I am probably going to be on vacation just nicely to not be able to push anything anyway. + +/* Warn if clkout or clkoutx2 try to set unavailable parent */ +static int ti_adpll_clkout_set_parent(struct clk_hw *hw, u8 index) +{ + struct ti_adpll_clkout_data *co = to_clkout(hw); + struct ti_adpll_data *d = co->adpll; + + if (ti_adpll_clock_is_bypass(d) != index) + return -EAGAIN; + I think this part is still somewhat weird. You are not doing anything useful in this function, so do you need to implement it at all? Just returning -EINVAL always might work also. EAGAIN is wrong return value anyway as it can pretty much never succeed. -Tero + return 0; +} + -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Add clocks for dm814x ADPLL
On 12/22/2015 05:53 PM, Tony Lindgren wrote: These use the standard clock bindings and now we can make some of the fixed clocks into real clocks. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- Changes since v1: - Updated for changed clock names for "dcoclkldo" - Merged in the dra62x changes --- arch/arm/boot/dts/dm814x-clocks.dtsi | 256 ++- arch/arm/boot/dts/dra62x-clocks.dtsi | 26 2 files changed, 251 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi index e0ea6a9..b75ca91 100644 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -4,6 +4,170 @@ * published by the Free Software Foundation. */ +&pllss { + /* +* See TRM "2.6.10 Connected outputso DPLLS" and +* "2.6.11 Connected Outputs of DPLLJ". Only clkout is +* connected except for hdmi and usb. +*/ + adpll_mpu_ck: adpll@40 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-s-clock"; + reg = <0x40 0x40>; + clocks = <&devosc_ck &devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow", "clkinphif"; + clock-indices = <0>, <1>, <2>, <3>; + clock-output-names = "481c5040.adpll.dcoclkldo", +"481c5040.adpll.clkout", +"481c5040.adpll.clkoutx2", +"481c5040.adpll.clkouthif"; Discussed this offline, but looks like most of the clock output names can probably be generated runtime, as they seem duplicate across adplls? Including the address component. Based on the offline discussion though: Acked-by: Tero Kristo -Tero + }; + + adpll_dsp_ck: adpll@80 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x80 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-indices = <0>, <1>, <2>; + clock-output-names = "481c5080.adpll.dcoclkldo", +"481c5080.adpll.clkout", +"481c5080.adpll.clkoutldo"; + }; + + adpll_sgx_ck: adpll@b0 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0xb0 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-indices = <0>, <1>, <2>; + clock-output-names = "481c50b0.adpll.dcoclkldo", +"481c50b0.adpll.clkout", +"481c50b0.adpll.clkoutldo"; + }; + + adpll_hdvic_ck: adpll@e0 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0xe0 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-indices = <0>, <1>, <2>; + clock-output-names = "481c50e0.adpll.dcoclkldo", +"481c50e0.adpll.clkout", +"481c50e0.adpll.clkoutldo"; + }; + + adpll_l3_ck: adpll@110 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x110 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-indices = <0>, <1>, <2>; + clock-output-names = "481c5110.adpll.dcoclkldo", +"481c5110.adpll.clkout", +"481c5110.adpll.clkoutldo"; + }; + + adpll_isp_ck: adpll@140 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x140 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-indices = <0>, <1>, <2>; + clock-output-names = "481c5140.adpll.dcoclkldo", +"481c51
[RFC 7/9] ARM: dts: omap4: add hwmod module clocks
Add clock nodes for the SoC hwmods. This is done in preparation to remove hwmod data from kernel, hwmod will use the clock nodes instead for module level enable / disable logic. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 854 +--- 1 file changed, 781 insertions(+), 73 deletions(-) diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index f2c48f0..1d3e0b8 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -183,6 +183,20 @@ reg = <0x0528>; }; + aess_mod_ck: aess_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0528>; + clocks = <&aess_fclk>; + }; + + mcpdm_mod_ck: mcpdm_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0530>; + clocks = <&pad_clks_ck>; + }; + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { #clock-cells = <0>; compatible = "ti,divider-clock"; @@ -194,6 +208,34 @@ ti,invert-autoidle-bit; }; + mpu_mod_ck: mpu_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0320>; + clocks = <&dpll_mpu_m2_ck>; + }; + + mmu_dsp_mod_ck: mmu_dsp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0420>; + clocks = <&dpll_iva_m4x2_ck>; + }; + + dsp_mod_ck: dsp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0420>; + clocks = <&dpll_iva_m4x2_ck>; + }; + + l4_abe_mod_ck: l4_abe_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0520>; + clocks = <&ocp_abe_iclk>; + }; + core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -480,6 +522,13 @@ reg = <0x0538>; }; + dmic_mod_ck: dmic_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0538>; + clocks = <&func_dmic_abe_gfclk>; + }; + func_dmic_abe_gfclk: func_dmic_abe_gfclk { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -496,6 +545,13 @@ reg = <0x0540>; }; + mcasp_mod_ck: mcasp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0540>; + clocks = <&func_mcasp_abe_gfclk>; + }; + func_mcasp_abe_gfclk: func_mcasp_abe_gfclk { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -520,6 +576,13 @@ reg = <0x0548>; }; + mcbsp1_mod_ck: mcbsp1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0548>; + clocks = <&func_mcbsp1_gfclk>; + }; + mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -536,6 +599,13 @@ reg = <0x0550>; }; + mcbsp2_mod_ck: mcbsp2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0550>; + clocks = <&func_mcbsp2_gfclk>; + }; + mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; @@ -552,6 +622,13 @@ reg = <0x0558>; }; + mcbsp3_mod_ck: mcbsp3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0558>; + clocks = <&func_mcbsp3_gfclk>; + }; + slimbus1_fclk_1: slimbus1_fclk_1 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -568,52 +645,66 @@ reg = <0x0560>; }; - slimbus1_fclk_2: slimbus1_fclk_2 { + slimbus1_mod_ck: slimbus1_mod
[RFC 9/9] clk: ti: omap4: update clock aliases to reflect new module clocks
The clock data in DT has been updated, and the clock aliases must be updated to match. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-44xx.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 7a8b51b..81cd26e 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -164,17 +164,17 @@ static struct ti_dt_clk omap44xx_clks[] = { DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"), DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"), DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"), - DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"), - DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"), - DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"), - DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"), - DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"), - DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"), - DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"), - DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"), - DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"), - DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"), - DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"), + DT_CLK(NULL, "timer1_mod_ck", "timer1_mod_ck"), + DT_CLK(NULL, "timer10_mod_ck", "timer10_mod_ck"), + DT_CLK(NULL, "timer11_mod_ck", "timer11_mod_ck"), + DT_CLK(NULL, "timer2_mod_ck", "timer2_mod_ck"), + DT_CLK(NULL, "timer3_mod_ck", "timer3_mod_ck"), + DT_CLK(NULL, "timer4_mod_ck", "timer4_mod_ck"), + DT_CLK(NULL, "timer5_mod_ck", "timer5_mod_ck"), + DT_CLK(NULL, "timer6_mod_ck", "timer6_mod_ck"), + DT_CLK(NULL, "timer7_mod_ck", "timer7_mod_ck"), + DT_CLK(NULL, "timer8_mod_ck", "timer8_mod_ck"), + DT_CLK(NULL, "timer9_mod_ck", "timer9_mod_ck"), DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"), DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"), DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 3/9] clk: ti: remove un-used definitions from public clk_hw_omap struct
Clksel support has been deprecated a while back, so remove these from the struct also. Signed-off-by: Tero Kristo --- include/linux/clk/ti.h |4 1 file changed, 4 deletions(-) diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 223be69..ec5613a 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -127,8 +127,6 @@ struct clk_hw_omap_ops { * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) * @flags: see "struct clk.flags possibilities" above * @clksel_reg: for clksel clks, register va containing src/divisor select - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector - * @clksel: for clksel clks, pointer to struct clksel for this clock * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock * @clkdm_name: clockdomain name that this clock is contained in * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime @@ -143,8 +141,6 @@ struct clk_hw_omap { u8 enable_bit; u8 flags; void __iomem*clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; struct dpll_data*dpll_data; const char *clkdm_name; struct clockdomain *clkdm; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 6/9] clk: ti: add support for omap4 module clocks
Previously, hwmod core has been used for controlling the hwmod level clocks. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with common clock framework. Add support for new clock type under the TI clock driver, which will be used to convert all the existing hwmdo clocks to. This helps to get rid of the clock related hwmod data from kernel and instead parsing this from DT. Signed-off-by: Tero Kristo --- drivers/clk/ti/Makefile |3 +- drivers/clk/ti/clkt_mod.c | 351 + include/linux/clk/ti.h|2 + 3 files changed, 355 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/ti/clkt_mod.c diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index d4ac960..d1b9d41 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,7 +1,8 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ - clkt_dpll.o clkt_iclk.o clkt_dflt.o + clkt_dpll.o clkt_iclk.o clkt_dflt.o \ + clkt_mod.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o diff --git a/drivers/clk/ti/clkt_mod.c b/drivers/clk/ti/clkt_mod.c new file mode 100644 index 000..186d5f7 --- /dev/null +++ b/drivers/clk/ti/clkt_mod.c @@ -0,0 +1,351 @@ +/* + * OMAP hardware module clock support + * + * Copyright (C) 2015 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "clock.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define OMAP4_MODULEMODE_MASK 0x3 + +#define MODULEMODE_HWCTRL 0x1 +#define MODULEMODE_SWCTRL 0x2 + +#define OMAP4_IDLEST_MASK (0x3 << 16) +#define OMAP4_IDLEST_SHIFT 16 + +#define CLKCTRL_IDLEST_FUNCTIONAL 0x0 +#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 +#define CLKCTRL_IDLEST_DISABLED0x3 + +#define OMAP4_MAX_MODULE_READY_TIME2000 +#define OMAP4_MAX_MODULE_DISABLE_TIME 5000 + +static u32 _omap4_idlest(u32 val) +{ + val &= OMAP4_IDLEST_MASK; + val >>= OMAP4_IDLEST_SHIFT; + + return val; +} + +static bool _omap4_is_idle(u32 val) +{ + val = _omap4_idlest(val); + + return val == CLKCTRL_IDLEST_DISABLED; +} + +static bool _omap4_is_ready(u32 val) +{ + val = _omap4_idlest(val); + + return val == CLKCTRL_IDLEST_FUNCTIONAL || + val == CLKCTRL_IDLEST_INTERFACE_IDLE; +} + +static int _omap4_hwmod_clk_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 val; + int timeout = 0; + int ret; + + if (!clk->enable_bit) + return 0; + + if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, +"%s: could not enable %s's clockdomain %s: %d\n", +__func__, clk_hw_get_name(hw), +clk->clkdm_name, ret); + return ret; + } + } + + val = ti_clk_ll_ops->clk_readl(clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK; + val |= clk->enable_bit; + + ti_clk_ll_ops->clk_writel(val, clk->enable_reg); + + /* Wait until module is enabled */ + while (!_omap4_is_ready(val)) { + udelay(1); + timeout++; + if (timeout > OMAP4_MAX_MODULE_READY_TIME) { + pr_err("%s: failed to enable\n", clk_hw_get_name(hw)); + return -EBUSY; + } + val = ti_clk_ll_ops->clk_readl(clk->enable_reg); + } + + return 0; +} + +static void _omap4_hwmod_clk_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 val; + int timeout = 0; + + i
[RFC 0/9] ARM: OMAP4: hwmod clkctrl conversion to DT + clock driver
Hi, This series adds support for hwmod gate clock type, and changes OMAP4 as an example to use the new clock type, converting the existing hwmod_data clkctrl definitions to clock nodes under device tree. Some additional magic is required for handling timer clocks, as the clock driver assumes it can do mux operations on the hwmod main clock, the mux-mod clock type variants are for this purpose. The data files have been automatically converted by scripting, so doing the same conversion for any AMxyz / OMAP4+ SoC should be relatively easy to do. Boot tested on OMAP4 panda ES board, also tried that suspend-resume / cpuidle works fine. Testing done on top of 4.4-rc3. This series is one part of the work to get rid of hwmod data from kernel. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 8/9] ARM: OMAP4: hwmod_data: use module clocks from DT
Replace the usage of prcm->clkstctrl with main_clk:s provided via DT. This is done in preparation to get rid of hwmod data from kernel. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 339 1 file changed, 95 insertions(+), 244 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index a5e444b..8da75eb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -67,10 +67,10 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { .clkdm_name = "l3_emif_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, }, }, + .main_clk = "dmm_mod_ck", }; /* @@ -88,11 +88,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { .clkdm_name = "l3_instr_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, + .main_clk = "l3_instr_mod_ck", }; /* l3_main_1 */ @@ -102,10 +101,10 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .clkdm_name = "l3_1_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, }, }, + .main_clk = "l3_main_1_mod_ck", }; /* l3_main_2 */ @@ -115,10 +114,10 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .clkdm_name = "l3_2_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, }, }, + .main_clk = "l3_main_2_mod_ck", }; /* l3_main_3 */ @@ -128,11 +127,10 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { .clkdm_name = "l3_instr_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, + .main_clk = "l3_main_3_mod_ck", }; /* @@ -150,12 +148,12 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { .clkdm_name = "abe_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, .flags= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, }, }, + .main_clk = "l4_abe_mod_ck", }; /* l4_cfg */ @@ -165,10 +163,10 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .clkdm_name = "l4_cfg_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, }, }, + .main_clk = "l4_cfg_mod_ck", }; /* l4_per */ @@ -178,10 +176,10 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { .clkdm_name = "l4_per_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, }, }, + .main_clk = "l4_per_mod_ck", }; /* l4_wkup */ @@ -191,10 +189,10 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .clkdm_name = "l4_wkup_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, }, }, + .main_clk = "l4_wkup_mod_ck", }; /* @@ -232,11 +230,10 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { .clkdm_name = "l3_instr_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, -
[RFC 2/9] ARM: OMAP2+: hwmod: initialize main clocks directly from DT
This avoids the need to add clock aliases under drivers/clk/ti/clk-xyz.c files. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 48495ad..5fa8965 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -786,11 +786,20 @@ static int _init_main_clk(struct omap_hwmod *oh) if (!oh->main_clk) return 0; - oh->_clk = clk_get(NULL, oh->main_clk); - if (IS_ERR(oh->_clk)) { - pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", - oh->name, oh->main_clk); - return -EINVAL; + if (of_have_populated_dt()) { + struct of_phandle_args clkspec; + + clkspec.np = of_find_node_by_name(NULL, oh->main_clk); + oh->_clk = of_clk_get_from_provider(&clkspec); + } + + if (!oh->_clk) { + oh->_clk = clk_get(NULL, oh->main_clk); + if (IS_ERR(oh->_clk)) { + pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", + oh->name, oh->main_clk); + return -EINVAL; + } } /* * HACK: This needs a re-visit once clk_prepare() is implemented -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 4/9] clk: ti: mux: export mux clock APIs locally
get_parent and set_parent are going to be required by the support of module clocks, so export these locally. Signed-off-by: Tero Kristo --- drivers/clk/ti/clock.h |3 +++ drivers/clk/ti/mux.c |4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 90f3f47..7eca8a1 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -224,6 +224,9 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; extern const struct clk_ops ti_clk_divider_ops; extern const struct clk_ops ti_clk_mux_ops; +u8 ti_clk_mux_get_parent(struct clk_hw *hw); +int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index); + int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index 69f08a1..d723dad 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -28,7 +28,7 @@ #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) -static u8 ti_clk_mux_get_parent(struct clk_hw *hw) +u8 ti_clk_mux_get_parent(struct clk_hw *hw) { struct clk_mux *mux = to_clk_mux(hw); int num_parents = clk_hw_get_num_parents(hw); @@ -65,7 +65,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw) return val; } -static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) +int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct clk_mux *mux = to_clk_mux(hw); u32 val; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 1/9] ARM: OMAP2+: omap_device: create clock alias purely from DT data
This avoids the need to add most of the clock aliases under drivers/clk/ti/clk-xyz.c files. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_device.c | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 72ebc4c..3389ce7 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -62,6 +62,18 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, return; } + r = clk_get_sys(NULL, clk_name); + + if (IS_ERR(r) && of_have_populated_dt()) { + struct of_phandle_args clkspec; + + clkspec.np = of_find_node_by_name(NULL, clk_name); + + r = of_clk_get_from_provider(&clkspec); + + clk_register_clkdev(r, clk_name, NULL); + } + rc = clk_add_alias(clk_alias, dev_name(&od->pdev->dev), clk_name, NULL); if (rc) { if (rc == -ENODEV || rc == -ENOMEM) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 5/9] dt-bindings: clk: ti: Document module clock type
Document the new TI module clock type, which is intended to replace the internal clock control handling within omap_hwmod. Module clock is effectively a gate clock controlling both interface and functional clocks for a single hardware IP block. Signed-off-by: Tero Kristo --- .../devicetree/bindings/clock/ti/module.txt| 57 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/module.txt diff --git a/Documentation/devicetree/bindings/clock/ti/module.txt b/Documentation/devicetree/bindings/clock/ti/module.txt new file mode 100644 index 000..a5f70f2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/module.txt @@ -0,0 +1,57 @@ +Binding for Texas Instruments module clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. This clock is +quite much similar to the basic gate-clock [2], however, internally +it controls an OMAP module clock, which effectively handles +both interface and functional clocks for a single module. In some +cases, support for mux clock [3] is composited to the same clock node, +currently only needed for proper support of timer module clocks. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/gate.txt +[3] Documentation/devicetree/bindings/clock/ti/mux.txt + +Required properties: +- compatible : shall be one of: + "ti,omap4-mod-clock" - basic module clock, no gating supported + "ti,omap4-hw-mod-clock" - module clock with hardware gating support + "ti,omap4-sw-mod-clock" - module clock with software forced gating support + "ti,omap4-mux-mod-clock" - composite clock with mux and module clocks, no +gating supported + "ti,omap4-hw-mux-mod-clock" - composite clock with mux and module clocks, + with hardware gating + "ti,omap4-sw-mux-mod-clock" - composite clock with mux and module clocks, + with software forced gating + +- #clock-cells : from common clock binding; shall be set to 0 +- clocks : link to phandle of parent clock(s) +- reg : offset for register controlling adjustable gate and optional mux + +Optional properties: +- ti,bit-shift : bit shift for programming the clock mux, only needed for +the nodes of the mux variant + +Examples: + timer6_mod_ck: timer6_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x0570>; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + i2c1_mod_ck: i2c1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14a0>; + clocks = <&func_96m_fclk>; + }; + + hsi_mod_ck: hsi_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1338>; + clocks = <&hsi_fck>; + }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2] clk: ti: omap5+: dpll: implement errata i810
Errata i810 states that DPLL controller can get stuck while transitioning to a power saving state, while its M/N ratio is being re-programmed. As a workaround, before re-programming the M/N ratio, SW has to ensure the DPLL cannot start an idle state transition. SW can disable DPLL idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request active by setting a dependent clock domain in SW_WKUP. This errata is known to impact OMAP5 and DRA7 chips, but lets enable it unconditionally to avoid any potential problems with earlier generation SoCs also. Signed-off-by: Tero Kristo --- v2: made the fix to be applied unconditionally on all OMAP3+ SoCs drivers/clk/ti/dpll3xxx.c | 20 +++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index f4dec00..cb26eb8 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -305,7 +305,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) { struct dpll_data *dd = clk->dpll_data; - u8 dco, sd_div; + u8 dco, sd_div, ai = 0; u32 v; /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ @@ -350,6 +350,21 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) v |= sd_div << __ffs(dd->sddiv_mask); } + /* +* Errata i810 - DPLL controller can get stuck while transitioning +* to a power saving state. Software must ensure the DPLL can not +* transition to a low power state while changing M/N values. +* Easiest way to accomplish this is to prevent DPLL autoidle +* before doing the M/N re-program. +*/ + ai = omap3_dpll_autoidle_read(clk); + if (ai) { + omap3_dpll_deny_idle(clk); + + /* OCP barrier */ + omap3_dpll_autoidle_read(clk); + } + ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); /* Set 4X multiplier and low-power mode */ @@ -379,6 +394,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) _omap3_noncore_dpll_lock(clk); + if (ai) + omap3_dpll_allow_idle(clk); + return 0; } -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: ti: omap5+: dpll: implement errata i810
On 12/03/2015 06:48 PM, Tony Lindgren wrote: * Tero Kristo [151130 06:44]: + /* +* Errata i810 - DPLL controller can get stuck while transitioning +* to a power saving state. Software must ensure the DPLL can not +* transition to a low power state while changing M/N values. +* Easiest way to accomplish this is to prevent DPLL autoidle +* before doing the M/N re-program. +*/ + errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810; + + if (errata_i810) { + ai = omap3_dpll_autoidle_read(clk); + if (ai) { + omap3_dpll_deny_idle(clk); + + /* OCP barrier */ + omap3_dpll_autoidle_read(clk); + } + } Should we just do this unconditionally? It seems like disabling the autoidle always before reprogramming is a good idea. Well, that is a few extra register accesses, but given the DPLL re-programming is a slow operation it probably does not matter. Let me spin a new version of this patch, it will avoid the need for the errata flag also. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] clk: ti: Add support for dm814x ADPLL
On 12/11/2015 04:26 AM, Tony Lindgren wrote: On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL. Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall levels to postcore_initcall". Also note that this patch does not implement clk_set_rate, that will be posted later on when available. Signed-off-by: Tony Lindgren Hi Tony, Looks mostly good to me, added some minor comments inline below. Sorry again for latencies in my replies. -Tero --- Updated to use adpll_lj and adpll_s naming and s/FAPLL/ADPLL/ in the documentation as suggested by Matthijs. If no other comments, I'd like to have this patch alone in an immutable branch againt v4.4-rc1 that I can merge in too. Maybe Tero wants to do that and merge this along with the other omap clock patches? --- .../devicetree/bindings/clock/ti/adpll.txt | 42 + drivers/clk/Kconfig|1 + drivers/clk/ti/Kconfig |6 + drivers/clk/ti/Makefile|2 + drivers/clk/ti/adpll.c | 1028 drivers/clk/ti/clk-814x.c | 53 + 6 files changed, 1132 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/adpll.txt create mode 100644 drivers/clk/ti/Kconfig create mode 100644 drivers/clk/ti/adpll.c diff --git a/Documentation/devicetree/bindings/clock/ti/adpll.txt b/Documentation/devicetree/bindings/clock/ti/adpll.txt new file mode 100644 index 000..8d951de --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/adpll.txt @@ -0,0 +1,42 @@ +Binding for Texas Instruments ADPLL clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped ADPLL with two to three selectable input clocks +and three to four children.. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of "ti,dm814-adpll-s-clock" or + "ti,dm814-adpll-j-clock" depending on the type of the ADPLL +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks (clk-ref and clk-bypass) +- reg : address and length of the register set for controlling the ADPLL. + +Examples: + adpll_mpu_ck: adpll@40 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-s-clock"; + reg = <0x40 0x40>; + clocks = <&devosc_ck &devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow", "clkinphif"; + clock-indices = <0>, <1>, <2>, <3>; + clock-output-names = "481c5040.adpll.dcoclkldo", +"481c5040.adpll.clkout", +"481c5040.adpll.clkoutx2", +"481c5040.adpll.clkouthif"; + }; + + adpll_dsp_ck: adpll@80 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x80 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-indices = <0>, <1>, <2>; + clock-output-names = "481c5080.adpll.clkdcoldo", +"481c5080.adpll.clkout", +"481c5080.adpll.clkoutldo"; + }; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c3e3a02f..c0c9868 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -190,6 +190,7 @@ config COMMON_CLK_CDCE706 source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" +source "drivers/clk/ti/Kconfig" source "drivers/clk/qcom/Kconfig" endmenu diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig new file mode 100644 index 000..a9d5474 --- /dev/null +++ b/drivers/clk/ti/Kconfig @@ -0,0 +1,6 @@ +config COMMON_CLK_TI_ADPLL + tristate "Clock driver for dm814x ADPLL" + depends on ARCH_OMAP2PLUS + default y if SOC_TI81XX + ---help--- + ADPLL clock driver for the dm814x SoC using common clock framework. diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index d4ac960..dfe91d7 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -18,3 +18,5 @@ obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o ifdef CONFIG_ATAGS obj-$(CONFIG_ARCH_OMAP3)+= clk-3xxx-legacy.o endif + +obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c new file mode 100644 index 000..2c75c55 --- /dev/null +++ b/drivers/clk/ti/adpll.c @@ -0,0 +1,1028 @@ +/* + * This program is free software; you can redistribute
Re: [PATCH 02/10] clk: ti: Add few dm814x clock aliases
On 12/08/2015 10:11 PM, Tony Lindgren wrote: * Tero Kristo [151208 11:25]: On 12/08/2015 06:57 PM, Tony Lindgren wrote: Anybody from the clock department care to ack this one? Sorry been rather busy lately... I'd like to get this series into Linux next as it fixes some some issues. Yeah looks good to me, don't have access to dm814x so can't test. Acked-by: Tero Kristo Thanks. Are you planning to push this via omap tree if this is critical for you? Yes this series needs to be merged in certain order to keep t410 booting. Should not conflict with anything else AFAIK. Ok at least I am fine with that. The dm81xx clock alias file is pretty independent of anything else. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/10] clk: ti: Add few dm814x clock aliases
On 12/08/2015 06:57 PM, Tony Lindgren wrote: * Tony Lindgren [151201 15:43]: The timer clock aliases are needed early on dm814x. Let's also add the aliases for the interconnects and MMC. Cc: Michael Turquette Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Anybody from the clock department care to ack this one? Sorry been rather busy lately... I'd like to get this series into Linux next as it fixes some some issues. Yeah looks good to me, don't have access to dm814x so can't test. Acked-by: Tero Kristo Are you planning to push this via omap tree if this is critical for you? -Tero Regards, Tony drivers/clk/ti/clk-814x.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c index e172920..9e85fcc 100644 --- a/drivers/clk/ti/clk-814x.c +++ b/drivers/clk/ti/clk-814x.c @@ -14,10 +14,14 @@ static struct ti_dt_clk dm814_clks[] = { DT_CLK(NULL, "devosc_ck", "devosc_ck"), DT_CLK(NULL, "mpu_ck", "mpu_ck"), DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"), + DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"), DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"), + DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"), DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"), DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"), DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), + DT_CLK(NULL, "timer1_fck", "timer1_fck"), + DT_CLK(NULL, "timer2_fck", "timer2_fck"), DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), { .node_name = NULL }, -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] clk: ti: omap5+: dpll: implement errata i810
Errata i810 states that DPLL controller can get stuck while transitioning to a power saving state, while its M/N ratio is being re-programmed. As a workaround, before re-programming the M/N ratio, SW has to ensure the DPLL cannot start an idle state transition. SW can disable DPLL idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request active by setting a dependent clock domain in SW_WKUP. This errata impacts OMAP5 and DRA7 chips, so enable the errata for these. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c |4 drivers/clk/ti/dpll3xxx.c | 25 - include/linux/clk/ti.h |1 + 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index acb60ed..d058125 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -225,5 +225,9 @@ void __init ti_clk_init_features(void) if (omap_rev() == OMAP3430_REV_ES1_0) features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; + /* Errata I810 for omap5 / dra7 */ + if (soc_is_omap54xx() || soc_is_dra7xx()) + features.flags |= TI_CLK_ERRATA_I810; + ti_clk_setup_features(&features); } diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index f4dec00..1c30038 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -305,8 +305,9 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) { struct dpll_data *dd = clk->dpll_data; - u8 dco, sd_div; + u8 dco, sd_div, ai = 0; u32 v; + bool errata_i810; /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ _omap3_noncore_dpll_bypass(clk); @@ -350,6 +351,25 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) v |= sd_div << __ffs(dd->sddiv_mask); } + /* +* Errata i810 - DPLL controller can get stuck while transitioning +* to a power saving state. Software must ensure the DPLL can not +* transition to a low power state while changing M/N values. +* Easiest way to accomplish this is to prevent DPLL autoidle +* before doing the M/N re-program. +*/ + errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810; + + if (errata_i810) { + ai = omap3_dpll_autoidle_read(clk); + if (ai) { + omap3_dpll_deny_idle(clk); + + /* OCP barrier */ + omap3_dpll_autoidle_read(clk); + } + } + ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); /* Set 4X multiplier and low-power mode */ @@ -379,6 +399,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) _omap3_noncore_dpll_lock(clk); + if (errata_i810 && ai) + omap3_dpll_allow_idle(clk); + return 0; } diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 223be69..75205df 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -286,6 +286,7 @@ struct ti_clk_features { #define TI_CLK_DPLL_HAS_FREQSELBIT(0) #define TI_CLK_DPLL4_DENY_REPROGRAMBIT(1) #define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) +#define TI_CLK_ERRATA_I810 BIT(3) void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [4.4-rc][PATCH] ARM: dts: am4372: fix clock source for arm twd and global timers
On 11/30/2015 03:49 PM, Grygorii Strashko wrote: On 11/30/2015 03:32 PM, Tero Kristo wrote: On 11/30/2015 01:53 PM, Grygorii Strashko wrote: On 11/30/2015 10:25 AM, Tero Kristo wrote: On 11/27/2015 09:44 PM, Grygorii Strashko wrote: ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2. But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result. Timekeeping core misbehaves. For example, execution of command "sleep 5" will take 10 sec instead of 5. Hence, fix it by adding mpu_periphclk ("fixed-factor-clock") and use it for clocking ARM TWD and Global timer (same way as on OMAP4). Cc: Tony Lindgren Cc: Felipe Balbi Cc: Tero Kristo Fixes:commit 8cbd4c2f6a99 ("arm: boot: dts: am4372: add ARM timers and SCU nodes") Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/am4372.dtsi| 4 ++-- arch/arm/boot/dts/am43xx-clocks.dtsi | 8 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d83ff9c..de8791a 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -74,7 +74,7 @@ reg = <0x48240200 0x100>; interrupts = ; interrupt-parent = <&gic>; -clocks = <&dpll_mpu_m2_ck>; +clocks = <&mpu_periphclk>; }; local_timer: timer@48240600 { @@ -82,7 +82,7 @@ reg = <0x48240600 0x100>; interrupts = ; interrupt-parent = <&gic>; -clocks = <&dpll_mpu_m2_ck>; +clocks = <&mpu_periphclk>; }; l2-cache-controller@48242000 { diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index cc88728..2ff58b1 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -259,6 +259,14 @@ ti,invert-autoidle-bit; }; +mpu_periphclk: mpu_periphclk { +#clock-cells = <0>; +compatible = "fixed-factor-clock"; +clocks = <&dpll_mpu_ck>; I don't think this is correct, ARM core is fed dpll_mpu_m2_ck, where the divisor value can potentially differ from 1. If you feed this clock directly from dpll_mpu_ck, you bypass this divisor. Sry. My mistake. I'll update it to use dpll_mpu_m2_ck. Did you check what is the impact of cpufreq on the ARM TWD/timers? TWD is cpufreq friendly, ARM GT is not. I think the TWD kick period changes with cpufreq also right? linux/arch/arm/kernel/smp_twd.c has code to handle cpufreq. How are the clocks handled with cpufreq? The user just needs to understand that the timers will be screwed if he uses ARM GT? Should we add some sort of dependency to disable the ARM GT if cpufreq is enabled? Yep. May be, but very good question is how to do that in case of OMAP multiplatform build which enables most of all config options at once. There two threads related to this: [1] http://www.spinics.net/lists/arm-kernel/msg459649.html [2] http://www.spinics.net/lists/arm-kernel/msg461141.html Personally, I've do not see better way than [2] right now. Yeah, [2] seems the way to go. +clock-mult = <1>; +clock-div = <2>; +}; + dpll_ddr_ck: dpll_ddr_ck { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; By the way, does this patch is still correct taking into account dependency from cpufreq? Does it make sense update it to use dpll_mpu_ck and resend? Well, this patch is still valid, as the selection of the clocksource should be done elsewhere, and this patch should not care about that. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [4.4-rc][PATCH] ARM: dts: am4372: fix clock source for arm twd and global timers
On 11/30/2015 01:53 PM, Grygorii Strashko wrote: On 11/30/2015 10:25 AM, Tero Kristo wrote: On 11/27/2015 09:44 PM, Grygorii Strashko wrote: ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2. But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result. Timekeeping core misbehaves. For example, execution of command "sleep 5" will take 10 sec instead of 5. Hence, fix it by adding mpu_periphclk ("fixed-factor-clock") and use it for clocking ARM TWD and Global timer (same way as on OMAP4). Cc: Tony Lindgren Cc: Felipe Balbi Cc: Tero Kristo Fixes:commit 8cbd4c2f6a99 ("arm: boot: dts: am4372: add ARM timers and SCU nodes") Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/am4372.dtsi| 4 ++-- arch/arm/boot/dts/am43xx-clocks.dtsi | 8 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d83ff9c..de8791a 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -74,7 +74,7 @@ reg = <0x48240200 0x100>; interrupts = ; interrupt-parent = <&gic>; -clocks = <&dpll_mpu_m2_ck>; +clocks = <&mpu_periphclk>; }; local_timer: timer@48240600 { @@ -82,7 +82,7 @@ reg = <0x48240600 0x100>; interrupts = ; interrupt-parent = <&gic>; -clocks = <&dpll_mpu_m2_ck>; +clocks = <&mpu_periphclk>; }; l2-cache-controller@48242000 { diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index cc88728..2ff58b1 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -259,6 +259,14 @@ ti,invert-autoidle-bit; }; +mpu_periphclk: mpu_periphclk { +#clock-cells = <0>; +compatible = "fixed-factor-clock"; +clocks = <&dpll_mpu_ck>; I don't think this is correct, ARM core is fed dpll_mpu_m2_ck, where the divisor value can potentially differ from 1. If you feed this clock directly from dpll_mpu_ck, you bypass this divisor. Sry. My mistake. I'll update it to use dpll_mpu_m2_ck. Did you check what is the impact of cpufreq on the ARM TWD/timers? TWD is cpufreq friendly, ARM GT is not. I think the TWD kick period changes with cpufreq also right? How are the clocks handled with cpufreq? The user just needs to understand that the timers will be screwed if he uses ARM GT? Should we add some sort of dependency to disable the ARM GT if cpufreq is enabled? -Tero +clock-mult = <1>; +clock-div = <2>; +}; + dpll_ddr_ck: dpll_ddr_ck { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [4.4-rc][PATCH] ARM: dts: am4372: fix clock source for arm twd and global timers
On 11/27/2015 09:44 PM, Grygorii Strashko wrote: ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2. But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result. Timekeeping core misbehaves. For example, execution of command "sleep 5" will take 10 sec instead of 5. Hence, fix it by adding mpu_periphclk ("fixed-factor-clock") and use it for clocking ARM TWD and Global timer (same way as on OMAP4). Cc: Tony Lindgren Cc: Felipe Balbi Cc: Tero Kristo Fixes:commit 8cbd4c2f6a99 ("arm: boot: dts: am4372: add ARM timers and SCU nodes") Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/am4372.dtsi| 4 ++-- arch/arm/boot/dts/am43xx-clocks.dtsi | 8 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d83ff9c..de8791a 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -74,7 +74,7 @@ reg = <0x48240200 0x100>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&dpll_mpu_m2_ck>; + clocks = <&mpu_periphclk>; }; local_timer: timer@48240600 { @@ -82,7 +82,7 @@ reg = <0x48240600 0x100>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&dpll_mpu_m2_ck>; + clocks = <&mpu_periphclk>; }; l2-cache-controller@48242000 { diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index cc88728..2ff58b1 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -259,6 +259,14 @@ ti,invert-autoidle-bit; }; + mpu_periphclk: mpu_periphclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_mpu_ck>; I don't think this is correct, ARM core is fed dpll_mpu_m2_ck, where the divisor value can potentially differ from 1. If you feed this clock directly from dpll_mpu_ck, you bypass this divisor. Did you check what is the impact of cpufreq on the ARM TWD/timers? -Tero + clock-mult = <1>; + clock-div = <2>; + }; + dpll_ddr_ck: dpll_ddr_ck { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/4] clk: ti816x: Add missing dmtimer clkdev entries
On 11/13/2015 06:29 PM, Neil Armstrong wrote: Add missing clkdev dmtimer related entries for dm816x. 32Khz and ext sources were missing. Cc: Brian Hutchinson Acked-by: Tony Lindgren Signed-off-by: Neil Armstrong Your own sign-off should be at the top of the list, fixed this locally myself. Queued for 4.4-rc-fixes, thanks. -Tero --- drivers/clk/ti/clk-816x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c index 1dfad0c..2a5d84f 100644 --- a/drivers/clk/ti/clk-816x.c +++ b/drivers/clk/ti/clk-816x.c @@ -20,6 +20,8 @@ static struct ti_dt_clk dm816x_clks[] = { DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), + DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), + DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), DT_CLK(NULL, "mpu_ck", "mpu_ck"), DT_CLK(NULL, "timer1_fck", "timer1_fck"), DT_CLK(NULL, "timer2_fck", "timer2_fck"), -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] clk: ti: fixes for 4.4-rc
Hi Michael, Stephen, Here are some TI clock driver fixes for 4.4-rc. -Tero The following changes since commit 8005c49d9aea74d382f474ce11afbbc7d7130bec: Linux 4.4-rc1 (2015-11-15 17:00:27 -0800) are available in the git repository at: https://github.com/t-kristo/linux-pm.git for-4.4-rc/ti-clk-fixes for you to fetch changes up to 167af5ef2cdba14ff14a13c91e5532ed479083d8: clk: ti: drop locking code from mux/divider drivers (2015-11-24 11:30:27 +0200) Grygorii Strashko (1): clk: ti: drop locking code from mux/divider drivers Neil Armstrong (1): clk: ti816x: Add missing dmtimer clkdev entries Nicolas Pitre (2): clk: ti: clkt_dpll: fix wrong do_div() usage clk: ti: fapll: fix wrong do_div() usage drivers/clk/ti/clk-816x.c |2 ++ drivers/clk/ti/clkt_dpll.c |4 ++-- drivers/clk/ti/divider.c | 16 +++- drivers/clk/ti/fapll.c |4 ++-- drivers/clk/ti/mux.c | 15 +++ 5 files changed, 12 insertions(+), 29 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: ti: drop locking code from mux/divider drivers
On 10/24/2015 12:10 AM, Grygorii Strashko wrote: On 10/01/2015 10:20 PM, Grygorii Strashko wrote: TI's mux and divider clock drivers do not require locking and they do not initialize internal spinlocks. This code was occasionally copy-posted from generic mux/divider drivers. So remove it. Cc: Tony Lindgren Cc: Sekhar Nori Signed-off-by: Grygorii Strashko --- Gentle ping. Queued for 4.4-rc-fixes, thanks. -Tero drivers/clk/ti/divider.c | 16 +++- drivers/clk/ti/mux.c | 15 +++ 2 files changed, 6 insertions(+), 25 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ti/fapll: fix wrong do_div() usage
On 11/04/2015 06:17 AM, Nicolas Pitre wrote: do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre Fixed Subject locally to format "clk: ti: %s". Queued for 4.4-rc-fixes, thanks. -Tero diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index f4b2e9888b..66a0d0ed8b 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -168,7 +168,7 @@ static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, { struct fapll_data *fd = to_fapll(hw); u32 fapll_n, fapll_p, v; - long long rate; + u64 rate; if (ti_fapll_clock_is_bypass(fd)) return parent_rate; @@ -314,7 +314,7 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, { struct fapll_synth *synth = to_synth(hw); u32 synth_div_m; - long long rate; + u64 rate; /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ if (!synth->div) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ti/clkt_dpll: fix wrong do_div() usage
On 11/04/2015 06:09 AM, Nicolas Pitre wrote: do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre Fixed Subject locally to format "clk: ti: %s". Queued for 4.4-rc fixes, thanks. -Tero diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index 9023ca9caf..b5cc6f66ae 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c @@ -240,7 +240,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) */ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) { - long long dpll_clk; + u64 dpll_clk; u32 dpll_mult, dpll_div, v; struct dpll_data *dd; @@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) dpll_div = v & dd->div1_mask; dpll_div >>= __ffs(dd->div1_mask); - dpll_clk = (long long)clk_get_rate(dd->clk_ref) * dpll_mult; + dpll_clk = (u64)clk_get_rate(dd->clk_ref) * dpll_mult; do_div(dpll_clk, dpll_div + 1); return dpll_clk; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] rtc: ds1307: Fix alarm programming for mcp794xx
mcp794xx alarm registers must be written in BCD format. However, the alarm programming logic neglected this by adding one to the value after bin2bcd conversion has been already done, writing bad values to month register in case the alarm being set is in October. In this case, the alarm month value becomes 0x0a instead of the expected 0x10. Fix by moving the +1 addition within the bin2bcd call also. Fixes: 1d1945d261a2 ("drivers/rtc/rtc-ds1307.c: add alarm support for mcp7941x chips") Signed-off-by: Tero Kristo --- drivers/rtc/rtc-ds1307.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c index a705e64..188006c 100644 --- a/drivers/rtc/rtc-ds1307.c +++ b/drivers/rtc/rtc-ds1307.c @@ -718,9 +718,9 @@ static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) regs[3] = bin2bcd(t->time.tm_sec); regs[4] = bin2bcd(t->time.tm_min); regs[5] = bin2bcd(t->time.tm_hour); - regs[6] = bin2bcd(t->time.tm_wday) + 1; + regs[6] = bin2bcd(t->time.tm_wday + 1); regs[7] = bin2bcd(t->time.tm_mday); - regs[8] = bin2bcd(t->time.tm_mon) + 1; + regs[8] = bin2bcd(t->time.tm_mon + 1); /* Clear the alarm 0 interrupt flag. */ regs[6] &= ~MCP794XX_BIT_ALMX_IF; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2] ARM: OMAP3: clock: remove un-used core dpll re-program code
Remove the OMAP3 core DPLL re-program code, and the associated SRAM code that does the low-level programming of the DPLL divider, idling of the SDRAM etc. This code was never fully implemented in the kernel; things missing were driver side handling of core clock changes (they need to account for their functional clock rate being changed on-the-fly), and the whole framework required for handling this. Thus, there is not much point to keep carrying the low-level support code either. Signed-off-by: Tero Kristo Cc: Tony Lindgren Cc: Paul Walmsley --- Changes since v1: - rebased on top of 4.3-rc4 - removed AFLAGS for sram34xx.S file which has been removed arch/arm/mach-omap2/Makefile |3 - arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 122 --- arch/arm/mach-omap2/sram.c | 25 --- arch/arm/mach-omap2/sram.h | 14 -- arch/arm/mach-omap2/sram34xx.S | 346 5 files changed, 510 deletions(-) delete mode 100644 arch/arm/mach-omap2/clkt34xx_dpll3m2.c delete mode 100644 arch/arm/mach-omap2/sram34xx.S diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 9358696..ceefcee 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -48,11 +48,9 @@ AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec) # Functions loaded to SRAM obj-$(CONFIG_SOC_OMAP2420) += sram242x.o obj-$(CONFIG_SOC_OMAP2430) += sram243x.o -obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o AFLAGS_sram242x.o :=-Wa,-march=armv6 AFLAGS_sram243x.o :=-Wa,-march=armv6 -AFLAGS_sram34xx.o :=-Wa,-march=armv7-a # Restart code (OMAP4/5 currently in omap4-common.c) obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o @@ -186,7 +184,6 @@ obj-$(CONFIG_ARCH_OMAP2)+= clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) -obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_SOC_AM33XX) += $(clock-common) obj-$(CONFIG_SOC_OMAP5)+= $(clock-common) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c deleted file mode 100644 index 3f65213..000 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * OMAP34xx M2 divider clock code - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation - * - * Paul Walmsley - * Jouni Högander - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include "clock.h" -#include "clock3xxx.h" -#include "sdrc.h" -#include "sram.h" - -#define CYCLES_PER_MHZ 100 - -struct clk *sdrc_ick_p, *arm_fck_p; - -/* - * CORE DPLL (DPLL3) M2 divider rate programming functions - * - * These call into SRAM code to do the actual CM writes, since the SDRAM - * is clocked from DPLL3. - */ - -/** - * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider - * @clk: struct clk * of DPLL to set - * @rate: rounded target rate - * - * Program the DPLL M2 divider with the rounded target rate. Returns - * -EINVAL upon error, or 0 upon success. - */ -int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 new_div = 0; - u32 unlock_dll = 0; - u32 c; - unsigned long validrate, sdrcrate, _mpurate; - struct omap_sdrc_params *sdrc_cs0; - struct omap_sdrc_params *sdrc_cs1; - int ret; - unsigned long clkrate; - - if (!clk || !rate) - return -EINVAL; - - new_div = DIV_ROUND_UP(parent_rate, rate); - validrate = parent_rate / new_div; - - if (validrate != rate) - return -EINVAL; - - sdrcrate = clk_get_rate(sdrc_ick_p); - clkrate = clk_hw_get_rate(hw); - if (rate > clkrate) - sdrcrate <<= ((rate / clkrate) >> 1); - else - sdrcrate >>= ((clkrate / rate) >> 1); - - ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); - if (ret) - return -EINVAL; - - if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { - pr_debug("clock: will unlock SDRC DLL\n"); - u
Re: [PATCH] ARM: OMAP3: clock: remove un-used core dpll re-program code
On 10/12/2015 08:01 PM, Tony Lindgren wrote: * Tony Lindgren [150812 03:59]: * Tony Lindgren [150812 00:29]: * Tero Kristo [150716 01:10]: Remove the OMAP3 core DPLL re-program code, and the associated SRAM code that does the low-level programming of the DPLL divider, idling of the SDRAM etc. This code was never fully implemented in the kernel; things missing were driver side handling of core clock changes (they need to account for their functional clock rate being changed on-the-fly), and the whole framework required for handling this. Thus, there is not much point to keep carrying the low-level support code either. OK I'm applying this into omap-for-v4.3/soc. If we ever need the code it will be in the git history. Actually I'll wait on this one and apply it later on as it currently adds merge conflicts into Linux next. Looks like this needs to be updated to apply on v4.3-rc4, can you please repost? Ok, just posted it. -Tero Using v4.3-rc4 as the base for v4.4 because it contains most of the mmc fixes. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: AM35xx: Add M-USB clk device ID
On 10/12/2015 06:22 PM, Rolf Peukert wrote: The glue code in drivers/usb/musb/am35x.c calls clk_get() to get its interface and function clocks for the M-USB controller. These calls fail in the current kernel. This patch adds clock definitions containing the device ID to the list in clk-3xxx.c, so the calls to clk_get() in am35x.c can succeed. Signed-off-by: Rolf Peukert --- drivers/clk/ti/clk-3xxx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 8831e1a..b635deb 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -507,7 +507,9 @@ static struct ti_dt_clk am35xx_clks[] = { DT_CLK("davinci_mdio.0", NULL, "emac_fck"), DT_CLK("vpfe-capture", "master", "vpfe_ick"), DT_CLK("vpfe-capture", "slave", "vpfe_fck"), + DT_CLK("5c04.am35x_otg_hs", "ick", "hsotgusb_ick_am35xx"), DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), + DT_CLK("5c04.am35x_otg_hs", "fck", "hsotgusb_fck_am35xx"), DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), DT_CLK(NULL, "hecc_ck", "hecc_ck"), DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), Adding clock aliases should be avoided, isn't there any other way to fix this issue? Like adding clocks = <&xyz> references under the DT node? -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: DM3730 vs 3630 DSS Cock dividers
On 10/12/2015 10:35 PM, Tony Lindgren wrote: * Tomi Valkeinen [151012 11:08]: On 12.10.2015 19:00, Tony Lindgren wrote: * Adam Ford [151010 13:29]: Tomi and Tony, I am working on the LogicPD DM3730 Torpedo module. If I try to use the DSS, I get the same errors as mentioned in these previous messages found here: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/255103.html The patch is basicaly: * >> drivers/video/fbdev/omap2/dss/dss.c | 5 +++-- *>* >> 1 file changed, 3 insertions(+), 2 deletions(-) *>* >> *>* >> diff --git a/drivers/video/fbdev/omap2/dss/dss.c b/drivers/video/fbdev/omap2/dss/dss.c *>* >> index d55266c..ad6561f 100644 *>* >> --- a/drivers/video/fbdev/omap2/dss/dss.c *>* >> +++ b/drivers/video/fbdev/omap2/dss/dss.c *>* >> @@ -707,9 +707,10 @@ static const struct dss_features omap34xx_dss_feats __initconst = { *>* >> .dpi_select_source = &dss_dpi_select_source_omap2_omap3, *>* >> }; *>* >> *>* >> +/* Supposedly 3630 can use div 32 mult 2, but that needs to be rechecked */ *>* >> static const struct dss_features omap3630_dss_feats __initconst = { *>* >> - .fck_div_max= 32, *>* >> - .dss_fck_multiplier = 1, *>* >> + .fck_div_max= 16, *>* >> + .dss_fck_multiplier = 2, *>* > *>* > These values tell about the clock hardware, they are not settings that *>* > can be changed to change the clock. OMAP3630 has a fixed x2 multiplier *>* > and a divider with maximum value of 16. *>* > *>* > Tomi *>* > *>* >* I don't see this mainstream yet, but the patch is from a while ago. Do you guys know if this will make it into the kernel? Without it, I cannot the DM3730 to DSS to operate correctly. AFAIK 37xx is same as 3630 and does not work properly without the patch above as we've seen. Well, the patch is definitely wrong for 3630, as 3630 has divider range from 1 to 32, as seen from the CM_CLKSEL_DSS register. Yes something is wrong somewhere for sure.. What if it's .dss_fck_multiplier = 2 and .fck_div_max = 32? I can't find the fixed x2 multiplier from the TRM, but looking at the .dts files, 3630 DSS gets the clock from dpll4_m4x2_ck, so maybe it is there. Or maybe the clocks in the .dts files are wrong, and the multplier in dss.c is right. Yes grepping for it we have it both for legacy and dts clocks: $ git grep dpll4_m4x2_ck Documentation/devicetree/bindings/clock/ti/gate.txt:clocks = <&dpll4_m4x2_ck>; arch/arm/boot/dts/omap3430es1-clocks.dtsi: clocks = <&dpll4_m4x2_ck>; arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi: clocks = <&dpll4_m4x2_ck>; arch/arm/boot/dts/omap3xxx-clocks.dtsi: dpll4_m4x2_ck: dpll4_m4x2_ck { drivers/clk/ti/clk-3xxx-legacy.c:static struct ti_clk_gate dpll4_m4x2_ck_data = { drivers/clk/ti/clk-3xxx-legacy.c:static struct ti_clk dpll4_m4x2_ck = { drivers/clk/ti/clk-3xxx-legacy.c: .name = "dpll4_m4x2_ck", drivers/clk/ti/clk-3xxx-legacy.c: .data = &dpll4_m4x2_ck_data, drivers/clk/ti/clk-3xxx-legacy.c: .parent = "dpll4_m4x2_ck", drivers/clk/ti/clk-3xxx-legacy.c: .parent = "dpll4_m4x2_ck", drivers/clk/ti/clk-3xxx-legacy.c: CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck), drivers/clk/ti/clk-3xxx.c: DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"), And looking at the TRM, "3.5.3.3.4 DPLL Clock Summary" hints strongly that there is no x2 multiplier there, so it might be that the dts clock files are not right. Or maybe the TRM was copied from the 34xx and never updated? Tero, any ideas? TRMs are correct, 3630 does not have x2 multiplier after DPLL4. In the clock data, dpll4_m4x2 path is an x1 multiplier on omap3630, it is easier to represent this in DT than completely remove the dpll4_*x2 nodes for omap36xx. This is how it was already before the DT clocks. Here is a copy paste from clock debug data on omap36xx where you see the rate for the whole dpll4_m4 path is 96MHz: dpll4_m4_ck 019600 0 0 dpll4_m4x2_mul_ck 019600 0 0 dpll4_m4x2_ck 019600 0 0 dss1_alwon_fck_3430es2 04 9600 0 0 And same on omap34xx (not sure why the clock rate is totally different here though, but you see the x2 applied): dpll4_m4_ck 01 21600 0 0 dpll4_m4x2_mul_ck 01 43200 0 0 dpll4_m4x2_ck 01 43200 0 0 -Tero Unfortunately I have no working omap3 devices to test this =(. Should not cost you more than few tens of whatever units to get one :) Anybody have a spare 37xx device with an LCD to donate for Tomi? Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in t
Re: [RFC 0/7] ARM: OMAP2+: support for DT based pwrdm/clkdm data
On 10/06/2015 03:09 PM, Tony Lindgren wrote: * Tero Kristo [150814 05:36]: Basically the question with this set is, whether the DT node layout / compatible string arrangement looks sane or not. Some of the compatibles can be squashed together especially at clkdm data side, seeing the remaining stub data portions are rather minimal. They could also just be retained just in case we need to tweak something later Well does this play along with the genpd? Let's assume that within a few merge cycles we have proper s3220 interconnect driver for each L4 instance along the lines of simple-pm-bus ;) I guess the question is what shall we represent under genpd. This series represents/registers each clockdomain / powerdomain as a single genpd entity (see patch #6, it adds the support for registering genpds.) If the plan is to represent also each hwmod device as a genpd entity, it should work fine I think, as each device can have a single clkdm as their parent. Patch #6 is still missing support for actual control of the domains, the functions are just dummies. Hwmod should use genpd also instead of direct control of clkdms. We could also add support for voltagedomains under genpd if required. This RFC series is rather minimal in functionality still just to get some feedback of the approaches taken. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: ti: fix dual-registration of uart4_ick
On 10/05/2015 01:17 PM, Tony Lindgren wrote: * Ben Dooks [150929 06:14]: On 25/09/15 06:42, Tero Kristo wrote: On 09/23/2015 08:30 PM, Tony Lindgren wrote: * Ben Dooks [150923 07:53]: On the OMAP AM3517 platform the uart4_ick gets registered twice, causing any power managment to /dev/ttyO3 to fail when trying to wake the device up. This solves the following oops: [] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008 [] PC is at serial_omap_pm+0x48/0x15c [] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c No uart4 on 34xx/35xx, that got introduced with 36xx so: Acked-by: Tony Lindgren Signed-off-by: Ben Dooks --- drivers/clk/ti/clk-3xxx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 5e12f32..2e7ef1f 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -374,7 +374,6 @@ static struct ti_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "gpio2_ick", "gpio2_ick"), DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), DT_CLK(NULL, "uart3_ick", "uart3_ick"), -DT_CLK(NULL, "uart4_ick", "uart4_ick"), DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), NAK. This patch is actually only partially correct, it removes the uart4_ick alias for omap36xx also. It should be added back to the omap36xx clks array. Care to post a v2? Thankyou for the feedback. I'll update, but do not have a device to test. Hmm but isn't that entry already there for 36xx? So this just removes a duplicate for 36xx.. Tero, can you please check again, maybe I'm confused. uart4_ick wasn't there, we only had uart4_fck listed for omap36xx. -Tero Regars, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] clock: ti: fixes for 4.3-rc
Hi Stephen, Mike, A few TI clock driver fixes to pull against 4.3-rc. -Tero The following changes since commit 9ffecb10283508260936b96022d4ee43a7798b4c: Linux 4.3-rc3 (2015-09-27 07:50:08 -0400) are available in the git repository at: https://github.com/t-kristo/linux-pm.git for-4.3-rc/ti-clk-fixes for you to fetch changes up to 7aba4f5201d1b7b3ddb0b03883d9edf69851ddad: clk: ti: dflt: fix enable_reg validity check (2015-10-02 09:24:28 +0300) Ben Dooks (1): clk: ti: fix dual-registration of uart4_ick Peter Ujfalusi (1): clk: ti: clk-7xx: Remove hardwired ABE clock configuration Suman Anna (1): clk: ti: dflt: fix enable_reg validity check drivers/clk/ti/clk-3xxx.c |2 +- drivers/clk/ti/clk-7xx.c | 18 +- drivers/clk/ti/clkt_dflt.c |4 ++-- 3 files changed, 4 insertions(+), 20 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: ti: dflt: fix enable_reg validity check
On 09/30/2015 01:37 AM, Suman Anna wrote: The default clock enabling functions for TI clocks - omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a NULL check for the enable_reg field of the clk_hw_omap structure. This enable_reg field however is merely a combination of the index of the master IP module, and the offset from the master IP module's base address. A value of 0 is perfectly valid, and the current error checking will fail in these cases. The issue was found when trying to enable the iva2_ck clock on OMAP3 platforms. So, switch the check to use IS_ERR. This correction is similar to the logic used in commit c807dbedb5e5 ("clk: ti: fix ti_clk_get_reg_addr error handling"). Signed-off-by: Suman Anna --- Hi Tero, Patch done against 4.3-rc3. There are couple of similar checks in drivers/clk/ti/clockdomain.c, but those seem to be ok. This is a non-urgent fix, as there are currently no active users of iva2_ck in the kernel (the MMU node is disabled in DT atm). Boot tested on OMAP3 Beagle-XM, AM437x GP EVM, AM335x BeagleBone Black, OMAP4 Panda, OMAP5 uEVM and DRA7 Beagle-X15 boards. regards Suman Following is the error log from a unit test of the IVA MMU on OMAP3 using some additional patch to enable the DTS node, [ 86.626342] omap_iommu_test_init: iommu_test_init entered [ 86.632080] omap_iommu_test iommu_test: Enabling IOMMU... [ 86.647460] omap_iommu_test iommu_test: testing IOMMU 5d00.mmu [ 86.654815] omap2_dflt_clk_enable: iva2_ck missing enable_reg [ 86.680938] [ cut here ] [ 86.685821] WARNING: CPU: 0 PID: 910 at drivers/clk/clk.c:675 clk_disable+0x28/0x34() [ 86.694091] Modules linked in: iommu_dt_test(O+) [ 86.698974] CPU: 0 PID: 910 Comm: insmod Tainted: G O 4.3.0-rc3-8-g61458979cbbe #40 [ 86.708618] Hardware name: Generic OMAP36xx (Flattened Device Tree) [ 86.715240] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [ 86.723419] [] (show_stack) from [] (dump_stack+0x84/0x9c) [ 86.731048] [] (dump_stack) from [] (warn_slowpath_common+0x78/0xb4) [ 86.739593] [] (warn_slowpath_common) from [] (warn_slowpath_null+0x1c/0x24) [ 86.748870] [] (warn_slowpath_null) from [] (clk_disable+0x28/0x34) [ 86.757324] [] (clk_disable) from [] (_disable_clocks+0x18/0x68) [ 86.765502] [] (_disable_clocks) from [] (omap_hwmod_deassert_hardreset+0xc8/0x180) [ 86.775421] [] (omap_hwmod_deassert_hardreset) from [] (omap_device_deassert_hardreset+0x34/ 0x54) [ 86.786621] [] (omap_device_deassert_hardreset) from [] (omap_iommu_attach_dev+0xbc/0x1fc) [ 86.797180] [] (omap_iommu_attach_dev) from [] (__iommu_attach_device+0x1c/0x80) [ 86.806854] [] (__iommu_attach_device) from [] (omap_iommu_test_probe+0xd0/0x21c [iommu_dt_t est]) [ 86.818054] [] (omap_iommu_test_probe [iommu_dt_test]) from [] (platform_drv_probe+0x44/0xa4 ) [ 86.828857] [] (platform_drv_probe) from [] (driver_probe_device+0x1f4/0x2f0) [ 86.838195] [] (driver_probe_device) from [] (__driver_attach+0x94/0x98) [ 86.847045] [] (__driver_attach) from [] (bus_for_each_dev+0x6c/0xa0) [ 86.855651] [] (bus_for_each_dev) from [] (bus_add_driver+0x18c/0x214) [ 86.864349] [] (bus_add_driver) from [] (driver_register+0x78/0xf8) [ 86.872772] [] (driver_register) from [] (do_one_initcall+0x80/0x1dc) [ 86.881378] [] (do_one_initcall) from [] (do_init_module+0x5c/0x1d0) [ 86.889892] [] (do_init_module) from [] (load_module+0x1818/0x1f70) [ 86.898315] [] (load_module) from [] (SyS_init_module+0xdc/0x14c) [ 86.906555] [] (SyS_init_module) from [] (ret_fast_syscall+0x0/0x1c) [ 86.915039] ---[ end trace 49b229a4289ab8b2 ]--- [ 86.919891] omap_hwmod: mmu_iva: failed to hardreset [ 86.925384] omap-iommu 5d00.mmu: deassert_reset failed: -16 [ 86.931640] omap_iommu_test iommu_test: can't get omap iommu: -16 [ 86.938140] omap_iommu_test iommu_test: can't attach iommu device: -16 [ 86.945068] omap_iommu_test_init failed, ret = -16 drivers/clk/ti/clkt_dflt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Queued for 4.3-rc-fixes thanks, as I have other patches to push for that. -Tero diff --git a/drivers/clk/ti/clkt_dflt.c b/drivers/clk/ti/clkt_dflt.c index 90d7d8a21c49..1ddc288fce4e 100644 --- a/drivers/clk/ti/clkt_dflt.c +++ b/drivers/clk/ti/clkt_dflt.c @@ -222,7 +222,7 @@ int omap2_dflt_clk_enable(struct clk_hw *hw) } } - if (unlikely(!clk->enable_reg)) { + if (unlikely(IS_ERR(clk->enable_reg))) { pr_err("%s: %s missing enable_reg\n", __func__, clk_hw_get_name(hw)); ret = -EINVAL; @@ -264,7 +264,7 @@ void omap2_dflt_clk_disable(struct clk_hw *hw) u32 v; clk = to_clk_hw_omap(hw); - if (!clk->enable_reg) { + if (IS_ERR(clk->enable_reg)) { /* * 'independent' here refers to a clock which is not * controlled by its parent. --
Re: [PATCH v2] clk: ti: fix dual-registration of uart4_ick
On 10/02/2015 03:15 AM, Stephen Boyd wrote: On 09/29, Ben Dooks wrote: On the OMAP AM3517 platform the uart4_ick gets registered twice, causing any power managment to /dev/ttyO3 to fail when trying to wake the device up. This solves the following oops: [] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008 [] PC is at serial_omap_pm+0x48/0x15c [] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c Cc: sta...@vger.kernel.org Cc: mturque...@baylibre.com Cc: sb...@codeaurora.org Cc: linux-...@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: t-kri...@ti.com Cc: linux-ker...@lists.codethink.co.uk Signed-off-by: Ben Dooks Which patch broke this? Adding a Fixes: line will help us figure out where to backport this. The issue has been around since the legacy clock data code already, I am not quite sure which initially broke it though. As such, we can use the initial clock conversion commit as a fixes by for this: commit aafd900cab87d339dc3004c241eebc854005124b Author: Tero Kristo Date: Fri Aug 2 14:04:19 2013 +0300 CLK: TI: add omap3 clock init file I'll add a fixes tag to this and queue it for 4.3-rc-fixes. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/11 RESEND] ARM: OMAP: DRA7: hwmod: Add data for McASP3
On 09/30/2015 01:06 PM, Peter Ujfalusi wrote: Paul, On 09/27/2015 10:02 AM, Paul Walmsley wrote: /* + * 'mcasp' class + * + */ +static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = { + .sysc_offs = 0x0004, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields= &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { + .name = "mcasp", + .sysc = &dra7xx_mcasp_sysc, +}; + +/* mcasp3 */ +static struct omap_hwmod dra7xx_mcasp3_hwmod = { + .name = "mcasp3", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp3_ahclkx_mux", I'd expect this clock to be something derived from mcasp3_aux_gfclk, according to Table 24-408 "Clocks and Resets" of SPRUHZ6. Could you please doublecheck this? I can not explain this. If I change the main_clk to "mcasp3_aux_gfclk_mux" then I can not access to McASP3 register at all. I don't see anything popping out in the clock data, nor in other places. + .flags = HWMOD_SWSUP_SIDLE, Not sure why this has been added, I can not find any pointers regarding to this and everything is working w/o this flag. Will remove it in v2. Is this needed? If it is, please add a brief comment describing the issue or bug that it's working around. + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'mmc' class * */ @@ -2566,6 +2598,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp3_hwmod, So this is the low-speed control/register access port, where the MPU writes to the McASP3 config registers... + .clk= "l3_iclk_div", ... and thus this interface clock doesn't look right for this port, since it's most likely generated from the L4PER2, where this port is connected. So it should probably be "l4_iclk_div". There is no "l4_iclk_div" for dra7xx. Looking around the file all other script generated data uses "l3_iclk_div" for IPs under dra7xx_l4_per2_hwmod. Tero: do you know the reason for this? This comes from the autogen generated data. Looking at the hwdb data for dra7, it seems l3 clock is defined as the OCP input clock for most of the modules. Looking at TRM, we also have L3 ICK defined as the interface clock for GPIO modules for example, and also mcasp modules. I think this is just a documentation issue and we are missing a divide by 2 from all interface clocks, the interface clocks are coming from l4 interconnects and the interconnect chapter still clearly states that the l4 clock is l3 clock / 2. -Tero + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; There's another struct omap_hwmod_ocp_if record missing: the high-speed bus-master port that the McASP3 uses to DMA audio data. This port should most likely be clocked with "l3_iclk_div" per Table 24-408 "Clocks and Resets". This port is also where the registers described in Table 24-555 "MCASP_DAT Register Summary 3" L3_MAIN column are exposed. You've got that address map range blocked out in your DT data reg property, and associated with this device, right? 0x4600? Yes, the McASP3-dat port is not used ATM. This is over the L3 interconnect and due to a feature we can not use it with sDMA (constant addressing is not supported through L3 interconnect for DMAs). We could use eDMA, but there are complications regarding to that. At the moment we are using the sDMA through the L4 interconnect address space. + static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = { { .pa_start = 0x48078000, @@ -3338,6 +3378,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_wkup__dcan1, &dra7xx_l4_per2__dcan2, &dra7xx_l4_per2__cpgmac0, + &dra7xx_l4_per2__mcasp3, &dra7xx_gmac__mdio, &dra7xx_l4_cfg__dma_system, &dra7xx_l3_main_1__dss, -- 2.5.0 - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/17] ARM: dts: am4372: add reset data
On 09/25/2015 03:57 PM, Lokesh Vutla wrote: Hi Tero, On Thursday 24 September 2015 07:56 PM, Tero Kristo wrote: Add reset data for pruss, gfx, wkup-m3 and system reset. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am4372.dtsi | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 0447c04a..fcc8d31 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -116,12 +116,15 @@ reg-names = "umem", "dmem"; ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; + reset-names = "wkup_m3"; + resets = <&prcm 0x2000 0x10 3 0x14 5>; }; prcm: prcm@1f { compatible = "ti,am4-prcm"; reg = <0x1f 0x11000>; interrupts = ; + #reset-cells = <5>; prcm_clocks: clocks { #address-cells = <1>; @@ -130,6 +133,12 @@ prcm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + reset-cells = <&prcm 0x4000 0 0 4 0>; This should be resets instead of reset-cells. With this change, reboot is functional on AM437x GP evm. Oops, nasty typo there. Thanks for catching. -Tero Thanks and regards, Lokesh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: ti: clk-7xx: Remove hardwired ABE clock configuration
On 09/25/2015 09:59 AM, Peter Ujfalusi wrote: Tero, On 09/16/2015 09:42 AM, Tero Kristo wrote: On 09/14/2015 11:52 AM, Peter Ujfalusi wrote: Hi Tero, On 08/24/2015 10:35 AM, Peter Ujfalusi wrote: The ABE related clocks should be configured via DT and not have it wired inside of the kernel. can you take a look at this patch? It will not cause any regression since we do not have audio support mainline and the pending series does not need this part anymore. This patch looks okay to me. So, you are saying this doesn't depend on anything? Isn't this causing any boot-time issues with the ABE DPLL left dangling with boot setup, potentially blocking PM? I am just wondering if we should group this patch with the rest of the audio support patches for dra7. Without this patch the ABE DPLL will have frequency which is not going to be correct to be used with the ATL. The ATL is disabled by default and only enabled when we use the audio. Which is not the case w/o the other series. Ok, queuing for 4.3-rc fixes. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: ti: fix dual-registration of uart4_ick
On 09/23/2015 08:30 PM, Tony Lindgren wrote: * Ben Dooks [150923 07:53]: On the OMAP AM3517 platform the uart4_ick gets registered twice, causing any power managment to /dev/ttyO3 to fail when trying to wake the device up. This solves the following oops: [] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008 [] PC is at serial_omap_pm+0x48/0x15c [] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c No uart4 on 34xx/35xx, that got introduced with 36xx so: Acked-by: Tony Lindgren Signed-off-by: Ben Dooks --- drivers/clk/ti/clk-3xxx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 5e12f32..2e7ef1f 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -374,7 +374,6 @@ static struct ti_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "gpio2_ick", "gpio2_ick"), DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), DT_CLK(NULL, "uart3_ick", "uart3_ick"), - DT_CLK(NULL, "uart4_ick", "uart4_ick"), DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), NAK. This patch is actually only partially correct, it removes the uart4_ick alias for omap36xx also. It should be added back to the omap36xx clks array. Care to post a v2? -Tero -- 2.5.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 03/17] ARM: dts: omap3: add reset data
Copy over the reset data from hwmod database to DT. After this is taken into use, the data in hwmod database can be removed. A new node has been also added for sad2d to support sad2d resets. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap3.dtsi | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 69a40cf..5be9aaa 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -64,11 +64,23 @@ iva: iva { compatible = "ti,iva2.2"; ti,hwmods = "iva"; + reset-names = "logic", "seq0", "seq1"; + resets = <&prm 0x 0 0 0 8>, +<&prm 0x 0 1 0 9>, +<&prm 0x 0 2 0 10>; dsp { compatible = "ti,omap3-c64"; }; }; + + sad2d: sad2d { + compatible = "ti,sad2d"; + ti,hwmods = "sad2d"; + reset-names = "rst_modem_sw", "rst_modem_pwron_sw"; + resets = <&prm 0x0a00 0 0 0 8>, +<&prm 0x0a00 0 1 0 9>; + }; }; /* @@ -154,6 +166,7 @@ compatible = "ti,omap3-prm"; reg = <0x48306000 0x4000>; interrupts = <11>; + #reset-cells = <5>; prm_clocks: clocks { #address-cells = <1>; @@ -162,6 +175,12 @@ prm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + resets = <&prm 0x1200 0 2 0 0>; + }; }; cm: cm@48004000 { @@ -471,6 +490,8 @@ interrupts = <28>; ti,hwmods = "mmu_iva"; status = "disabled"; + reset-names = "mmu"; + resets = <&prm 0x 0 1 0 9>; }; wdt2: wdt@48314000 { -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 13/17] ARM: OMAP5: hwmod_data: remove reset data
This is provided via DT, and no longer needed in the hwmod database. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 14 -- 1 file changed, 14 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 7c3fac0..9e33ac8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -1378,21 +1378,14 @@ static struct omap_hwmod_class omap54xx_mmu_hwmod_class = { .sysc = &omap54xx_mmu_sysc, }; -static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; - static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { .name = "mmu_dsp", .class = &omap54xx_mmu_hwmod_class, .clkdm_name = "dsp_clkdm", - .rst_lines = omap54xx_mmu_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets), .main_clk = "dpll_iva_h11x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, .modulemode = MODULEMODE_HWCTRL, }, @@ -1400,21 +1393,14 @@ static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { }; /* mmu ipu */ -static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = { - { .name = "mmu_cache", .rst_shift = 2 }, -}; - static struct omap_hwmod omap54xx_mmu_ipu_hwmod = { .name = "mmu_ipu", .class = &omap54xx_mmu_hwmod_class, .clkdm_name = "ipu_clkdm", - .rst_lines = omap54xx_mmu_ipu_resets, - .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets), .main_clk = "dpll_core_h22x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, .modulemode = MODULEMODE_HWCTRL, }, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 17/17] ARM: OMAP2+: PRM: remove redundant system reset code
This is now handled via the reset controller and the provided information from DT, so the legacy support code is no longer needed. OMAP3 version shall be removed once OMAP3 is also DT only. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/prm2xxx.c | 15 --- arch/arm/mach-omap2/prm33xx.c | 18 -- arch/arm/mach-omap2/prm44xx.c |1 - arch/arm/mach-omap2/prminst44xx.c | 20 4 files changed, 54 deletions(-) diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c index 752018ce..70f711b 100644 --- a/arch/arm/mach-omap2/prm2xxx.c +++ b/arch/arm/mach-omap2/prm2xxx.c @@ -101,20 +101,6 @@ static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst) } /** - * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC - * - * Set the DPLL reset bit, which should reboot the SoC. This is the - * recommended way to restart the SoC. No return value. - */ -static void omap2xxx_prm_dpll_reset(void) -{ - omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD, - OMAP2_RM_RSTCTRL); - /* OCP barrier */ - omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); -} - -/** * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module * @module: PRM module to clear wakeups from * @regs: register offset to clear @@ -216,7 +202,6 @@ static struct prm_ll_data omap2xxx_prm_ll_data = { .assert_hardreset = &omap2_prm_assert_hardreset, .deassert_hardreset = &omap2_prm_deassert_hardreset, .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted, - .reset_system = &omap2xxx_prm_dpll_reset, .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs, }; diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index dcb5001..12b15a2 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -336,23 +336,6 @@ static int am33xx_check_vcvp(void) return 0; } -/** - * am33xx_prm_global_warm_sw_reset - reboot the device via warm reset - * - * Immediately reboots the device through warm reset. - */ -static void am33xx_prm_global_warm_sw_reset(void) -{ - am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK, - AM33XX_RST_GLOBAL_WARM_SW_MASK, - AM33XX_PRM_DEVICE_MOD, - AM33XX_PRM_RSTCTRL_OFFSET); - - /* OCP barrier */ - (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD, - AM33XX_PRM_RSTCTRL_OFFSET); -} - struct pwrdm_ops am33xx_pwrdm_operations = { .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, @@ -375,7 +358,6 @@ static struct prm_ll_data am33xx_prm_ll_data = { .assert_hardreset = am33xx_prm_assert_hardreset, .deassert_hardreset = am33xx_prm_deassert_hardreset, .is_hardreset_asserted = am33xx_prm_is_hardreset_asserted, - .reset_system = am33xx_prm_global_warm_sw_reset, }; int __init am33xx_prm_init(const struct omap_prcm_init_data *data) diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 3076800..76d7e30 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -702,7 +702,6 @@ static struct prm_ll_data omap44xx_prm_ll_data = { .assert_hardreset = omap4_prminst_assert_hardreset, .deassert_hardreset = omap4_prminst_deassert_hardreset, .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, - .reset_system = omap4_prminst_global_warm_sw_reset, .vp_check_txdone= omap4_prm_vp_check_txdone, .vp_clear_txdone= omap4_prm_vp_clear_txdone, }; diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index d0b15db..ffed63f 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -174,23 +174,3 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; } - - -void omap4_prminst_global_warm_sw_reset(void) -{ - u32 v; - s32 inst = omap4_prmst_get_prm_dev_inst(); - - if (inst == PRM_INSTANCE_UNKNOWN) - return; - - v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst, - OMAP4_PRM_RSTCTRL_OFFSET); - v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; - omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, -inst, OMAP4_PRM_RSTCTRL_OFFSET); - - /* OCP barrier */ - v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, - inst, OMAP4_PRM_RSTCTRL_OFFSET); -} -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe lin
[PATCH 11/17] ARM: OMAP2+: use system reset info from device tree data
System reset mapping used by reboot is now provided through DT data and a reset controller. Use this instead of the hardcoded PRM API. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile |6 -- arch/arm/mach-omap2/am33xx-restart.c | 27 --- arch/arm/mach-omap2/board-generic.c | 16 arch/arm/mach-omap2/common.c | 29 + arch/arm/mach-omap2/common.h |2 ++ arch/arm/mach-omap2/omap2-restart.c |2 +- arch/arm/mach-omap2/omap3-restart.c |2 +- arch/arm/mach-omap2/omap4-restart.c | 27 --- arch/arm/mach-omap2/ti81xx-restart.c | 34 -- 9 files changed, 41 insertions(+), 104 deletions(-) delete mode 100644 arch/arm/mach-omap2/am33xx-restart.c delete mode 100644 arch/arm/mach-omap2/omap4-restart.c delete mode 100644 arch/arm/mach-omap2/ti81xx-restart.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 9358696..491dc6e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -57,13 +57,7 @@ AFLAGS_sram34xx.o:=-Wa,-march=armv7-a # Restart code (OMAP4/5 currently in omap4-common.c) obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o -obj-$(CONFIG_SOC_TI81XX) += ti81xx-restart.o -obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o -obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o -obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o -obj-$(CONFIG_SOC_OMAP5)+= omap4-restart.o -obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o # Pin multiplexing obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c deleted file mode 100644 index 5bace6a..000 --- a/arch/arm/mach-omap2/am33xx-restart.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * am33xx-restart.c - Code common to all AM33xx machines. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - -#include "common.h" -#include "prm.h" - -/** - * am3xx_restart - trigger a software restart of the SoC - * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c - * @cmd: passed from the userspace program rebooting the system (if provided) - * - * Resets the SoC. For @cmd, see the 'reboot' syscall in - * kernel/sys.c. No return value. - */ -void am33xx_restart(enum reboot_mode mode, const char *cmd) -{ - /* TODO: Handle mode and cmd if necessary */ - - omap_prm_reset_system(); -} diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 24c9afc..6a82a9c 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -177,7 +177,7 @@ DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)") .init_late = ti81xx_init_late, .init_time = omap3_gptimer_timer_init, .dt_compat = ti814x_boards_compat, - .restart= ti81xx_restart, + .restart= omap_restart, MACHINE_END static const char *const ti816x_boards_compat[] __initconst = { @@ -194,7 +194,7 @@ DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)") .init_late = ti81xx_init_late, .init_time = omap3_gptimer_timer_init, .dt_compat = ti816x_boards_compat, - .restart= ti81xx_restart, + .restart= omap_restart, MACHINE_END #endif @@ -212,7 +212,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") .init_late = am33xx_init_late, .init_time = omap3_gptimer_timer_init, .dt_compat = am33xx_boards_compat, - .restart= am33xx_restart, + .restart= omap_restart, MACHINE_END #endif @@ -237,7 +237,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") .init_late = omap4430_init_late, .init_time = omap4_local_timer_init, .dt_compat = omap4_boards_compat, - .restart= omap44xx_restart, + .restart= omap_restart, MACHINE_END #endif @@ -259,7 +259,7 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") .init_late = omap5_init_late, .init_time = omap5_realtime_timer_init, .dt_compat = omap5_boards_compat, - .restart= omap44xx_restart, + .restart= omap_restart, MACHINE_END #endif @@ -281,7 +281,7 @@ DT_MACHINE_START(AM43_DT, "Generic
[PATCH 12/17] ARM: OMAP4: hwmod_data: remove reset data
This is provided via DT and no longer needed under the hwmod database. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 48 +++- 1 file changed, 5 insertions(+), 43 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 43eebf2..0447ba9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -535,21 +535,14 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { }; /* dsp */ -static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { - { .name = "dsp", .rst_shift = 0 }, -}; - static struct omap_hwmod omap44xx_dsp_hwmod = { .name = "dsp", .class = &omap44xx_dsp_hwmod_class, .clkdm_name = "tesla_clkdm", - .rst_lines = omap44xx_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), .main_clk = "dpll_iva_m4x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, .modulemode = MODULEMODE_HWCTRL, }, @@ -1414,22 +1407,14 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { }; /* ipu */ -static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { - { .name = "cpu0", .rst_shift = 0 }, - { .name = "cpu1", .rst_shift = 1 }, -}; - static struct omap_hwmod omap44xx_ipu_hwmod = { .name = "ipu", .class = &omap44xx_ipu_hwmod_class, .clkdm_name = "ducati_clkdm", - .rst_lines = omap44xx_ipu_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), .main_clk = "ducati_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, .modulemode = MODULEMODE_HWCTRL, }, @@ -1497,23 +1482,14 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = { }; /* iva */ -static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { - { .name = "seq0", .rst_shift = 0 }, - { .name = "seq1", .rst_shift = 1 }, - { .name = "logic", .rst_shift = 2 }, -}; - static struct omap_hwmod omap44xx_iva_hwmod = { .name = "iva", .class = &omap44xx_iva_hwmod_class, .clkdm_name = "ivahd_clkdm", - .rst_lines = omap44xx_iva_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), .main_clk = "dpll_iva_m5x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, .modulemode = MODULEMODE_HWCTRL, }, @@ -2093,9 +2069,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { }; static struct omap_hwmod omap44xx_mmu_ipu_hwmod; -static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { - { .name = "mmu_cache", .rst_shift = 2 }, -}; static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { { @@ -2119,13 +2092,10 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { .name = "mmu_ipu", .class = &omap44xx_mmu_hwmod_class, .clkdm_name = "ducati_clkdm", - .rst_lines = omap44xx_mmu_ipu_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), .main_clk = "ducati_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, .modulemode = MODULEMODE_HWCTRL, }, @@ -2140,9 +2110,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { }; static struct omap_hwmod omap44xx_mmu_dsp_hwmod; -static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { { @@ -2166,13 +2133,10 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { .name = "mmu_dsp",
[PATCH 15/17] ARM: OMAP24xx: hwmod: remove reset data from hwmod database
These are now parsed from DT, so not needed under the hwmod database anymore. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 13 - arch/arm/mach-omap2/omap_hwmod_2430_data.c |7 --- 2 files changed, 20 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 65b1647..5db681d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -49,16 +49,10 @@ static struct omap_hwmod_class iva1_hwmod_class = { .name = "iva1", }; -static struct omap_hwmod_rst_info omap2420_iva_resets[] = { - { .name = "iva", .rst_shift = 8 }, -}; - static struct omap_hwmod omap2420_iva_hwmod = { .name = "iva", .class = &iva1_hwmod_class, .clkdm_name = "iva1_clkdm", - .rst_lines = omap2420_iva_resets, - .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), .main_clk = "iva1_ifck", }; @@ -67,17 +61,10 @@ static struct omap_hwmod_class dsp_hwmod_class = { .name = "dsp", }; -static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { - { .name = "logic", .rst_shift = 0 }, - { .name = "mmu", .rst_shift = 1 }, -}; - static struct omap_hwmod omap2420_dsp_hwmod = { .name = "dsp", .class = &dsp_hwmod_class, .clkdm_name = "dsp_clkdm", - .rst_lines = omap2420_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), .main_clk = "dsp_fck", }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 79127b3..cc0cfaf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -44,17 +44,10 @@ */ /* IVA2 (IVA2) */ -static struct omap_hwmod_rst_info omap2430_iva_resets[] = { - { .name = "logic", .rst_shift = 0 }, - { .name = "mmu", .rst_shift = 1 }, -}; - static struct omap_hwmod omap2430_iva_hwmod = { .name = "iva", .class = &iva_hwmod_class, .clkdm_name = "dsp_clkdm", - .rst_lines = omap2430_iva_resets, - .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), .main_clk = "dsp_fck", }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/17] ARM: dts: am4372: add reset data
Add reset data for pruss, gfx, wkup-m3 and system reset. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am4372.dtsi | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 0447c04a..fcc8d31 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -116,12 +116,15 @@ reg-names = "umem", "dmem"; ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; + reset-names = "wkup_m3"; + resets = <&prcm 0x2000 0x10 3 0x14 5>; }; prcm: prcm@1f { compatible = "ti,am4-prcm"; reg = <0x1f 0x11000>; interrupts = ; + #reset-cells = <5>; prcm_clocks: clocks { #address-cells = <1>; @@ -130,6 +133,12 @@ prcm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + reset-cells = <&prcm 0x4000 0 0 4 0>; + }; }; scm: scm@21 { @@ -1053,6 +1062,21 @@ ti,hwmods = "vpfe1"; status = "disabled"; }; + + gfx: gfx@5600 { + compatible = "ti,am4376-sgx530", "img,sgx530"; + ti,hwmods = "gfx"; + status = "disabled"; + reset-names = "gfx"; + resets = <&prcm 0x400 0x10 0 0x14 0>; + }; + + pruss: pruss@5440 { + compatible = "ti,am4372-pruss"; + ti,hwmods = "pruss"; + reset-names = "pruss"; + resets = <&prcm 0x800 0x10 1 0x14 0>; + }; }; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/17] ARM: dts: omap5: add reset data
Copy over the reset data from hwmod database to DT. After this is taken into use, the data in hwmod database can be removed. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5.dtsi | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 4205a8a..631a8ae 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -242,6 +242,7 @@ compatible = "ti,omap5-prm"; reg = <0x6000 0x3000>; interrupts = ; + #reset-cells = <5>; prm_clocks: clocks { #address-cells = <1>; @@ -250,6 +251,12 @@ prm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + resets = <&prm 0x1c00 0 0 4 0>; + }; }; scrm: scrm@a000 { @@ -614,6 +621,8 @@ interrupts = ; ti,hwmods = "mmu_dsp"; #iommu-cells = <0>; + reset-names = "mmu_cache"; + resets = <&prm 0x400 0x10 1 0x14 1>; }; mmu_ipu: mmu@55082000 { @@ -623,6 +632,8 @@ ti,hwmods = "mmu_ipu"; #iommu-cells = <0>; ti,iommu-bus-err-back; + reset-names = "mmu_cache"; + resets = <&prm 0x700 0x210 2 0x214 2>; }; keypad: keypad@4ae1c000 { -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 06/17] ARM: dts: dra7: add reset data
Copy over the reset data from kernel to DT. Currently, only system reset has been defined, but rest can be added later once needed. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7.dtsi |7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5d65db9..e299b07 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -199,6 +199,7 @@ compatible = "ti,dra7-prm"; reg = <0x6000 0x3000>; interrupts = ; + #reset-cells = <5>; prm_clocks: clocks { #address-cells = <1>; @@ -207,6 +208,12 @@ prm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + resets = <&prm 0x1d00 0 0 4 0>; + }; }; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 00/17] ARM: OMAP2+: reset controller support
Hi, This series adds reset controller support on top of the existing PRM/PRCM code. All the currently defined reset sources in hwmod databases are moved over to DT, and all except OMAP3 hwmod resets are also removed. OMAP3 hwmod reset data can be removed once OMAP3 is DT only. Reboot support is also converted to use the new reset controller nodes, and a new DT node is introduced for this purpose; system_reset. I guess the main question regarding this series is whether the DT changes are okay, I was forced to create a few top level ocp nodes for IVA/DSP etc. which were missing, and a couple of peripheral nodes for AMx3xx to host the reset data. DSP/IVA nodes should be created for OMAP5+ also to support the resets for these, but currently these are completely missing so I did not bother adding them. One motivation for this series is to get rid of the hwmod database reset info, which eventually allows getting rid of the hwmod data completely (read: moved over to DT.) Boot tested on omap3-beagle, omap4-panda-es, omap5-uevm, dra7-evm, beagle-x15, sdp2430, sdp3430, beaglebone-white, beaglebone-black, am43xx-gp-evm. Reboot tested on omap3-beagle, omap4-panda-es, omap5-uevm, beagle-x15. Reboot on amx3xx does not seem functional in base 4.3-rc2 so wasn't able to test this. Testing branch pushed at: tree: https://github.com/t-kristo/linux-pm.git branch: 4.3-rc2-prcm-reset-fwk Tero Kristo (17): ARM: OMAP2+: PRM: add support for reset controller ARM: OMAP2+: hwmod: parse also soc hierarchy for hwmod compatible nodes ARM: dts: omap3: add reset data ARM: dts: omap4: add reset data ARM: dts: omap5: add reset data ARM: dts: dra7: add reset data ARM: dts: am4372: add reset data ARM: dts: am33xx: add reset data ARM: dts: OMAP24xx: add reset data ARM: OMAP2+: hwmod: parse reset information from DT ARM: OMAP2+: use system reset info from device tree data ARM: OMAP4: hwmod_data: remove reset data ARM: OMAP5: hwmod_data: remove reset data ARM: OMAP2: hwmod: AMx3xx: remove redundant reset info ARM: OMAP24xx: hwmod: remove reset data from hwmod database ARM: OMAP2+: hwmod: remove obsolete support for some hardreset logic ARM: OMAP2+: PRM: remove redundant system reset code arch/arm/boot/dts/am33xx.dtsi | 24 +++ arch/arm/boot/dts/am4372.dtsi | 24 +++ arch/arm/boot/dts/dra7.dtsi|7 + arch/arm/boot/dts/omap2420.dtsi| 24 +++ arch/arm/boot/dts/omap2430.dtsi| 17 ++ arch/arm/boot/dts/omap3.dtsi | 21 ++ arch/arm/boot/dts/omap4.dtsi | 27 +++ arch/arm/boot/dts/omap5.dtsi | 11 ++ arch/arm/mach-omap2/Kconfig|1 + arch/arm/mach-omap2/Makefile |6 - arch/arm/mach-omap2/am33xx-restart.c | 27 --- arch/arm/mach-omap2/board-generic.c| 16 +- arch/arm/mach-omap2/common.c | 29 +++ arch/arm/mach-omap2/common.h |2 + arch/arm/mach-omap2/omap2-restart.c|2 +- arch/arm/mach-omap2/omap3-restart.c|2 +- arch/arm/mach-omap2/omap4-restart.c| 27 --- arch/arm/mach-omap2/omap_hwmod.c | 203 ++-- arch/arm/mach-omap2/omap_hwmod.h | 12 +- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 13 -- arch/arm/mach-omap2/omap_hwmod_2430_data.c |7 - .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 30 --- arch/arm/mach-omap2/omap_hwmod_33xx_data.c |8 - arch/arm/mach-omap2/omap_hwmod_43xx_data.c |8 - arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 48 + arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 14 -- arch/arm/mach-omap2/prm2xxx.c | 15 -- arch/arm/mach-omap2/prm33xx.c | 18 -- arch/arm/mach-omap2/prm44xx.c |1 - arch/arm/mach-omap2/prm_common.c | 167 arch/arm/mach-omap2/prminst44xx.c | 20 -- arch/arm/mach-omap2/ti81xx-restart.c | 34 32 files changed, 476 insertions(+), 389 deletions(-) delete mode 100644 arch/arm/mach-omap2/am33xx-restart.c delete mode 100644 arch/arm/mach-omap2/omap4-restart.c delete mode 100644 arch/arm/mach-omap2/ti81xx-restart.c bloat-o-meter: add/remove: 13/24 grow/shrink: 20/579 up/down: 1732/-3020 (-1288) function old new delta ti_reset_xlate - 456+456 _init 10121380+368 _dt_assert_hardreset - 128+128 omap2_prm_reset_controller_register- 108+108 __omap_init_restart- 100+100 __f
[PATCH 16/17] ARM: OMAP2+: hwmod: remove obsolete support for some hardreset logic
OMAP4+ prcm struct no longer requires the support for the rstctrl / rstst offsets, as the data is parsed from DT for all platforms. Remove also the obsolete hardreset support functions from the hwmod code. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod.c | 108 -- arch/arm/mach-omap2/omap_hwmod.h |4 -- 2 files changed, 112 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 974260a..9d7a034 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3069,106 +3069,6 @@ static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, oh->prcm.omap2.module_offs, 0); } -/** - * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args - * @oh: struct omap_hwmod * to assert hardreset - * @ohri: hardreset line data - * - * Call omap4_prminst_assert_hardreset() with parameters extracted - * from the hwmod @oh and the hardreset line data @ohri. Only - * intended for use as an soc_ops function pointer. Passes along the - * return value from omap4_prminst_assert_hardreset(). XXX This - * function is scheduled for removal when the PRM code is moved into - * drivers/. - */ -static int _omap4_assert_hardreset(struct omap_hwmod *oh, - struct omap_hwmod_rst_info *ohri) -{ - if (!oh->clkdm) - return -EINVAL; - - return omap_prm_assert_hardreset(ohri->rst_shift, -oh->clkdm->pwrdm.ptr->prcm_partition, -oh->clkdm->pwrdm.ptr->prcm_offs, -oh->prcm.omap4.rstctrl_offs); -} - -/** - * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args - * @oh: struct omap_hwmod * to deassert hardreset - * @ohri: hardreset line data - * - * Call omap4_prminst_deassert_hardreset() with parameters extracted - * from the hwmod @oh and the hardreset line data @ohri. Only - * intended for use as an soc_ops function pointer. Passes along the - * return value from omap4_prminst_deassert_hardreset(). XXX This - * function is scheduled for removal when the PRM code is moved into - * drivers/. - */ -static int _omap4_deassert_hardreset(struct omap_hwmod *oh, -struct omap_hwmod_rst_info *ohri) -{ - if (!oh->clkdm) - return -EINVAL; - - if (ohri->st_shift) - pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", - oh->name, ohri->name); - return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift, - oh->clkdm->pwrdm.ptr->prcm_partition, - oh->clkdm->pwrdm.ptr->prcm_offs, - oh->prcm.omap4.rstctrl_offs, - oh->prcm.omap4.rstctrl_offs + - OMAP4_RST_CTRL_ST_OFFSET); -} - -/** - * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args - * @oh: struct omap_hwmod * to test hardreset - * @ohri: hardreset line data - * - * Call omap4_prminst_is_hardreset_asserted() with parameters - * extracted from the hwmod @oh and the hardreset line data @ohri. - * Only intended for use as an soc_ops function pointer. Passes along - * the return value from omap4_prminst_is_hardreset_asserted(). XXX - * This function is scheduled for removal when the PRM code is moved - * into drivers/. - */ -static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, - struct omap_hwmod_rst_info *ohri) -{ - if (!oh->clkdm) - return -EINVAL; - - return omap_prm_is_hardreset_asserted(ohri->rst_shift, - oh->clkdm->pwrdm.ptr-> - prcm_partition, - oh->clkdm->pwrdm.ptr->prcm_offs, - oh->prcm.omap4.rstctrl_offs); -} - -/** - * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args - * @oh: struct omap_hwmod * to deassert hardreset - * @ohri: hardreset line data - * - * Call am33xx_prminst_deassert_hardreset() with parameters extracted - * from the hwmod @oh and the hardreset line data @ohri. Only - * intended for use as an soc_ops function pointer. Passes along the - * return value from am33xx_prminst_deassert_hardreset(). XXX This - * function is scheduled for removal when the PRM code is moved into - * drivers/. - */ -static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, -struct omap_hwmod_rst_info *ohri) -{ - return omap
[PATCH 02/17] ARM: OMAP2+: hwmod: parse also soc hierarchy for hwmod compatible nodes
Previously the code was only parsing ocp hierarchy, which misses mpu and iva/dsp nodes at least, which still contain hwmod support. Parse also the soc hierarchy to include these. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index cc8a987..f53ebc6 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2467,15 +2467,24 @@ static int __init _init(struct omap_hwmod *oh, void *data) if (of_have_populated_dt()) { struct device_node *bus; + struct device_node *soc; bus = of_find_node_by_name(NULL, "ocp"); if (!bus) return -ENODEV; r = of_dev_hwmod_lookup(bus, oh, &index, &np); - if (r) - pr_debug("omap_hwmod: %s missing dt data\n", oh->name); - else if (np && index) + if (r) { + soc = of_find_node_by_name(NULL, "soc"); + if (soc) + r = of_dev_hwmod_lookup(soc, oh, &index, &np); + + if (r) + pr_debug("omap_hwmod: %s missing dt data\n", +oh->name); + } + + if (np && index) pr_warn("omap_hwmod: %s using broken dt data from %s\n", oh->name, np->name); } -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 08/17] ARM: dts: am33xx: add reset data
Add reset data for pruss, gfx, wkup-m3, and system reset. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am33xx.dtsi | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d23e252..3974c3b 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -110,11 +110,14 @@ reg-names = "umem", "dmem"; ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; + reset-names = "wkup_m3"; + resets = <&prcm 0xd00 0 3 0xc 5>; }; prcm: prcm@20 { compatible = "ti,am3-prcm"; reg = <0x20 0x4000>; + #reset-cells = <5>; prcm_clocks: clocks { #address-cells = <1>; @@ -123,6 +126,12 @@ prcm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + resets = <&prcm 0xf00 0 0 8 1>; + }; }; scm: scm@21 { @@ -879,6 +888,21 @@ reg = <0x4831 0x2000>; interrupts = <111>; }; + + pruss: pruss@4a30 { + compatible = "ti,am3352-pruss"; + ti,hwmods = "pruss"; + reset-names = "pruss"; + resets = <&prcm 0xc00 0 1 0 1>; + }; + + gfx: gfx@5600 { + compatible = "ti,am3352-sgx530", "img,sgx530"; + ti,hwmods = "gfx"; + status = "disabled"; + reset-names = "gfx"; + resets = <&prcm 0x1100 0x4 0 0x14 0>; + }; }; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/17] ARM: dts: omap4: add reset data
Copy over the reset data from hwmod database to DT. After this is taken into use, the data in hwmod database can be removed. A new node has been also added for ipu to support ipu resets. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap4.dtsi | 27 +++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index abc4473..d14c485 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -97,11 +97,25 @@ dsp { compatible = "ti,omap3-c64"; ti,hwmods = "dsp"; + reset-names = "dsp"; + resets = <&prm 0x0400 0x10 0 0x14 0>; }; iva { compatible = "ti,ivahd"; ti,hwmods = "iva"; + reset-names = "seq0", "seq1", "logic"; + resets = <&prm 0x0f00 0x10 0 0x14 0>, +<&prm 0x0f00 0x10 1 0x14 1>, +<&prm 0x0f00 0x10 2 0x14 2>; + }; + + ipu { + compatible = "ti,omap4-ipu"; + ti,hwmods = "ipu"; + reset-names = "cpu0", "cpu1"; + resets = <&prm 0x0700 0x210 0 0x214 0>, +<&prm 0x0700 0x210 1 0x214 1>; }; }; @@ -226,6 +240,7 @@ compatible = "ti,omap4-prm"; reg = <0x6000 0x3000>; interrupts = ; + #reset-cells = <5>; prm_clocks: clocks { #address-cells = <1>; @@ -234,6 +249,14 @@ prm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system", + "cold_sw"; + resets = <&prm 0x1b00 0 0 4 0>, +<&prm 0x1b00 0 1 4 1>; + }; }; scrm: scrm@a000 { @@ -553,6 +576,8 @@ interrupts = ; ti,hwmods = "mmu_dsp"; #iommu-cells = <0>; + reset-names = "mmu_cache"; + resets = <&prm 0x400 0x10 1 0x14 1>; }; mmu_ipu: mmu@55082000 { @@ -562,6 +587,8 @@ ti,hwmods = "mmu_ipu"; #iommu-cells = <0>; ti,iommu-bus-err-back; + reset-names = "mmu_cache"; + resets = <&prm 0x700 0x210 2 0x214 2>; }; wdt2: wdt@4a314000 { -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 09/17] ARM: dts: OMAP24xx: add reset data
Add iva, dsp and system reset control as DT data.. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap2420.dtsi | 24 arch/arm/boot/dts/omap2430.dtsi | 17 + 2 files changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 5b9a376..cfb802d 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -13,6 +13,23 @@ / { compatible = "ti,omap2420", "ti,omap2"; + soc { + iva { + compatible = "ti,omap2420-iva"; + ti,hwmods = "iva"; + reset-names = "iva"; + resets = <&prcm 0x800 0 8 0 8>; + }; + + dsp { + ti,hwmods = "dsp"; + compatible = "ti,omap2420-dsp"; + reset-names = "logic", "mmu"; + resets = <&prcm 0x800 0 0 0 4>, +<&prcm 0x800 0 1 0 5>; + }; + }; + ocp { l4: l4@4800 { compatible = "ti,omap2-l4", "simple-bus"; @@ -23,6 +40,7 @@ prcm: prcm@8000 { compatible = "ti,omap2-prcm"; reg = <0x8000 0x1000>; + #reset-cells = <5>; prcm_clocks: clocks { #address-cells = <1>; @@ -31,6 +49,12 @@ prcm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + resets = <&prcm 0x400 0 2 0 0>; + }; }; scm: scm@0 { diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 2390f38..0d5f0d6 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -13,6 +13,16 @@ / { compatible = "ti,omap2430", "ti,omap2"; + soc { + iva { + compatible = "ti,iva2.1"; + ti,hwmods = "iva"; + reset-names = "logic", "mmu"; + resets = <&prcm 0x800 0 0 0 4>, +<&prcm 0x800 0 1 0 5>; + }; + }; + ocp { l4_wkup: l4_wkup@4900 { compatible = "ti,omap2-l4-wkup", "simple-bus"; @@ -23,6 +33,7 @@ prcm: prcm@6000 { compatible = "ti,omap2-prcm"; reg = <0x6000 0x1000>; + #reset-cells = <5>; prcm_clocks: clocks { #address-cells = <1>; @@ -31,6 +42,12 @@ prcm_clockdomains: clockdomains { }; + + system_reset: system_reset { + compatible = "ti,system-reset"; + reset-names = "system"; + resets = <&prcm 0x400 0 2 0 0>; + }; }; scm: scm@2000 { -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 14/17] ARM: OMAP2: hwmod: AMx3xx: remove redundant reset info
AMx3xx reset info is now parsed from DT, so the data under hwmod database can be removed. Signed-off-by: Tero Kristo --- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 30 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |8 -- arch/arm/mach-omap2/omap_hwmod_43xx_data.c |8 -- 3 files changed, 46 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 907a452b..7405e78 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -27,8 +27,6 @@ #include "common.h" #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) -#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) -#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst)) /* * 'l3' class @@ -143,10 +141,6 @@ static struct omap_hwmod_class am33xx_pruss_hwmod_class = { .name = "pruss", }; -static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { - { .name = "pruss", .rst_shift = 1 }, -}; - /* pru-icss */ /* Pseudo hwmod for reset control purpose only */ struct omap_hwmod am33xx_pruss_hwmod = { @@ -159,8 +153,6 @@ struct omap_hwmod am33xx_pruss_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .rst_lines = am33xx_pruss_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), }; /* gfx */ @@ -169,10 +161,6 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = { .name = "gfx", }; -static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { - { .name = "gfx", .rst_shift = 0, .st_shift = 0}, -}; - struct omap_hwmod am33xx_gfx_hwmod = { .name = "gfx", .class = &am33xx_gfx_hwmod_class, @@ -183,8 +171,6 @@ struct omap_hwmod am33xx_gfx_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .rst_lines = am33xx_gfx_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), }; /* @@ -1397,17 +1383,9 @@ static void omap_hwmod_am33xx_clkctrl(void) CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET); } -static void omap_hwmod_am33xx_rst(void) -{ - RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET); - RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET); - RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET); -} - void omap_hwmod_am33xx_reg(void) { omap_hwmod_am33xx_clkctrl(); - omap_hwmod_am33xx_rst(); } static void omap_hwmod_am43xx_clkctrl(void) @@ -1470,15 +1448,7 @@ static void omap_hwmod_am43xx_clkctrl(void) CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET); } -static void omap_hwmod_am43xx_rst(void) -{ - RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET); - RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET); - RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET); -} - void omap_hwmod_am43xx_reg(void) { omap_hwmod_am43xx_clkctrl(); - omap_hwmod_am43xx_rst(); } diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index cc0791d..e4fc8b3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -64,10 +64,6 @@ static struct omap_hwmod am33xx_l4_hs_hwmod = { }, }; -static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { - { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, -}; - /* wkup_m3 */ static struct omap_hwmod am33xx_wkup_m3_hwmod = { .name = "wkup_m3", @@ -79,13 +75,9 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = { .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, - .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, - .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, - .rst_lines = am33xx_wkup_m3_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index e97a894..d486c42 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -52,10 +52,6 @@ static struct omap_hwmod am43xx_l4_hs_hwmod = { }, }; -static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { - { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, -}; - static struct omap_hwmod am43xx_wkup_m3_hwmod = { .name = "wkup_m3", .class
[PATCH 10/17] ARM: OMAP2+: hwmod: parse reset information from DT
DT can now be used to provide reset information, so parse this to avoid the need to have reset info under hwmod data. This patch disables the support for existing reset data under hwmod data, so shall be applied only after the DT reset conversion. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod.c | 104 +- arch/arm/mach-omap2/omap_hwmod.h |8 +-- 2 files changed, 107 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index f53ebc6..974260a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -142,6 +142,7 @@ #include #include #include +#include #include @@ -1611,9 +1612,10 @@ static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, if (!strcmp(rst_line, name)) { ohri->rst_shift = oh->rst_lines[i].rst_shift; ohri->st_shift = oh->rst_lines[i].st_shift; - pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", + ohri->rc = oh->rst_lines[i].rc; + pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d rc %x\n", oh->name, __func__, rst_line, ohri->rst_shift, -ohri->st_shift); +ohri->st_shift, (u32)ohri->rc); return 0; } @@ -2445,6 +2447,58 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, } /** + * _init_resets - initialize internal reset data for hwmod @oh + * @oh: struct omap_hwmod * + * @np: device node pointer for this hwmod + * + * Look up the reset info for this hwmod from device tree. + */ +static int __init _init_resets(struct omap_hwmod *oh, struct device_node *np) +{ + int num; + int i; + int ret; + const char *reset_name; + struct reset_control *rc; + + num = of_property_count_strings(np, "reset-names"); + if (num < 1) + return 0; + + oh->rst_lines = kcalloc(num, sizeof(struct omap_hwmod_rst_info), + GFP_KERNEL); + + for (i = 0; i < num; i++) { + ret = of_property_read_string_index(np, "reset-names", i, + &reset_name); + if (ret) + goto cleanup; + + rc = of_reset_control_get(np, reset_name); + if (IS_ERR(rc)) { + ret = PTR_ERR(rc); + goto cleanup; + } + + oh->rst_lines[i].name = kstrdup(reset_name, GFP_KERNEL); + oh->rst_lines[i].rc = rc; + } + + oh->rst_lines_cnt = num; + + return ret; + +cleanup: + for (i = 0; i < num; i++) { + if (oh->rst_lines[i].rc) + reset_control_put(oh->rst_lines[i].rc); + } + kfree(oh->rst_lines); + oh->rst_lines = NULL; + return ret; +} + +/** * _init - initialize internal data for the hwmod @oh * @oh: struct omap_hwmod * * @n: (unused) @@ -2507,6 +2561,13 @@ static int __init _init(struct omap_hwmod *oh, void *data) oh->flags |= HWMOD_INIT_NO_RESET; if (of_find_property(np, "ti,no-idle-on-init", NULL)) oh->flags |= HWMOD_INIT_NO_IDLE; + + r = _init_resets(oh, np); + if (r < 0) { + WARN(1, "omap_hwmod: %s: couldn't init reset\n", +oh->name); + return -EINVAL; + } } oh->_state = _HWMOD_STATE_INITIALIZED; @@ -3108,6 +3169,39 @@ static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, oh->prcm.omap4.rstst_offs); } +static int _dt_assert_hardreset(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) +{ + if (!ohri->rc) { + pr_err("%s: %s: missing rc\n", __func__, oh->name); + WARN_ONCE(1, "missing rc\n"); + return 0; + } + + return reset_control_assert(ohri->rc); +} + +static int _dt_deassert_hardreset(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) +{ + if (!ohri->rc) { + pr_err("%s: %s: missing rc\n", __func__, oh->name); + return 0; + } + + return reset_control_deassert(ohri->rc); +} + +static int _dt_is_hardreset_asserted(struct omap_hwmod *oh, +struct omap_hwmod_rst_info *ohri) +{ + if (!ohri->rc) { + pr_err("%s: %s: missing rc\n"
[PATCH 01/17] ARM: OMAP2+: PRM: add support for reset controller
PRM driver now supports reset controller for the defined reset lines. Reset configurations are provided through device tree. Later, functionality like hwmod and system reboot will be changed to use the generic framework. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Kconfig |1 + arch/arm/mach-omap2/prm_common.c | 167 ++ 2 files changed, 168 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 07d2e10..ac3ef43 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -92,6 +92,7 @@ config ARCH_OMAP2PLUS select SOC_BUS select TI_PRIV_EDMA select OMAP_IRQCHIP + select RESET_CONTROLLER help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 3fc2cbe..161d8ab 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include "soc.h" #include "prm2xxx_3xxx.h" @@ -51,6 +53,11 @@ #define OMAP_PRCM_MAX_NR_PENDING_REG 2 /* + * Default partition for OMAP resets, maps to PRM + */ +#define OMAP_RESET_DEFAULT_PARTITION 1 + +/* * prcm_irq_chips: an array of all of the "generic IRQ chips" in use * by the PRCM interrupt handler code. There will be one 'chip' per * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have @@ -737,6 +744,162 @@ static const struct of_device_id const omap_prcm_dt_match_table[] __initconst = { } }; +struct ti_reset_data { + s16 module; + u16 offset; + u16 st_offset; + u8 shift; + u8 st_shift; + u8 part; +}; + +struct ti_reset_ctrl { + struct reset_controller_dev rcdev; + struct ti_reset_data **resets; + int num_resets; + int max_resets; + s16 offset; +}; + +#define to_ti_reset_ctrl(_rcdev) container_of(_rcdev, struct ti_reset_ctrl, \ + rcdev) + +static struct ti_reset_data *_get_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_reset_ctrl *ctrl = to_ti_reset_ctrl(rcdev); + + return ctrl->resets[id]; +} + +static int ti_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_reset_data *reset = _get_reset(rcdev, id); + + return omap_prm_assert_hardreset(reset->shift, reset->part, +reset->module, reset->offset); +} + +static int ti_reset_deassert(struct reset_controller_dev *rcdev, +unsigned long id) +{ + struct ti_reset_data *reset = _get_reset(rcdev, id); + + return omap_prm_deassert_hardreset(reset->shift, reset->st_shift, + reset->part, reset->module, + reset->offset, reset->st_offset); +} + +static int ti_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_reset_data *reset = _get_reset(rcdev, id); + + return omap_prm_is_hardreset_asserted(reset->shift, reset->part, + reset->module, reset->offset); +} + +static struct reset_control_ops ti_reset_ops = { + .assert = ti_reset_assert, + .deassert = ti_reset_deassert, + .status = ti_reset_status, +}; + +static int ti_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct ti_reset_ctrl *ctrl = to_ti_reset_ctrl(rcdev); + s16 module; + u16 offset, st_offset; + u8 shift, st_shift; + int index = 0; + struct ti_reset_data *reset; + + if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells)) + return -EINVAL; + + module = reset_spec->args[0] - ctrl->offset; + offset = reset_spec->args[1]; + shift = reset_spec->args[2]; + st_offset = reset_spec->args[3]; + st_shift = reset_spec->args[4]; + + for (index = 0; index < ctrl->num_resets; index++) { + reset = ctrl->resets[index]; + + if (module == reset->module && offset == reset->offset && + st_offset == reset->st_offset && shift == reset->shift && + st_shift == reset->st_shift) + return index; + } + + reset = kzalloc(sizeof(*reset), GFP_KERNEL); + + reset->module = module; + reset->offset = offset; + reset->st_offset = st_offset; + reset->shift = shift; + reset->st_shift = st_shift; + reset->part = O
Re: [PATCH] clk: ti: clk-7xx: Remove hardwired ABE clock configuration
On 09/14/2015 11:52 AM, Peter Ujfalusi wrote: Hi Tero, On 08/24/2015 10:35 AM, Peter Ujfalusi wrote: The ABE related clocks should be configured via DT and not have it wired inside of the kernel. can you take a look at this patch? It will not cause any regression since we do not have audio support mainline and the pending series does not need this part anymore. This patch looks okay to me. So, you are saying this doesn't depend on anything? Isn't this causing any boot-time issues with the ABE DPLL left dangling with boot setup, potentially blocking PM? I am just wondering if we should group this patch with the rest of the audio support patches for dra7. -Tero Signed-off-by: Peter Ujfalusi --- Hi Tero, the ABE PLL configuration can, and will be done for dra7xx in DT with the assigned-clocks/rate/parent feature so no need to have this anymore. Regards, Peter drivers/clk/ti/clk-7xx.c | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 9b5b289e6334..a911d7de3377 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -18,7 +18,6 @@ #include "clock.h" -#define DRA7_DPLL_ABE_DEFFREQ 180633600 #define DRA7_DPLL_GMAC_DEFFREQ10 #define DRA7_DPLL_USB_DEFFREQ 96000 @@ -313,27 +312,12 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck; + struct clk *dpll_ck, *hdcp_ck; ti_dt_clocks_register(dra7xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); - sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); - dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); - - rc = clk_set_parent(abe_dpll_mux, sys_clkin2); - if (!rc) - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); - if (rc) - pr_err("%s: failed to configure ABE DPLL!\n", __func__); - - dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2); - if (rc) - pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); if (rc) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 1/7] ARM: dts: OMAP4+: add prcm_mpu node
PRCM has a local instance directly under the MPU domain, for controlling local MPU powerdomains and clockdomains. Add a DT node for this for omap4, omap5 and dra7. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7.dtsi |8 arch/arm/boot/dts/omap4.dtsi |8 arch/arm/boot/dts/omap5.dtsi |8 3 files changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5332b57..73ef19317 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -64,6 +64,14 @@ interrupt-parent = <&gic>; }; + prcm_mpu: prcm_mpu@48243000 { + compatible = "ti,omap4-prcm-mpu", "simple-bus"; + reg = <0x48243000 0xb00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48243000 0xb00>; + }; + wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index f884d6a..e569e28 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -66,6 +66,14 @@ cache-level = <2>; }; + prcm_mpu: prcm_mpu@48243000 { + compatible = "ti,omap4-prcm-mpu", "simple-bus"; + reg = <0x48243000 0x900>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48243000 0x900>; + }; + local-timer@48240600 { compatible = "arm,cortex-a9-twd-timer"; clocks = <&mpu_periphclk>; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index efe5f73..b0a123f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -99,6 +99,14 @@ interrupt-parent = <&gic>; }; + prcm_mpu: prcm_mpu@48243000 { + compatible = "ti,omap4-prcm-mpu", "simple-bus"; + reg = <0x48243000 0xb00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48243000 0xb00>; + }; + wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 0/7] ARM: OMAP2+: support for DT based pwrdm/clkdm data
Hi, This series provides DT based support for clock/powerdomain data. Some parts of the data is retained under the existing *_data.c files to act as templates. Also, minimal support for generic power domains is added, but without power_off / power_on support at this point (should be relatively trivial to add on top.) The pm-domains.c file has lots of debugging info present at the moment just for testing purposes, the pr_infos shall be gone from the actual code if this should go forward. Patches 1-4 contains some generic tweaks to the PRCM core handling, and should be good to go in their current form already. As a sample in this set, only omap4 clkdm/pwrdm data is converted. Conversion for the rest should be relatively easy to script (I have a script that converts OMAP5/DRA7/AM43xx already, needs some tweaking for the rest of the SoCs.) Basically the question with this set is, whether the DT node layout / compatible string arrangement looks sane or not. Some of the compatibles can be squashed together especially at clkdm data side, seeing the remaining stub data portions are rather minimal. They could also just be retained just in case we need to tweak something later I also pushed a test branch here: tree: https://github.com/t-kristo/linux-pm.git branch: 4.1-rc2-prcm-domains-dt (contains the clock changes on bottom) Overall diffstat for the set below: arch/arm/boot/dts/dra7.dtsi |8 + arch/arm/boot/dts/omap4.dtsi| 40 +++- arch/arm/boot/dts/omap44xx-clocks.dtsi | 298 +++- arch/arm/boot/dts/omap5.dtsi|8 + arch/arm/mach-omap2/Kconfig |1 + arch/arm/mach-omap2/Makefile|3 +- arch/arm/mach-omap2/clockdomain.h | 10 +- arch/arm/mach-omap2/clockdomains44xx_data.c | 327 +++ arch/arm/mach-omap2/cm_common.c | 12 + arch/arm/mach-omap2/io.c| 184 +-- arch/arm/mach-omap2/omap_hwmod.c|5 +- arch/arm/mach-omap2/pm-domains.c| 228 +++ arch/arm/mach-omap2/powerdomain.h |9 +- arch/arm/mach-omap2/powerdomains44xx_data.c | 124 +++--- arch/arm/mach-omap2/prcm-common.h |5 + arch/arm/mach-omap2/prm_common.c| 71 ++ drivers/clk/ti/clk.c|3 +- 17 files changed, 854 insertions(+), 482 deletions(-) bloat-o-meter (with the CONFIG_PM_GENERIC_DOMAINS in place pre/post): add/remove: 22/15 grow/shrink: 26/19 up/down: 10698/-2304 (8394) function old new delta omap_clkdm_match_table -4704 +4704 omap_pwrdm_match_table -3136 +3136 of_omap_clockdomain_init - 912+912 of_omap_powerdomain_init - 408+408 The new compatible strings are consuming any saved space (and plenty more.) With clkdm templates, we can save this (on OMAP4): add/remove: 0/0 grow/shrink: 1/23 up/down: 4/-874 (-870) Pwrdm templates maybe a bit less, as there are less users. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 5/7] ARM: dts: omap4: add clockdomain / powerdomain data
Clockdomain / powerdomain nodes with corresponding register addresses and PRCM hierarchy is added to the DT. This data can be parsed to create the clock/powerdomain data required by the kernel. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap4.dtsi | 32 +++- arch/arm/boot/dts/omap44xx-clocks.dtsi | 298 +++- 2 files changed, 321 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e569e28..62bfd07 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -72,6 +72,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48243000 0x900>; + + prcm_mpu_pm_domains: pm_domains { + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; }; local-timer@48240600 { @@ -141,26 +147,38 @@ cm1: cm1@4000 { compatible = "ti,omap4-cm1"; reg = <0x4000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4000 0x2000>; cm1_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; - cm1_clockdomains: clockdomains { + cm1_pm_domains: pm_domains { + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; cm2: cm2@8000 { compatible = "ti,omap4-cm2"; reg = <0x8000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8000 0x3000>; cm2_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; - cm2_clockdomains: clockdomains { + cm2_pm_domains: pm_domains { + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; @@ -233,13 +251,19 @@ compatible = "ti,omap4-prm"; reg = <0x6000 0x3000>; interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x6000 0x3000>; prm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; - prm_clockdomains: clockdomains { + prm_pm_domains: pm_domains { + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; @@ -252,7 +276,7 @@ #size-cells = <0>; }; - scrm_clockdomains: clockdomains { + scrm_pm_domains: pm_domains { }; }; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index f2c48f0..370694b 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -744,11 +744,105 @@ }; }; -&prm_clockdomains { - emu_sys_clkdm: emu_sys_clkdm { - compatible = "ti,clockdomain"; +&prm_pm_domains { + core_pwrdm: core_pwrdm@700 { + compatible = "ti,omap4-core-pwrdm"; + reg = <0x700 0x1c>; + #power-domain-cells = <0>; + }; + +
[RFC 6/7] ARM: OMAP2+: PRCM: add support for registering prcm domains from DT
Power and clock domains can now be registered from DT based layout. Some data is retained in the kernel for initialization purposes. The platforms that require DT based domain support, shall have their DT and the clock/powerdomainxyz_data.c files updated. The template clock/powerdomain data should be stripped to minimal amount and use a clkdm_setup / pwrdm_setup struct that consumes less memory. This patch is just directly using the existing data for the template purposes. The domains are also now registered via the generic power domain framework, and can be used by other generic parts of the kernel also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Kconfig |1 + arch/arm/mach-omap2/Makefile |3 +- arch/arm/mach-omap2/clockdomain.h | 10 +- arch/arm/mach-omap2/pm-domains.c | 228 + arch/arm/mach-omap2/powerdomain.h |9 +- 5 files changed, 243 insertions(+), 8 deletions(-) create mode 100644 arch/arm/mach-omap2/pm-domains.c diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 6468f15..b4a0ce1 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -24,6 +24,7 @@ config ARCH_OMAP4 select ARCH_OMAP2PLUS select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_CPU_SUSPEND if PM + select PM_GENERIC_DOMAINS if PM select ARM_ERRATA_720789 select ARM_GIC select HAVE_ARM_SCU if SMP diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d424920..1ac9fa7 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -140,7 +140,8 @@ obj-$(CONFIG_SOC_OMAP5)+= voltagedomains54xx_data.o obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common) # OMAP powerdomain framework -powerdomain-common += powerdomain.o powerdomain-common.o +powerdomain-common += powerdomain.o powerdomain-common.o \ + pm-domains.o obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 77bab5f..d316c4e 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -123,7 +123,7 @@ struct omap_hwmod; * definitions (OMAP4 only) */ struct clockdomain { - const char *name; + char *name; union { const char *name; struct powerdomain *ptr; @@ -132,9 +132,9 @@ struct clockdomain { const u8 flags; u8 _flags; const u8 dep_bit; - const u8 prcm_partition; - const u16 cm_inst; - const u16 clkdm_offs; + u8 prcm_partition; + u16 cm_inst; + u16 clkdm_offs; struct clkdm_dep *wkdep_srcs; struct clkdm_dep *sleepdep_srcs; int usecount; @@ -235,4 +235,6 @@ extern struct clkdm_dep gfx_24xx_wkdeps[]; extern struct clkdm_dep dsp_24xx_wkdeps[]; extern struct clockdomain wkup_common_clkdm; +int of_omap_clockdomain_init(const struct of_device_id *match); + #endif diff --git a/arch/arm/mach-omap2/pm-domains.c b/arch/arm/mach-omap2/pm-domains.c new file mode 100644 index 000..b373b21 --- /dev/null +++ b/arch/arm/mach-omap2/pm-domains.c @@ -0,0 +1,228 @@ +/* + * DT based powerdomain support for OMAP2+ SoCs + * + * Copyright (C) 2015 Texas Instruments, Inc. + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include "powerdomain.h" +#include "clockdomain.h" +#include "prcm-common.h" + +#define OMAP_PD_TYPE_PWRDM 0x1 +#define OMAP_PD_TYPE_CLKDM 0x2 + +struct omap_pm_domain { + void *domain; + int type; + struct generic_pm_domain pd; +}; + +#define to_omap_pm_domain(genpd) container_of(genpd, struct omap_pm_domain, pd) + +static int _get_offset(struct device_node *node, u16 *val) +{ + u32 tmp; + + if (of_property_read_u32(node, "reg", &tmp)) { + pr_err("%s: %s does not provide reg addr!\n", __func__, + node->name); + return -EINVAL; + } + + *val = (u16)tmp; + + return 0; +} + +static int omap_genpd_power_off(struct generic_pm_domain *gen_pd) +{ + return 0; +} + +static int omap_genpd_power_on(struct generic_pm_domain *gen_pd) +{ + return 0; +} + +int __init of_omap_powerdomain_init(const struct of_device_id *match_table) +{ + struct device_node *np; + const struct of_device_id *match; + struct powerdomain *pd_tmpl, *pd; +
[RFC 2/7] ARM: OMAP4+: PRCM: add support for registering PRCM partition against DT node
The PRCM core code contains a notion of PRCM partition and instances, and all PRCM driver register accesses are done through the partitions. The APIs provided in this patch make it possible for PRCM child nodes to map their register spaces against proper PRCM partition, and access the correct partition ID through the common PRCM APIs. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/cm_common.c | 12 + arch/arm/mach-omap2/prcm-common.h |5 arch/arm/mach-omap2/prm_common.c | 53 + 3 files changed, 70 insertions(+) diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index 23e8bce..541ecaa 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -23,6 +23,8 @@ #include "cm33xx.h" #include "cm44xx.h" #include "clock.h" +#include "prcm43xx.h" +#include "prcm44xx.h" /* * cm_ll_data: function pointers to SoC-specific implementations of @@ -225,11 +227,13 @@ int cm_unregister(struct cm_ll_data *cld) static struct omap_prcm_init_data cm_data __initdata = { .index = TI_CLKM_CM, .init = omap4_cm_init, + .part = OMAP4430_CM1_PARTITION, }; static struct omap_prcm_init_data cm2_data __initdata = { .index = TI_CLKM_CM2, .init = omap4_cm_init, + .part = OMAP4430_CM2_PARTITION, }; #endif @@ -268,6 +272,7 @@ static struct omap_prcm_init_data am4_prcm_data __initdata = { .index = TI_CLKM_CM, .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE, .init = omap4_cm_init, + .part = AM43XX_CM_PARTITION, }; #endif @@ -316,6 +321,7 @@ int __init omap2_cm_base_init(void) const struct of_device_id *match; struct omap_prcm_init_data *data; void __iomem *mem; + int ret; for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { data = (struct omap_prcm_init_data *)match->data; @@ -337,6 +343,12 @@ int __init omap2_cm_base_init(void) if (data->init && (data->flags & CM_SINGLE_INSTANCE || (cm_base && cm2_base))) data->init(data); + + if (data->part) { + ret = omap_prcm_map_partition(np, data->part); + if (ret) + return ret; + } } return 0; diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 6ae0b3a..037754d 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -527,6 +527,7 @@ struct omap_prcm_irq_setup { * @device_inst_offset: device instance offset within the module address space * @init: low level PRCM init function for this module * @np: device node for this PRCM module + * @part: PRCM partition ID, applicable for OMAP4+ only */ struct omap_prcm_init_data { int index; @@ -536,6 +537,7 @@ struct omap_prcm_init_data { s32 device_inst_offset; int (*init)(const struct omap_prcm_init_data *data); struct device_node *np; + u8 part; }; extern void omap_prcm_irq_cleanup(void); @@ -545,6 +547,9 @@ extern int omap_prcm_event_to_irq(const char *event); extern void omap_prcm_irq_prepare(void); extern void omap_prcm_irq_complete(void); +int omap_prcm_map_partition(struct device_node *np, u8 part); +int omap_prcm_get_partition(struct device_node *np); + # endif #endif diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 7add799..a3f0aef 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -37,6 +37,7 @@ #include "prm54xx.h" #include "prm7xx.h" #include "prcm43xx.h" +#include "prcm44xx.h" #include "common.h" #include "clock.h" #include "cm.h" @@ -77,6 +78,8 @@ u16 prm_features; static struct prm_ll_data null_prm_ll_data; static struct prm_ll_data *prm_ll_data = &null_prm_ll_data; +static struct device_node *prcm_base_nodes[OMAP4_MAX_PRCM_PARTITIONS]; + /* Private functions */ /* @@ -670,6 +673,7 @@ static struct omap_prcm_init_data omap4_prm_data __initdata = { .init = omap44xx_prm_init, .device_inst_offset = OMAP4430_PRM_DEVICE_INST, .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT, + .part = OMAP4430_PRM_PARTITION, }; #endif @@ -679,6 +683,7 @@ static struct omap_prcm_init_data omap5_prm_data __initdata = { .init = omap44xx_prm_init, .device_inst_offset = OMAP54XX_PRM_DEVICE_INST, .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE, + .part = OMAP54XX_PRM_PARTITION, }; #endif @@ -688,6 +693,7 @@ static struct omap_prcm_init_data dra7_prm_data __initdata = { .init = omap44xx_prm_init, .device_inst_offset = D
[RFC 3/7] ARM: OMAP4+: PRCM: parse PRCM MPU base address from DT
All the OMAP4+ boards are DT based only, so the prcm_mpu base address can be parsed from DT. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/io.c |4 arch/arm/mach-omap2/prm_common.c | 18 ++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a253aaf..fc207ff 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -48,7 +48,6 @@ #include "cm44xx.h" #include "prm.h" #include "cm.h" -#include "prcm_mpu44xx.h" #include "prminst44xx.h" #include "prm2xxx.h" #include "prm3xxx.h" @@ -628,7 +627,6 @@ void __init omap4430_init_early(void) { omap2_set_globals_tap(OMAP443X_CLASS, OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); - omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); omap2_control_base_init(); omap4xxx_check_revision(); omap4xxx_check_features(); @@ -656,7 +654,6 @@ void __init omap5_init_early(void) { omap2_set_globals_tap(OMAP54XX_CLASS, OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); - omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap2_control_base_init(); omap4_pm_init_early(); omap2_prcm_base_init(); @@ -681,7 +678,6 @@ void __init omap5_init_late(void) void __init dra7xx_init_early(void) { omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); - omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap2_control_base_init(); omap4_pm_init_early(); omap2_prcm_base_init(); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index a3f0aef..ea2fb54 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -38,6 +38,7 @@ #include "prm7xx.h" #include "prcm43xx.h" #include "prcm44xx.h" +#include "prcm_mpu44xx.h" #include "common.h" #include "clock.h" #include "cm.h" @@ -697,6 +698,13 @@ static struct omap_prcm_init_data dra7_prm_data __initdata = { }; #endif +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) +static struct omap_prcm_init_data omap4_prcm_mpu_data __initdata = { + .part = OMAP4430_PRCM_MPU_PARTITION, +}; +#endif + #ifdef CONFIG_SOC_AM43XX static struct omap_prcm_init_data am4_prm_data __initdata = { .index = TI_CLKM_PRM, @@ -741,6 +749,10 @@ static const struct of_device_id omap_prcm_dt_match_table[] __initconst = { #ifdef CONFIG_SOC_DRA7XX { .compatible = "ti,dra7-prm", .data = &dra7_prm_data }, #endif +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) + { .compatible = "ti,omap4-prcm-mpu", .data = &omap4_prcm_mpu_data }, +#endif { } }; @@ -769,6 +781,9 @@ int __init omap2_prm_base_init(void) if (data->index == TI_CLKM_PRM) prm_base = mem + data->offset; + if (data->part == OMAP4430_PRCM_MPU_PARTITION) + omap2_set_globals_prcm_mpu(mem); + data->mem = mem; data->np = np; @@ -813,6 +828,9 @@ int __init omap_prcm_init(void) for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) { data = match->data; + if (data->part == OMAP4430_PRCM_MPU_PARTITION) + continue; + ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); if (ret) return ret; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 4/7] ARM: OMAP2+: PRCM: move PRCM data init later in boot sequence
This avoids the need to use memblock_virt_alloc in the code. Done in preparation of adding generic PM domains to OMAP platform codebase; generic PM domain registration doesn't work during early_init. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/io.c | 180 -- arch/arm/mach-omap2/omap_hwmod.c |5 +- drivers/clk/ti/clk.c |3 +- 3 files changed, 118 insertions(+), 70 deletions(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index fc207ff..282fd96 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -62,6 +62,12 @@ static int (*omap_clk_soc_init)(void); /* + * prcm_data_init: points to a function that does the SoC-specific + * PRCM data (pwrdm/clkdm/hwmod) initializations + */ +static void (*prcm_data_init)(void); + +/* * The machine specific code may provide the extra mapping besides the * default mapping provided here. */ @@ -375,19 +381,24 @@ static void __init __maybe_unused omap_common_late_init(void) } #ifdef CONFIG_SOC_OMAP2420 -void __init omap2420_init_early(void) +static void __init omap2420_prcm_data_init(void) { - omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); - omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), - OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); - omap2_control_base_init(); - omap2xxx_check_revision(); omap2_prcm_base_init(); omap2xxx_voltagedomains_init(); omap242x_powerdomains_init(); omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); +} + +void __init omap2420_init_early(void) +{ + omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); + omap2_control_base_init(); + omap2xxx_check_revision(); + prcm_data_init = omap2420_prcm_data_init; omap_clk_soc_init = omap2420_dt_clk_init; rate_table = omap2420_rate_table; } @@ -401,19 +412,24 @@ void __init omap2420_init_late(void) #endif #ifdef CONFIG_SOC_OMAP2430 -void __init omap2430_init_early(void) +static void __init omap2430_prcm_data_init(void) { - omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); - omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), - OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); - omap2_control_base_init(); - omap2xxx_check_revision(); omap2_prcm_base_init(); omap2xxx_voltagedomains_init(); omap243x_powerdomains_init(); omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); +} + +void __init omap2430_init_early(void) +{ + omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); + omap2_control_base_init(); + omap2xxx_check_revision(); + prcm_data_init = omap2430_prcm_data_init; omap_clk_soc_init = omap2430_dt_clk_init; rate_table = omap2430_rate_table; } @@ -431,22 +447,8 @@ void __init omap2430_init_late(void) * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. */ #ifdef CONFIG_ARCH_OMAP3 -void __init omap3_init_early(void) +static void __init omap3_prcm_data_init(void) { - omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); - omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), - OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); - /* XXX: remove these once OMAP3 is DT only */ - if (!of_have_populated_dt()) { - omap2_set_globals_control( - OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE)); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); - omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), -NULL); - } - omap2_control_base_init(); - omap3xxx_check_revision(); - omap3xxx_check_features(); omap2_prcm_base_init(); /* XXX: remove these once OMAP3 is DT only */ if (!of_have_populated_dt()) { @@ -471,6 +473,25 @@ void __init omap3_init_early(void) } } +void __init omap3_init_early(void) +{ + omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); + /* XXX: remove these once OMAP3 is DT only */ + if (!of_have_populated_dt()) { + omap2_set_globals_control( + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL
[RFC 7/7] ARM: OMAP4: PRCM: convert to DT based pwrdm/clkdm data
Clock and powerdomain data can now be moved partially to DT. Some init data is still left to the existing data files, to act as templates for the DT based data. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clockdomains44xx_data.c | 327 +++ arch/arm/mach-omap2/powerdomains44xx_data.c | 124 +++--- 2 files changed, 60 insertions(+), 391 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 95192a0..823f546 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -21,6 +21,7 @@ #include #include +#include #include "clockdomain.h" #include "cm1_44xx.h" @@ -31,413 +32,145 @@ #include "prcm44xx.h" #include "prcm_mpu44xx.h" -/* Static Dependencies for OMAP4 Clock Domains */ - -static struct clkdm_dep d2d_wkup_sleep_deps[] = { - { .clkdm_name = "abe_clkdm" }, - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_2_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { .clkdm_name = "l3_init_clkdm" }, - { .clkdm_name = "l4_cfg_clkdm" }, - { .clkdm_name = "l4_per_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep ducati_wkup_sleep_deps[] = { - { .clkdm_name = "abe_clkdm" }, - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_2_clkdm" }, - { .clkdm_name = "l3_dss_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { .clkdm_name = "l3_gfx_clkdm" }, - { .clkdm_name = "l3_init_clkdm" }, - { .clkdm_name = "l4_cfg_clkdm" }, - { .clkdm_name = "l4_per_clkdm" }, - { .clkdm_name = "l4_secure_clkdm" }, - { .clkdm_name = "l4_wkup_clkdm" }, - { .clkdm_name = "tesla_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep iss_wkup_sleep_deps[] = { - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep ivahd_wkup_sleep_deps[] = { - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep l3_dma_wkup_sleep_deps[] = { - { .clkdm_name = "abe_clkdm" }, - { .clkdm_name = "ducati_clkdm" }, - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_dss_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { .clkdm_name = "l3_init_clkdm" }, - { .clkdm_name = "l4_cfg_clkdm" }, - { .clkdm_name = "l4_per_clkdm" }, - { .clkdm_name = "l4_secure_clkdm" }, - { .clkdm_name = "l4_wkup_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep l3_dss_wkup_sleep_deps[] = { - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_2_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = { - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep l3_init_wkup_sleep_deps[] = { - { .clkdm_name = "abe_clkdm" }, - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { .clkdm_name = "l4_cfg_clkdm" }, - { .clkdm_name = "l4_per_clkdm" }, - { .clkdm_name = "l4_secure_clkdm" }, - { .clkdm_name = "l4_wkup_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { .clkdm_name = "l4_per_clkdm" }, - { NULL }, -}; - -static struct clkdm_dep mpu_wkup_sleep_deps[] = { - { .clkdm_name = "abe_clkdm" }, - { .clkdm_name = "ducati_clkdm" }, - { .clkdm_name = "ivahd_clkdm" }, - { .clkdm_name = "l3_1_clkdm" }, - { .clkdm_name = "l3_2_clkdm" }, - { .clkdm_name = "l3_dss_clkdm" }, - { .clkdm_name = "l3_emif_clkdm" }, - { .clkdm_name = "l3_gfx_clkdm" }, - { .clkdm_name = "l3_init_clkdm" }, - { .clkdm_name = "l4_cfg_clkdm" }, - { .clkdm_name = "l4_per_clkdm" }, - { .clkdm_name = "l4_sec
Re: [PATCH v2 5/6] ARM: AM43XX: HWMOD: Add rtc hwmod
On 08/12/2015 05:39 PM, Paul Walmsley wrote: On Mon, 10 Aug 2015, Keerthy wrote: The patch adds rtc hwmod. This is present on gp and sk evm and not on epos evm. Hence adding it selectively using a seprate list. Signed-off-by: Keerthy So just to confirm, the RTC IP block has been physically removed or permanently disabled on these new AM438x chips? So the registers are no longer accessible by the MPU? Is there a TRM available for these chips? No public TRM available, as the SoC mostly contains secure environment support on them. The RTC module is physically present on the SoC, but it is permanently disabled. A secure RTC is used instead on these devices, where needed. -Tero - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] omap clock dts changes for v4.3 merge window
The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590: Linux 4.2-rc2 (2015-07-12 15:10:30 -0700) are available in the git repository at: https://github.com/t-kristo/linux-pm.git for-4.3/ti-clk-dt for you to fetch changes up to dff8a207815a605872dfc5bffc1bae1cad29d87c: ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock (2015-07-31 12:13:18 +0300) Keerthy (2): ARM: dts: AM437X: add dpll_clksel_mac_clk node ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock arch/arm/boot/dts/am4372.dtsi|7 +-- arch/arm/boot/dts/am43xx-clocks.dtsi |9 + drivers/clk/ti/clk-43xx.c|1 + 3 files changed, 15 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/3] ARM: dts: dra7: scm_conf node cleanup
On 07/27/2015 01:27 PM, Roger Quadros wrote: Hi, This series cleans up the scm_conf node. v2: - split patch. use only core_sma_sw registers for the new scm_conf child. Series looks ok to me, so: Acked-by: Tero Kristo cheers, -roger Roger Quadros (3): ARM: dts: dra7: Remove ctrl_core and ctrl_general nodes ARM: dts: dra7: fix pinmux@1400 resource length ARM: dts: dra7: Add scm_conf@1c04 node arch/arm/boot/dts/dra7.dtsi | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY
On 07/17/2015 04:47 PM, Roger Quadros wrote: This register is required to be passed to the SATA PHY driver to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 8f1e25b..4a0718c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1140,6 +1140,7 @@ ctrl-module = <&omap_control_sata>; clocks = <&sys_clkin1>, <&sata_ref_clk>; clock-names = "sysclk", "refclk"; + syscon-pllreset = <&scm_conf 0x3fc>; #phy-cells = <0>; }; Looks fine to me. Make sure you use this register via regmap_update_bits only, seeing there is another potential user for the same register. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes
On 07/17/2015 04:47 PM, Roger Quadros wrote: scm_conf1 maps the control register address space after the padconf till the end. Fix the scm_conf and pmx_core resource lengths. We need to add 4 bytes to include the last 32-bit register space. Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes. They are not used by anyone and no longer needed as they are covered by scm_conf and scm_conf1. Looks like you are doing three things in this patch, maybe split it up as such? Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7.dtsi | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4a0718c..d07c34c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -141,7 +141,7 @@ dra7_pmx_core: pinmux@1400 { compatible = "ti,dra7-padconf", "pinctrl-single"; - reg = <0x1400 0x0464>; + reg = <0x1400 0x0468>; #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; @@ -149,6 +149,13 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x3fff>; }; + + scm_conf1: scm_conf@1 { Should be ... scm_conf@1868? Are there any users for this area anyway? I don't think we should map this area just for fun of it. Mostly it looks like this contains efuse values for OPPs, which should be mapped from the OPP layer, not as a generic syscon. + compatible = "syscon"; + reg = <0x1868 0x03e0>; + #address-cells = <1>; + #size-cells = <1>; + }; }; cm_core_aon: cm_core_aon@5000 { @@ -286,16 +293,6 @@ #thermal-sensor-cells = <1>; }; - dra7_ctrl_core: ctrl_core@4a002000 { - compatible = "syscon"; - reg = <0x4a002000 0x6d0>; - }; - - dra7_ctrl_general: tisyscon@4a002e00 { - compatible = "syscon"; - reg = <0x4a002e00 0x7c>; - }; I thought I had removed these already and yes... this was done in commit d919501feffa8715147582c3ffce96fad0c7016f already, but seems they were added back in a resolution for a merge conflict later. -Tero - sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] ARM: OMAP2+: hwmod: RTC: Add lock and unlock hooks
On 07/16/2015 01:13 PM, Paul Walmsley wrote: On Thu, 16 Jul 2015, Tero Kristo wrote: On 07/16/2015 03:15 AM, Paul Walmsley wrote: On Tue, 14 Jul 2015, Tero Kristo wrote: On 07/14/2015 01:09 PM, Lokesh Vutla wrote: Hi, On Wednesday 10 June 2015 02:56 PM, Lokesh Vutla wrote: Some IP blocks like RTC, needs an additional unlocking mechanism for writing to its registers. This patch adds optional lock and unlock function pointers to the IP block's hwmod data which gets executed before and after writing into IP sysconfig register. And also hook lock and unlock functions to AMx3xx, DRA7 RTC hwmod data, so that sysconfig registers are updated properly. ping on this series. Thanks and regards, Lokesh [...] It is also racy, as there is no locking in place to avoid concurrent access to the lock/unlock registers across hwmod+driver. I don't see the race. Where is it? See drivers/rtc/rtc-omap.c, am3352_rtc_unlock and am3352_rtc_lock. That code is accessing the exact same registers. I guess my question is, when is it possible that code could race with the hwmod code for the same device? Hmm yea I think you are right, this only gets potentially called within pm_runtime_get/put_sync for RTC. The current sequence is highly inefficient though, as we are doing multiple lock/unlock operations to the RTC from multiple sources. See following rtcwake trace on am43xx-gp-evm as an example. / # rtcwake -s 4 -m mem [7.425322] am3352_rtc_unlock [7.428330] am3352_rtc_lock [7.431139] am3352_rtc_unlock [7.434116] am3352_rtc_lock wakeup from "mem" at Sat Jan 1 00:00:11 2000 [7.448549] PM: Syncing filesystems ... done. [7.455425] Freezing user space processes ... (elapsed 0.001 seconds) done. [7.463738] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) do ne. [7.472532] Suspending console(s) (use no_console_suspend to debug) [7.481878] am3352_rtc_unlock [7.481889] am3352_rtc_lock [7.482307] PM: suspend of devices complete after 2.713 msecs [7.483479] PM: late suspend of devices complete after 1.153 msecs [7.484727] omap_hwmod_rtc_unlock [7.484733] omap_hwmod_rtc_lock [7.485182] PM: noirq suspend of devices complete after 1.685 msecs [7.485190] Disabling non-boot CPUs ... [7.485199] PM: Successfully put all powerdomains to target state [7.485199] PM: Wakeup source RTC Alarm [7.499853] PM: noirq resume of devices complete after 14.558 msecs [7.500047] am3352_rtc_unlock [7.500052] am3352_rtc_lock [7.500123] am3352_rtc_unlock [7.500128] am3352_rtc_lock [7.501019] PM: early resume of devices complete after 0.809 msecs [7.501464] am3352_rtc_unlock [7.501472] am3352_rtc_lock [7.558046] PM: resume of devices complete after 57.007 msecs [7.638807] Restarting tasks ... done. [7.643173] am3352_rtc_unlock [7.646162] am3352_rtc_lock But, I guess this is for some interested party to optimize if needed, and it is mostly an issue with the RTC driver itself. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: OMAP3: clock: remove un-used core dpll re-program code
Remove the OMAP3 core DPLL re-program code, and the associated SRAM code that does the low-level programming of the DPLL divider, idling of the SDRAM etc. This code was never fully implemented in the kernel; things missing were driver side handling of core clock changes (they need to account for their functional clock rate being changed on-the-fly), and the whole framework required for handling this. Thus, there is not much point to keep carrying the low-level support code either. Signed-off-by: Tero Kristo Cc: Tony Lindgren Cc: Paul Walmsley --- arch/arm/mach-omap2/Makefile |3 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 119 --- arch/arm/mach-omap2/sram.c | 25 --- arch/arm/mach-omap2/sram.h | 14 -- arch/arm/mach-omap2/sram34xx.S | 346 5 files changed, 1 insertion(+), 506 deletions(-) delete mode 100644 arch/arm/mach-omap2/clkt34xx_dpll3m2.c delete mode 100644 arch/arm/mach-omap2/sram34xx.S diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 903c85b..66129b6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -49,7 +49,6 @@ AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec) # Functions loaded to SRAM obj-$(CONFIG_SOC_OMAP2420) += sram242x.o obj-$(CONFIG_SOC_OMAP2430) += sram243x.o -obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o AFLAGS_sram242x.o :=-Wa,-march=armv6 AFLAGS_sram243x.o :=-Wa,-march=armv6 @@ -188,7 +187,7 @@ obj-$(CONFIG_ARCH_OMAP2)+= clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o +obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c deleted file mode 100644 index eb69acf..000 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * OMAP34xx M2 divider clock code - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation - * - * Paul Walmsley - * Jouni Högander - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include "clock.h" -#include "clock3xxx.h" -#include "clock34xx.h" -#include "sdrc.h" -#include "sram.h" - -#define CYCLES_PER_MHZ 100 - -/* - * CORE DPLL (DPLL3) M2 divider rate programming functions - * - * These call into SRAM code to do the actual CM writes, since the SDRAM - * is clocked from DPLL3. - */ - -/** - * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider - * @clk: struct clk * of DPLL to set - * @rate: rounded target rate - * - * Program the DPLL M2 divider with the rounded target rate. Returns - * -EINVAL upon error, or 0 upon success. - */ -int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 new_div = 0; - u32 unlock_dll = 0; - u32 c; - unsigned long validrate, sdrcrate, _mpurate; - struct omap_sdrc_params *sdrc_cs0; - struct omap_sdrc_params *sdrc_cs1; - int ret; - unsigned long clkrate; - - if (!clk || !rate) - return -EINVAL; - - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); - if (validrate != rate) - return -EINVAL; - - sdrcrate = __clk_get_rate(sdrc_ick_p); - clkrate = __clk_get_rate(hw->clk); - if (rate > clkrate) - sdrcrate <<= ((rate / clkrate) >> 1); - else - sdrcrate >>= ((clkrate / rate) >> 1); - - ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); - if (ret) - return -EINVAL; - - if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { - pr_debug("clock: will unlock SDRC DLL\n"); - unlock_dll = 1; - } - - /* -* XXX This only needs to be done when the CPU frequency changes -*/ - _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; - c =
Re: [PATCH 0/3] ARM: OMAP2+: hwmod: RTC: Add lock and unlock hooks
On 07/16/2015 03:15 AM, Paul Walmsley wrote: On Tue, 14 Jul 2015, Tero Kristo wrote: On 07/14/2015 01:09 PM, Lokesh Vutla wrote: Hi, On Wednesday 10 June 2015 02:56 PM, Lokesh Vutla wrote: Some IP blocks like RTC, needs an additional unlocking mechanism for writing to its registers. This patch adds optional lock and unlock function pointers to the IP block's hwmod data which gets executed before and after writing into IP sysconfig register. And also hook lock and unlock functions to AMx3xx, DRA7 RTC hwmod data, so that sysconfig registers are updated properly. ping on this series. Thanks and regards, Lokesh [...] It is also racy, as there is no locking in place to avoid concurrent access to the lock/unlock registers across hwmod+driver. I don't see the race. Where is it? See drivers/rtc/rtc-omap.c, am3352_rtc_unlock and am3352_rtc_lock. That code is accessing the exact same registers. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] clk: ti: clock driver code migration to drivers
On 07/16/2015 04:51 AM, Paul Walmsley wrote: On Tue, 14 Jul 2015, Tony Lindgren wrote: * Tero Kristo [150714 03:34]: On 07/14/2015 12:54 PM, Tony Lindgren wrote: * Tero Kristo [150714 01:56]: This pull request contains the TI clock driver set to move the clock implementations under clock driver. Some small portions of the clock driver code still remain under mach-omap2 after this, it should be decided whether this code is now obsolete and should be deleted or should someone try to fix it. Hmm care to clarify what is obsolete or broken after this series? Not after this series, was broken/obsolete already before. A couple of omap2/omap3 specific clock files still remain under mach-omap2, they are DVFS related. OMAP3 core dvfs support is currently completely unused (this could probably be removed, or shall we re-introduce the painful core dvfs at some point again?), and parts of the omap2 core dpll handling code should probably be re-written; or at least verified that it actually works properly. I can't test OMAP2 DVFS myself so don't dare to fiddle with it I could probably try to get some sort of DVFS test case to work on the board farm OMAP2 board I have access to though, I can investigate this. People seem to still want the 1 GiHz support, but I think that only depends on the SmartReflex and some kind of replacement for voltagedomains. So if the core DVFS support is unused, I doubt it's very high on anybody's list right now. At least several years ago, basic CORE DVFS support was working on OMAP3. The clock source changed rate, DRAM parameters were changed on the SDRC, etc. What was not implemented was pre-rate-change and post-rate-change notifiers in many of the device drivers, because the infrastructure didn't exist at the time in the clock code. Yes this is true, Nokia did an internal implementation for the pre/post notifier stuff which was never accepted upstream. The core dvfs code is no longer used in kernel for anything, it is just built in. The usefulness of the whole feature can be debated also, the use cases where it actually gives power savings is rather limited. I'll post a patch to remove the 'dead' core-dvfs code to the list, we can debate the issue there. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY
On 07/15/2015 04:47 PM, Roger Quadros wrote: Hi, On 15/07/15 15:07, Tony Lindgren wrote: * Kishon Vijay Abraham I [150715 04:24]: Hi Roger, On Tuesday 02 June 2015 02:40 PM, Roger Quadros wrote: This register is required to be passed to the SATA PHY driver to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f03a091..260f300 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1135,6 +1135,7 @@ ctrl-module = <&omap_control_sata>; clocks = <&sys_clkin1>, <&sata_ref_clk>; clock-names = "sysclk", "refclk"; + syscon-pllreset = <&dra7_ctrl_core 0x3fc>; I think all users of syscon should be made child node of scm_conf. Tony and Tero, is that right? It can't be child of scm_conf as the address is outside it's range. Looks like I have to add a new child to scm node that maps beyond the dra7_pmx_core padconf address range. If so, then we might have to modify the driver too. Yeah there should not be much need to use syscon outside scm_conf area and for I2C devices. If there's some other misc register area in dra7 in addition to scm_conf then it might make sense to use it. But in general, for the SCM registers, just a normal loadable kernel driver module doing of_ioremap on a dedicated range of registers is always a better option :) Lets take for example this register CTRL_CORE_SMA_SW_0. It has the SATA PLL_SOFT_RESET bit, EMIF1/2 gating control bits and ISOLATE bit. I don't see this fitting in any driver except the syscon approach. cheers, -roger Yea I think scm_conf can generally contain lots of weird registers that can have multiple users / use-cases. This is the junk-yard of SoC features the designers had no idea where to put them; so they put it under scm_conf. I'd say in some cases we are probably forced to map to it from other drivers, this is one of the reasons it is a syscon map in the first place, and generally speaking, they should not be children of scm_conf in the DT layout. You could probably add a "dummy" node under scm_conf which maps to the scm register, and which you would refer to from the sata driver. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL]
Hi Stephen, Mike, Here is the updated pull-request based on Stephen's request. This is on top of 4.1-rc2. The branch is force updated version of the one Stephen tried yesterday, the old one contained the minor build issues present on v3 of the patch set. I did a quick try of merging this branch on top of 4.2-rc2 and it works fine without any conflicts. -Tero The following changes since commit 5ebe6afaf0057ac3eaeb98defd5456894b446d22: Linux 4.1-rc2 (2015-05-03 19:22:23 -0700) are available in the git repository at: https://github.com/t-kristo/linux-pm.git for-4.2/ti-clk-move for you to fetch changes up to 989feafb84118a840ff21250a1e5f516f43e3dbb: clk: ti: move low-level access and init code under clock driver (2015-06-02 12:31:46 +0300) Tero Kristo (27): ARM: OMAP2+: clock: export driver API to setup/get clock features clk: ti: move generic OMAP DPLL implementation under drivers/clk clk: ti: move OMAP4+ DPLL implementation under drivers/clk clk: ti: move interface clock implementation under drivers/clk ARM: OMAP3: dpll3-m2: get rid of obsolete clksel access ARM: OMAP2+: clk: remove obsolete clksel support code ARM: OMAP2+: clock: remove clock_common_data.c file ARM: OMAP36xx: remove clock36xx.c/.h files clk: ti: autoidle: move generic autoidle handling code to clock driver clk: ti: move omap2_clk_enable_init_clocks under clock driver ARM: OMAP2+: clock: remove support for legacy mpurate command line param ARM: OMAP2+: clock: add support for clkdm ops to the low level clk ops ARM: OMAP2+: clock: add support for specific CM ops to ti_clk_ll_ops clk: ti: dpll: move omap3 DPLL functionality to clock driver ARM: OMAP3: clock: remove clock3xxx.c file ARM: OMAP2+: clock: remove clkdm_control static boolean from code clk: ti: dflt: move support for default gate clock to clock driver clk: ti: omap2430: move clock support code under clock driver clk: ti: clkdm: move clkdm gate clock support code to clock driver clk: ti: omap34xx: move omap34xx clock type support code to clock driver ARM: OMAP4: clock: remove clock44xx.h header clk: ti: am3517: move remaining am3517 clock support code to clock driver clk: ti: move some public definitions to private header ARM: OMAP2+: clock: remove dead definitions from the clock header file clk: ti: remove exported ll_ops struct, instead add an API for registration ARM: OMAP2+: clock: remove legacy omap2_clk_readl/writel APIs clk: ti: move low-level access and init code under clock driver arch/arm/mach-omap2/Makefile | 22 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c |7 +- arch/arm/mach-omap2/clkt_clksel.c | 466 -- arch/arm/mach-omap2/clkt_iclk.c| 68 -- arch/arm/mach-omap2/clock.c| 675 +--- arch/arm/mach-omap2/clock.h| 205 +- arch/arm/mach-omap2/clock2430.c| 57 -- arch/arm/mach-omap2/clock2xxx.c| 57 -- arch/arm/mach-omap2/clock34xx.c| 138 arch/arm/mach-omap2/clock34xx.h| 18 - arch/arm/mach-omap2/clock3517.c| 118 arch/arm/mach-omap2/clock3517.h| 14 - arch/arm/mach-omap2/clock36xx.c| 69 -- arch/arm/mach-omap2/clock36xx.h| 13 - arch/arm/mach-omap2/clock3xxx.c| 135 arch/arm/mach-omap2/clock44xx.h| 20 - arch/arm/mach-omap2/clock_common_data.c| 115 arch/arm/mach-omap2/io.c |3 +- drivers/clk/ti/Makefile| 17 +- drivers/clk/ti/apll.c |2 + drivers/clk/ti/autoidle.c | 121 +++- drivers/clk/ti/clk-2xxx.c |2 + drivers/clk/ti/clk-33xx.c |2 + drivers/clk/ti/clk-3xxx.c | 244 +++ drivers/clk/ti/clk-43xx.c |2 + drivers/clk/ti/clk-44xx.c |2 + drivers/clk/ti/clk-54xx.c |2 + drivers/clk/ti/clk-7xx.c |3 +- drivers/clk/ti/clk-816x.c |2 + drivers/clk/ti/clk.c | 145 - drivers/clk/ti/clkt_dflt.c | 316 + .../arm/mach-omap2 => drivers/clk/ti}/clkt_dpll.c | 27 +- drivers/clk/ti/clkt_iclk.c | 101 +++ drivers/clk/ti/clock.h | 113 drivers/clk/ti/clock
Re: [GIT PULL] clk: ti: clock driver code migration to drivers
On 07/14/2015 11:31 PM, Stephen Boyd wrote: On 07/14/2015 01:09 PM, Tero Kristo wrote: On 07/14/2015 10:29 PM, Stephen Boyd wrote: On 07/14/2015 01:54 AM, Tero Kristo wrote: The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590: Linux 4.2-rc2 (2015-07-12 15:10:30 -0700) Why did this get rebased onto v4.2-rc2? I thought it was all ready to go based on v4.1-rc2? If possible leave it on v4.1-rc2 please. You mean 4.2-rc1 I guess...? Or do you really mean the old 4.1-rc2? Old 4.1-rc2 please Ok, posting a new one after this, this one can be ignored. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] clk: ti: clock driver code migration to drivers
On 07/14/2015 10:29 PM, Stephen Boyd wrote: On 07/14/2015 01:54 AM, Tero Kristo wrote: The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590: Linux 4.2-rc2 (2015-07-12 15:10:30 -0700) Why did this get rebased onto v4.2-rc2? I thought it was all ready to go based on v4.1-rc2? If possible leave it on v4.1-rc2 please. You mean 4.2-rc1 I guess...? Or do you really mean the old 4.1-rc2? are available in the git repository at: g...@github.com:t-kristo/linux-pm.git for-4.3/ti-clk-move Also I can't fetch this. Please give a public URL and not the one you use for github. Oh sorry about that, git request-pull does this automatically. I'll update my script to use public URL. I fetched the for-4.2/ti-clk-move branch and did a test merge and fixed up omap3_noncore_dpll_determine_rate() and omap4_dpll_regm4xen_determine_rate() for the new determine rate signature and it looks like things are still compiling. So please redo the tag for that branch. Yea I can send a new pull-request tomorrow once my question is clarified. The code in the two branches is identical regarding the clock code changes, and both can be considered immutable and ready for pull if need be. -Tero 8<- diff --cc include/linux/clk/ti.h index 448b4f87b9eb,f1838256fbaa.. --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index d4d232fd89bc..d8aafd333058 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -250,12 +250,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); -long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *best_parent_rate, - struct clk_hw **best_parent_clk); +int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req); long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, @@ -273,12 +269,8 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); -long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, -unsigned long rate, -unsigned long min_rate, -unsigned long max_rate, -unsigned long *best_parent_rate, -struct clk_hw **best_parent_clk); +int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req); extern struct ti_clk_ll_ops *ti_clk_ll_ops; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] ARM: OMAP2+: hwmod: RTC: Add lock and unlock hooks
On 07/14/2015 01:09 PM, Lokesh Vutla wrote: Hi, On Wednesday 10 June 2015 02:56 PM, Lokesh Vutla wrote: Some IP blocks like RTC, needs an additional unlocking mechanism for writing to its registers. This patch adds optional lock and unlock function pointers to the IP block's hwmod data which gets executed before and after writing into IP sysconfig register. And also hook lock and unlock functions to AMx3xx, DRA7 RTC hwmod data, so that sysconfig registers are updated properly. ping on this series. Thanks and regards, Lokesh This looks kind of hackish to have the unlock + lock functionality copy pasted to both driver and hwmod. It is also racy, as there is no locking in place to avoid concurrent access to the lock/unlock registers across hwmod+driver. Can we avoid these issues somehow? -Tero Tested on: DRA7-evm: http://pastebin.ubuntu.com/1169/ DRA72-evm: http://pastebin.ubuntu.com/11688901/ BeagleBoard-x15: http://pastebin.ubuntu.com/11688907/ BeagleBoneBlack: http://pastebin.ubuntu.com/11688923/ AM437x-gp-evm: http://pastebin.ubuntu.com/11689157/ (Used an out of tree patch to enable RTC) Lokesh Vutla (3): ARM: OMAP2+: hwmod: add support for lock and unlock hooks ARM: DRA: hwmod: RTC: Add lock and unlock functions ARM: AMx3xx: RTC: Add lock and unlock functions arch/arm/mach-omap2/omap_hwmod.c | 13 ++ arch/arm/mach-omap2/omap_hwmod.h | 6 +++ .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 2 + arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 + arch/arm/mach-omap2/omap_hwmod_reset.c | 47 ++ 5 files changed, 70 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node
On 07/14/2015 02:06 PM, Tony Lindgren wrote: * Keerthy [150625 06:48]: On Thursday 18 June 2015 02:36 PM, Mugunthan V N wrote: On Thursday 18 June 2015 01:31 PM, Keerthy wrote: The series adds the missing clock node needed for cpsw. Keerthy (2): CLK: TI: add dpll_clksel_mac_clk node ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock arch/arm/boot/dts/am4372.dtsi| 7 +-- arch/arm/boot/dts/am43xx-clocks.dtsi | 9 + drivers/clk/ti/clk-43xx.c| 1 + 3 files changed, 15 insertions(+), 2 deletions(-) Tested-by: Mugunthan V N Thanks Mugunthan. A gentle ping on this series. Tero, care to review this series? Acked-by: Tero Kristo I guess this should go through your tree as this is mostly dts changes? -Tero Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] clk: ti: clock driver code migration to drivers
On 07/14/2015 12:54 PM, Tony Lindgren wrote: * Tero Kristo [150714 01:56]: This pull request contains the TI clock driver set to move the clock implementations under clock driver. Some small portions of the clock driver code still remain under mach-omap2 after this, it should be decided whether this code is now obsolete and should be deleted or should someone try to fix it. Hmm care to clarify what is obsolete or broken after this series? Not after this series, was broken/obsolete already before. A couple of omap2/omap3 specific clock files still remain under mach-omap2, they are DVFS related. OMAP3 core dvfs support is currently completely unused (this could probably be removed, or shall we re-introduce the painful core dvfs at some point again?), and parts of the omap2 core dpll handling code should probably be re-written; or at least verified that it actually works properly. I can't test OMAP2 DVFS myself so don't dare to fiddle with it I could probably try to get some sort of DVFS test case to work on the board farm OMAP2 board I have access to though, I can investigate this. And I take it's not obsolete or broken because of this series? :) No, this series does not touch the above mentioned pieces of code, so this definitely should not break anything. :) -Tero Also, I just gave this branch a quick boot test and it seems to behave for me. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] clk: ti: clock driver code migration to drivers
The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590: Linux 4.2-rc2 (2015-07-12 15:10:30 -0700) are available in the git repository at: g...@github.com:t-kristo/linux-pm.git for-4.3/ti-clk-move for you to fetch changes up to 792ee6c3ecf813a4e702bdaceee249c722ab89f5: clk: ti: move low-level access and init code under clock driver (2015-07-14 09:26:34 +0300) Hi Mike, Stephen, This pull request contains the TI clock driver set to move the clock implementations under clock driver. Some small portions of the clock driver code still remain under mach-omap2 after this, it should be decided whether this code is now obsolete and should be deleted or should someone try to fix it. -Tero Tero Kristo (27): ARM: OMAP2+: clock: export driver API to setup/get clock features clk: ti: move generic OMAP DPLL implementation under drivers/clk clk: ti: move OMAP4+ DPLL implementation under drivers/clk clk: ti: move interface clock implementation under drivers/clk ARM: OMAP3: dpll3-m2: get rid of obsolete clksel access ARM: OMAP2+: clk: remove obsolete clksel support code ARM: OMAP2+: clock: remove clock_common_data.c file ARM: OMAP36xx: remove clock36xx.c/.h files clk: ti: autoidle: move generic autoidle handling code to clock driver clk: ti: move omap2_clk_enable_init_clocks under clock driver ARM: OMAP2+: clock: remove support for legacy mpurate command line param ARM: OMAP2+: clock: add support for clkdm ops to the low level clk ops ARM: OMAP2+: clock: add support for specific CM ops to ti_clk_ll_ops clk: ti: dpll: move omap3 DPLL functionality to clock driver ARM: OMAP3: clock: remove clock3xxx.c file ARM: OMAP2+: clock: remove clkdm_control static boolean from code clk: ti: dflt: move support for default gate clock to clock driver clk: ti: omap2430: move clock support code under clock driver clk: ti: clkdm: move clkdm gate clock support code to clock driver clk: ti: omap34xx: move omap34xx clock type support code to clock driver ARM: OMAP4: clock: remove clock44xx.h header clk: ti: am3517: move remaining am3517 clock support code to clock driver clk: ti: move some public definitions to private header ARM: OMAP2+: clock: remove dead definitions from the clock header file clk: ti: remove exported ll_ops struct, instead add an API for registration ARM: OMAP2+: clock: remove legacy omap2_clk_readl/writel APIs clk: ti: move low-level access and init code under clock driver arch/arm/mach-omap2/Makefile | 22 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c |7 +- arch/arm/mach-omap2/clkt_clksel.c | 466 -- arch/arm/mach-omap2/clkt_iclk.c| 68 -- arch/arm/mach-omap2/clock.c| 675 +--- arch/arm/mach-omap2/clock.h| 205 +- arch/arm/mach-omap2/clock2430.c| 57 -- arch/arm/mach-omap2/clock2xxx.c| 57 -- arch/arm/mach-omap2/clock34xx.c| 138 arch/arm/mach-omap2/clock34xx.h| 18 - arch/arm/mach-omap2/clock3517.c| 118 arch/arm/mach-omap2/clock3517.h| 14 - arch/arm/mach-omap2/clock36xx.c| 69 -- arch/arm/mach-omap2/clock36xx.h| 13 - arch/arm/mach-omap2/clock3xxx.c| 135 arch/arm/mach-omap2/clock44xx.h| 20 - arch/arm/mach-omap2/clock_common_data.c| 115 arch/arm/mach-omap2/io.c |3 +- drivers/clk/ti/Makefile| 17 +- drivers/clk/ti/apll.c |2 + drivers/clk/ti/autoidle.c | 121 +++- drivers/clk/ti/clk-2xxx.c |2 + drivers/clk/ti/clk-33xx.c |2 + drivers/clk/ti/clk-3xxx.c | 244 +++ drivers/clk/ti/clk-43xx.c |2 + drivers/clk/ti/clk-44xx.c |2 + drivers/clk/ti/clk-54xx.c |2 + drivers/clk/ti/clk-7xx.c |3 +- drivers/clk/ti/clk-816x.c |2 + drivers/clk/ti/clk.c | 145 - drivers/clk/ti/clkt_dflt.c | 316 + .../arm/mach-omap2 => drivers/clk/ti}/clkt_dpll.c | 27 +- drivers/clk/ti/clkt_iclk.c | 101 +++ drivers/clk/ti/clock.h | 113 drivers/clk/ti/clockdomain.c | 78 +++ {arch/arm/mach-om
Re: am33xx: ignore SYSBOOT 15:14 if board OSC is known
On 05/21/2015 07:26 PM, Nuno Gonçalves wrote: Currently the processor PLLs and Dividers are configured according to SYSBOOT levels during boot [1][2]. In the case of boards with expansion capabitliy, like the Beaglebone, the expansion board might touch this SYSBOOT pins a provide a wrong clock information. If we know the OSC on board as a fact (for example 24MHz for the Beaglebone), the SYSBOOT information can be safely ignored and the correct value hardcoded on the DT. The patch following works for am33xx. Anyway I have some reservations about this. Maybe overriding "sys_clkin_ck" with "virt_2400_ck" is a better solution? Regards, Nuno Sorry, seems this patch was buried in my mailbox, thanks for the offline ping. Anyway, the approach taken here is a horrible hack IMO, both for software and hardware. - Why would a cape want to reconfigure SYSBOOT pins in the first place? If this happens, it is bad hardware design. If you really need to re-use SYSBOOT pins for something, you should make sure their value is proper during reset, and only after reset is released set-up their alternative use. - Reconfiguring SYSBOOT pins will cause other problems in addition to kernel configuration being wrong; namely, SYSBOOT pins are also read by ROM code and certain initializations are done based on this. If you provide wrong value on SYSBOOT, the initial PLL config is going to be wrong also, which can cause various problems for the device. The status for this patch is NAK. -Tero [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/am33xx-clocks.dtsi#n11 [2] http://www.ti.com/lit/ug/spruh73l/spruh73l.pdf diff --git a/src/arm/am335x-bone-common.dtsi b/src/arm/am335x-bone-common.dtsi index 77067d6..1ddaa58 100644 --- a/src/arm/am335x-bone-common.dtsi +++ b/src/arm/am335x-bone-common.dtsi @@ -356,6 +356,10 @@ status = "okay"; }; +&sys_clkin_ck { + clocks = <&virt_2400_ck>, <&virt_2400_ck>, <&virt_2400_ck>, <&virt_2400_ck>; +}; + /* the cape manager */ / { bone_capemgr { -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 00/27] ARM: OMAP2+: clock code move under clk driver
On 06/04/2015 02:11 AM, Michael Turquette wrote: Quoting Tero Kristo (2015-06-03 05:33:46) On 05/28/2015 02:15 AM, Tony Lindgren wrote: * Tero Kristo [150527 11:32]: On 05/26/2015 07:39 PM, Felipe Balbi wrote: On Tue, May 26, 2015 at 09:32:16AM -0700, Tony Lindgren wrote: * Tony Lindgren [150526 09:08]: * Tero Kristo [150525 08:01]: Hi, As requested, posting v3 with somewhat changed diff parameters and diffstat attached. Just some minor Makefile changes compared to v2, these were discussed under that set. Set has been pushed to: - tree: https://github.com/t-kristo/linux-pm.git - branch: for-4.2/ti-clk-move Looks like this causes a build error for at least omap2 only .config: drivers/clk/ti/dpll3xxx.o:(.rodata+0x1c): multiple definition of `clkhwops_omap3_dpll' drivers/clk/ti/dpll.o:(.rodata+0x0): first defined here You may want to create a file selecting ARCH_OMAP2PLUS=y, then point KCONFIG_ALLCONFIG to that file for make randconfig. Then just build randconfigs :) Usually the issues like this are exposed within few randconfig builds, some take longer if the options have dependencies. alternatively, just clone the repository at [1] and use the example script provided in README.md. [1] https://github.com/felipebalbi/omap-seeds Ok, I pushed an updated branch named: for-4.2/ti-clk-move-v4 This definitely compiles with OMAP2 / OMAP3 / OMAP4 / OMAP5 / DRA7 / AM33xx / AM43xx only setups (tried it out.) Thanks yeah seems to work for me now. Regards, Tony Question to Mike / Stephen, any chance of getting this in during the 4.2 merge anymore seeing we are already at 4.1-rc6? I can send a pull request if yes. Otherwise I just wait until we are past the next merge. Hi Tero, I'd like more time for any regressions this introduces to be fixed, so lets push back to next merge window. The always-wrong-but-never-by-much crystal ball[0] predicts June 14. This is less than two weeks away, so the wait should be short. Hi Mike / Stephen, I am planning to send a pull-request out for this, but this set is going to cause some minor merge conflicts with the recent header file change patches from Stephen, and the determine rate prototype change from Boris. I can alternatively just ignore these issues and send these patches on top of rc2 and let you handle the conflicts within clk-tree, or cherry-pick some stable commits for the same if you like. Which way do you prefer? -Tero [0] http://phb-crystal-ball.org/ Thanks, Mike -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5] clk: change clk_ops' ->determine_rate() prototype
On 07/08/2015 03:57 AM, Stephen Boyd wrote: On 07/07, Boris Brezillon wrote: Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: Boris Brezillon CC: Jonathan Corbet CC: Tony Lindgren CC: Ralf Baechle CC: "Emilio López" CC: Maxime Ripard CC: Tero Kristo CC: Peter De Schrijver CC: Prashant Gaikwad CC: Stephen Warren CC: Thierry Reding CC: Alexandre Courbot CC: linux-...@vger.kernel.org CC: linux-ker...@vger.kernel.org CC: linux-arm-ker...@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-m...@linux-mips.org CC: linux-te...@vger.kernel.org --- I'll throw this patch into -next now to see if any other problems shake out. I'm hoping we get some more acks though, so it'll be on it's own branch and become immutable in a week or so. One question below. Gave this patch a quick test on the boards I have access to, and didn't notice any obvious problems. So, for the TI parts: Acked-by: Tero Kristo diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 616f5ae..9e69f34 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -99,33 +99,33 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, parent_rate = __clk_get_rate(parent); - tmp_rate = rate_ops->round_rate(rate_hw, rate, + tmp_rate = rate_ops->round_rate(rate_hw, req->rate, &parent_rate); if (tmp_rate < 0) continue; - rate_diff = abs(rate - tmp_rate); + rate_diff = abs(req->rate - tmp_rate); - if (!rate_diff || !*best_parent_p + if (!rate_diff || !req->best_parent_hw || best_rate_diff > rate_diff) { - *best_parent_p = __clk_get_hw(parent); - *best_parent_rate = parent_rate; + req->best_parent_hw = __clk_get_hw(parent); + req->best_parent_rate = parent_rate; best_rate_diff = rate_diff; best_rate = tmp_rate; } if (!rate_diff) - return rate; + return 0; } - return best_rate; + req->rate = best_rate; + return 0; } else if (mux_hw && mux_ops && mux_ops->determine_rate) { __clk_hw_set_clk(mux_hw, hw); - return mux_ops->determine_rate(mux_hw, rate, min_rate, - max_rate, best_parent_rate, - best_parent_p); + return mux_ops->determine_rate(mux_hw, req); } else { pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n"); + req->rate = 0; return 0; Shouldn't this return an error now? And then assigning req->rate wouldn't be necessary. Sorry I must have missed this last round. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/5] Add support for PWMSS on DRA7
On 07/06/2015 09:11 AM, Vignesh R wrote: On Wednesday 03 June 2015 05:21 PM, Vignesh R wrote: Hi, This patch series adds support for PWMSS on DRA7. The IP is same as that present in AM33XX and AM43XX. The first patch changes clock domain in which PWMSS is present (l4per2_7xx_clkdm) to SW_WKUP. This is because legacy IPs like PWM does'nt support HW_AUTO prorperly. Hence, switch clock domain to SW_WKUP. This is based on the input from the hardware team. The rest of the patches add hwmod and dt entries and enable PWMSS on DRA7 based SoCs. Gentle ping... Patches 1-4 look good to me, not going to try to review patch 5 as I have no clue about PWM driver itself. So, for 1-4: Acked-by: Tero Kristo Some of the patches cause trivial merge conflicts with 4.2-rc1 though. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/6] ARM: AM43xx: Add the PRM IRQ register offsets
On 06/22/2015 09:22 AM, Keerthy wrote: Add the PRM IRQ register offsets. This patch doesn't apply cleanly to 4.2-rc1. -Tero Signed-off-by: Keerthy --- arch/arm/mach-omap2/prcm43xx.h | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index d026199..ec1ac5c 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -25,6 +25,10 @@ #define AM43XX_PRM_WKUP_INST 0x2000 #define AM43XX_PRM_DEVICE_INST0x4000 +/* PRM_IRQ offsets */ +#define AM43XX_PRM_IRQSTATUS_MPU_OFFSET0x0004 +#define AM43XX_PRM_IRQENABLE_MPU_OFFSET0x0008 + /* RM RSTCTRL offsets */ #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 @@ -146,4 +150,5 @@ #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET0x04a0 #define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET0x0068 #define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET0x0070 +#define AM43XX_PRM_IO_PMCTRL_OFFSET0x0024 #endif -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/6] ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 register offsets
On 06/22/2015 09:22 AM, Keerthy wrote: The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are hardcoded. This makes it difficult to reuse the code for single core SoCs like AM437x. Single core vs. having two sets of IRQENABLE / IRQSTATUS registers do not have any relation to each other. OMAP4+ has two IRQ registers, because the number of IRQ events is so large it does not fit into single register. Thus, the commit message is somewhat misleading, please fix. Hence making it part of omap_prcm_irq_setup structure so that case of single set of IRQ* registers can be handled generically. Signed-off-by: Keerthy --- arch/arm/mach-omap2/prcm-common.h | 8 arch/arm/mach-omap2/prm3xxx.c | 20 +- arch/arm/mach-omap2/prm44xx.c | 43 +-- arch/arm/mach-omap2/prm_common.c | 5 ++--- 4 files changed, 39 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 2e60406..99447e7 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -470,8 +470,8 @@ struct omap_prcm_irq { /** * struct omap_prcm_irq_setup - PRCM interrupt controller details - * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register - * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register + * @ack: PRM register offsets for the PRM_IRQSTATUS_MPU registers + * @mask: PRM register offsets for the PRM_IRQENABLE_MPU registers * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers * @nr_irqs: number of entries in the @irqs array * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) @@ -492,8 +492,8 @@ struct omap_prcm_irq { * specified in static initializers. */ struct omap_prcm_irq_setup { - u16 ack; - u16 mask; + u16 ack[2]; + u16 mask[2]; You don't really need two pairs of offsets; in generic case, if we have two IRQ registers, the offset between the two is 4, as used elsewhere in the code. By keeping the previous struct layout, you can save a few bytes of memory, and don't need to touch the omap3 code all over the place either. u16 pm_ctrl; u8 nr_regs; u8 nr_irqs; diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 62680aa..56649b0 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c No need to touch the OMAP3 code, as the offsets are always the default ones. diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 8149e5a..20b547a 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -43,8 +43,10 @@ static const struct omap_prcm_irq omap4_prcm_irqs[] = { }; static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { - .ack= OMAP4_PRM_IRQSTATUS_MPU_OFFSET, - .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, + .ack[0] = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, + .mask[0]= OMAP4_PRM_IRQENABLE_MPU_OFFSET, + .ack[1] = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET, + .mask[1]= OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, I think you should just keep the single IRQENABLE / IRQSTATUS definitions in place, and use +4 addressing where applicable. Having an array of the ack + mask definitions is kind of ugly. .pm_ctrl= OMAP4_PRM_IO_PMCTRL_OFFSET, .nr_regs= 2, .irqs = omap4_prcm_irqs, @@ -217,11 +219,11 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs) */ static void omap44xx_prm_read_pending_irqs(unsigned long *events) { - events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, - OMAP4_PRM_IRQSTATUS_MPU_OFFSET); + int i; - events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, - OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); + for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) + events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask[i], + omap4_prcm_irq_setup.ack[i]); ... change to mask + i * 4 / ack + i * 4. } /** @@ -251,17 +253,16 @@ static void omap44xx_prm_ocp_barrier(void) */ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) { - saved_mask[0] = - omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_OFFSET); - saved_mask[1] = - omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); + int i; - omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, -OMAP4_PRM_IRQENABLE_MPU_OFFSET); - omap4_prm_write_
Re: [PATCH] pinctrl: single: dra7: remove PCS_QUIRK_SHARED_IRQ
On 07/06/2015 06:25 PM, Tony Lindgren wrote: * Grygorii Strashko [150706 08:14]: On DRA7 there is one pinctrl domain (dra7_pmx_core) and PRCM wake-up IRQ is not shared, so remove quirk. Cc: Nishanth Menon Cc: Tony Lindgren Fixes: 31320beaa3d3 ('pinctrl: single: Add DRA7 pinctrl compatibility') Signed-off-by: Grygorii Strashko --- drivers/pinctrl/pinctrl-single.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 0b8d480..9b24b343 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1983,7 +1983,6 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = { }; static const struct pcs_soc_data pinctrl_single_dra7 = { - .flags = PCS_QUIRK_SHARED_IRQ, .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ }; Tero, care to take a look at this one and ack if OK? Looks fine to me. Acked-by: Tero Kristo Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] Add timer_32k_ck alias for dm816x in clk-816x.c
Subject should have clk: ti: in the beginning. On 06/15/2015 09:54 PM, Brian Hutchinson wrote: dm816x needs timer_32k_ck alias to use dual mode timers in dmtimers.c This adds a timer_32k_ck alias for sys_32_ck in clk-816x.c so omap_dm_timer_set_source will work for dm816x. Use checkpatch please. Or use a mailer that doesn't convert tabs to spaces. This patch seems to have something else that is strange also. Cc: Paul Walmsley mailto:p...@pwsan.com>> Cc: Tero Kristo mailto:t-kri...@ti.com>> Cc: Tony Lindgren mailto:t...@atomide.com>> Signed-off-by: Brian Hutchinson mailto:b.hutch...@gmail.com>> --- drivers/clk/ti/clk-816x.c_orig 2015-06-15 13:46:53.058128064 -0400 +++ drivers/clk/ti/clk-816x.c 2015-06-15 13:47:28.966306123 -0400 What is that _orig here? Are you using git to generate the patches? -Tero @@ -18,6 +18,7 @@ static struct ti_dt_clk dm816x_clks[] = DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "mpu_ck", "mpu_ck"), DT_CLK(NULL, "timer1_fck", "timer1_fck"), DT_CLK(NULL, "timer2_fck", "timer2_fck"), -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] add pwm capability to dm816x
On 06/15/2015 09:36 PM, Brian Hutchinson wrote: Clocks 4-7 are capable of PWM output on dm816x. This adds the pwm capability to those timers. Use checkpatch pls, I see lots of whitespace errors. Also, I don't think Mike / Stephen care about this patch, as it is against omap hwmod data only. -Tero Cc: Paul Walmsley mailto:p...@pwsan.com>> Cc: Tero Kristo mailto:t-kri...@ti.com>> Cc: Tony Lindgren mailto:t...@atomide.com>> Signed-off-by: Brian Hutchinson mailto:b.hutch...@gmail.com><mailto:t...@atomide.com>> --- arch/arm/mach-omap2/omap_hwmod_81xx_data.c_orig 2015-06-15 13:20:43.174343431 -0400 +++ arch/arm/mach-omap2/omap_hwmod_81xx_data.c 2015-06-15 13:34:51.770551392 -0400 @@ -546,6 +546,14 @@ static struct omap_timer_capability_dev_ .timer_capability = OMAP_TIMER_ALWON, }; +/* pwm timers dev attribute. + * timers 4-7 may be used for PWM output - see datasheet timer terminal + * functions table + */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_HAS_PWM, +}; + static struct omap_hwmod dm816x_timer1_hwmod = { .name = "timer1", .clkdm_name = "alwon_l3s_clkdm", @@ -619,7 +627,7 @@ static struct omap_hwmod dm816x_timer4_h .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, + .dev_attr = &capability_pwm_dev_attr, .class = &dm816x_timer_hwmod_class, }; @@ -640,7 +648,7 @@ static struct omap_hwmod dm816x_timer5_h .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, + .dev_attr = &capability_pwm_dev_attr, .class = &dm816x_timer_hwmod_class, }; @@ -661,7 +669,7 @@ static struct omap_hwmod dm816x_timer6_h .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, + .dev_attr = &capability_pwm_dev_attr, .class = &dm816x_timer_hwmod_class, }; @@ -682,7 +690,7 @@ static struct omap_hwmod dm816x_timer7_h .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, + .dev_attr = &capability_pwm_dev_attr, .class = &dm816x_timer_hwmod_class, }; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 00/27] ARM: OMAP2+: clock code move under clk driver
On 06/04/2015 02:11 AM, Michael Turquette wrote: Quoting Tero Kristo (2015-06-03 05:33:46) On 05/28/2015 02:15 AM, Tony Lindgren wrote: * Tero Kristo [150527 11:32]: On 05/26/2015 07:39 PM, Felipe Balbi wrote: On Tue, May 26, 2015 at 09:32:16AM -0700, Tony Lindgren wrote: * Tony Lindgren [150526 09:08]: * Tero Kristo [150525 08:01]: Hi, As requested, posting v3 with somewhat changed diff parameters and diffstat attached. Just some minor Makefile changes compared to v2, these were discussed under that set. Set has been pushed to: - tree: https://github.com/t-kristo/linux-pm.git - branch: for-4.2/ti-clk-move Looks like this causes a build error for at least omap2 only .config: drivers/clk/ti/dpll3xxx.o:(.rodata+0x1c): multiple definition of `clkhwops_omap3_dpll' drivers/clk/ti/dpll.o:(.rodata+0x0): first defined here You may want to create a file selecting ARCH_OMAP2PLUS=y, then point KCONFIG_ALLCONFIG to that file for make randconfig. Then just build randconfigs :) Usually the issues like this are exposed within few randconfig builds, some take longer if the options have dependencies. alternatively, just clone the repository at [1] and use the example script provided in README.md. [1] https://github.com/felipebalbi/omap-seeds Ok, I pushed an updated branch named: for-4.2/ti-clk-move-v4 This definitely compiles with OMAP2 / OMAP3 / OMAP4 / OMAP5 / DRA7 / AM33xx / AM43xx only setups (tried it out.) Thanks yeah seems to work for me now. Regards, Tony Question to Mike / Stephen, any chance of getting this in during the 4.2 merge anymore seeing we are already at 4.1-rc6? I can send a pull request if yes. Otherwise I just wait until we are past the next merge. Hi Tero, I'd like more time for any regressions this introduces to be fixed, so lets push back to next merge window. The always-wrong-but-never-by-much crystal ball[0] predicts June 14. This is less than two weeks away, so the wait should be short. Ok, I'll rebase this against rc1 and send a pull-request once we have it. -Tero [0] http://phb-crystal-ball.org/ Thanks, Mike -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 00/27] ARM: OMAP2+: clock code move under clk driver
On 05/28/2015 02:15 AM, Tony Lindgren wrote: * Tero Kristo [150527 11:32]: On 05/26/2015 07:39 PM, Felipe Balbi wrote: On Tue, May 26, 2015 at 09:32:16AM -0700, Tony Lindgren wrote: * Tony Lindgren [150526 09:08]: * Tero Kristo [150525 08:01]: Hi, As requested, posting v3 with somewhat changed diff parameters and diffstat attached. Just some minor Makefile changes compared to v2, these were discussed under that set. Set has been pushed to: - tree: https://github.com/t-kristo/linux-pm.git - branch: for-4.2/ti-clk-move Looks like this causes a build error for at least omap2 only .config: drivers/clk/ti/dpll3xxx.o:(.rodata+0x1c): multiple definition of `clkhwops_omap3_dpll' drivers/clk/ti/dpll.o:(.rodata+0x0): first defined here You may want to create a file selecting ARCH_OMAP2PLUS=y, then point KCONFIG_ALLCONFIG to that file for make randconfig. Then just build randconfigs :) Usually the issues like this are exposed within few randconfig builds, some take longer if the options have dependencies. alternatively, just clone the repository at [1] and use the example script provided in README.md. [1] https://github.com/felipebalbi/omap-seeds Ok, I pushed an updated branch named: for-4.2/ti-clk-move-v4 This definitely compiles with OMAP2 / OMAP3 / OMAP4 / OMAP5 / DRA7 / AM33xx / AM43xx only setups (tried it out.) Thanks yeah seems to work for me now. Regards, Tony Question to Mike / Stephen, any chance of getting this in during the 4.2 merge anymore seeing we are already at 4.1-rc6? I can send a pull request if yes. Otherwise I just wait until we are past the next merge. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 01/27] ARM: OMAP2+: clock: export driver API to setup/get clock features
On 05/29/2015 01:04 AM, Stephen Boyd wrote: On 05/25, Tero Kristo wrote: + +/** + * ti_clk_get_features - get clock driver features flags + * + * Get TI clock driver features description. Returns a pointer + * to the current feature setup. + */ +struct ti_clk_features *ti_clk_get_features(void) const? Ok changed locally in the branch. -Tero +{ + return &ti_clk_features; +} #endif -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/5] ARM: dts: DRA7: Add TBCLK for PWMSS
On 06/01/2015 02:53 PM, Vignesh R wrote: tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux clock to control ehrpwm tbclk. Care to add TRM reference here? -Tero Signed-off-by: Vignesh R --- arch/arm/boot/dts/dra7.dtsi | 5 + arch/arm/boot/dts/dra7xx-clocks.dtsi | 26 ++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f03a091cd076..387c76ca41f9 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -131,6 +131,11 @@ regulator-max-microvolt = <300>; }; }; + + scm_conf_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; }; dra7_pmx_core: pinmux@1400 { diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3b933f74d000..92452d61cf58 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -2136,3 +2136,29 @@ clocks = <&dpll_usb_ck>; }; }; + +&scm_conf_clocks { + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <20>; + reg = <0x0558>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <21>; + reg = <0x0558>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <22>; + reg = <0x0558>; + }; +}; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html