javier Martin javier.mar...@vista-silicon.com writes:
On 2 September 2011 19:14, Kevin Hilman khil...@ti.com wrote:
javier Martin javier.mar...@vista-silicon.com writes:
On 2 September 2011 08:05, Jarkko Nikula jarkko.nik...@bitmer.com wrote:
Other usual things to check that display is off
On 2 September 2011 19:14, Kevin Hilman khil...@ti.com wrote:
javier Martin javier.mar...@vista-silicon.com writes:
On 2 September 2011 08:05, Jarkko Nikula jarkko.nik...@bitmer.com wrote:
Other usual things to check that display is off (echo 1
/sys/class/graphics/fb0/blank) and no cable to
On 09/01/2011 08:46 PM, Kevin Hilman wrote:
javier Martinjavier.mar...@vista-silicon.com writes:
Hi Kevin,
thanks for your help.
CPU is staying in C0 probably because UARTs are not being idled, so SoC
cannot hit deeper idle states. Try the following at the command line to
to enable UART
On 2 September 2011 08:05, Jarkko Nikula jarkko.nik...@bitmer.com wrote:
Other usual things to check that display is off (echo 1
/sys/class/graphics/fb0/blank) and no cable to musb/otg port.
Haven't tried myself with recent kernel but does EHCI and hub on XM let to
idle cpu at all? At least
javier Martin javier.mar...@vista-silicon.com writes:
On 2 September 2011 08:05, Jarkko Nikula jarkko.nik...@bitmer.com wrote:
Other usual things to check that display is off (echo 1
/sys/class/graphics/fb0/blank) and no cable to musb/otg port.
Haven't tried myself with recent kernel but
javier Martin javier.mar...@vista-silicon.com writes:
I am trying to enable cpuidle and cpufreq support in latest stable
kernel (3.0.4) in the Beagleboard xM.
OMAP CPUfreq driver is still not in mailine. I plan to rectify that
(finally) for v3.2. In the mean time, feel free to try the
Hi Kevin,
thanks for your help.
CPU is staying in C0 probably because UARTs are not being idled, so SoC
cannot hit deeper idle states. Try the following at the command line to
to enable UART idle timeouts, so the SoC can attempt idle after the
timeout period
# UART timeouts: omap-serial
javier Martin javier.mar...@vista-silicon.com writes:
Hi Kevin,
thanks for your help.
CPU is staying in C0 probably because UARTs are not being idled, so SoC
cannot hit deeper idle states. Try the following at the command line to
to enable UART idle timeouts, so the SoC can attempt idle
