On Thu, Dec 13, 2012 at 07:21:30PM +, Jon Hunter wrote:
On 12/13/2012 11:41 AM, Will Deacon wrote:
On Wed, Dec 12, 2012 at 09:43:05PM +, Jon Hunter wrote:
Adds a device-tree binding for the ARM Cross Trigger Interface (CTI).
The ARM Cross Trigger Interface provides a way to route
On Fri, Dec 14, 2012 at 09:26:37PM +, Jon Hunter wrote:
Add PMU nodes for OMAP2, OMAP3 and OMAP4460 devices.
Please note that the node for OMAP4460 has been placed in a separate
header file for OMAP4460, because the node is not compatible with
OMAP4430.
Signed-off-by: Jon Hunter
[...]
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 01ce462..f7de9eb 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -39,6 +39,7 @@
#include omap_device.h
#include gpmc.h
#include gpmc-nand.h
+#include gpmc-onenand.h
+struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
+ const char *phandle, u8 index)
+{
+ struct usb_phy *phy = NULL, **ptr;
+ unsigned long flags;
+ struct device_node *node;
+
+ if (!dev-of_node) {
+ dev_dbg(dev, device does not have a
On Fri, Jan 25, 2013 at 10:23:57AM +, Kishon Vijay Abraham I wrote:
Added a new driver for the usb part of control module. This has an API
to power on the USB2 phy and an API to write to the mailbox depending on
whether MUSB has to act in host mode or in device mode.
Writing to control
[...]
+OMAP CONTROL USB
+
+Required properties:
+ - compatible: Should be ti,omap-control-usb
+ - reg : Address and length of the register set for the device. It
contains
+ the address of control_dev_conf and otghs_control or
phy_power_usb
Could you not use '-'
ezequiel.gar...@free-electrons.com
---
Changes from v2:
* Remove unneeded of_node_put() as reported by Mark Rutland
Changes from v1:
* Fix typo in Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
.../devicetree/bindings/mtd/gpmc-onenand.txt | 43 +++
arch/arm/mach
On Fri, Jan 25, 2013 at 02:59:28PM +, Felipe Balbi wrote:
Hi,
On Fri, Jan 25, 2013 at 12:29:43PM +, Mark Rutland wrote:
+ depending upon omap4 or omap5.
+ - reg-names: The names of the register addresses corresponding to
the registers
+ filled in reg
On Fri, Jan 25, 2013 at 04:23:46PM +, Felipe Balbi wrote:
Hi,
On Fri, Jan 25, 2013 at 04:14:02PM +, Mark Rutland wrote:
On Fri, Jan 25, 2013 at 02:59:28PM +, Felipe Balbi wrote:
Hi,
On Fri, Jan 25, 2013 at 12:29:43PM +, Mark Rutland wrote:
+ depending upon
On Fri, Jan 25, 2013 at 06:11:28PM +, Ezequiel Garcia wrote:
Hi Mark,
First of all: thanks for reviewing.
On Fri, Jan 25, 2013 at 12:56 PM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
I have a couple more comments after looking though this a bit more
thoroughly.
On Fri
On Mon, Feb 04, 2013 at 03:58:55PM +, Roger Quadros wrote:
Allows the OMAP EHCI controller to be specified via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
---
.../devicetree/bindings/usb/omap-ehci.txt | 34 ++
drivers/usb/host/ehci-omap.c
Hi,
I have a few comments on the binding and the way it's parsed.
On Mon, Feb 04, 2013 at 03:58:56PM +, Roger Quadros wrote:
Allows the OMAP HS USB host controller to be specified
via device tree.
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
[...]
+
+- single_ulpi_bypass: Must be present if the controller contains a single
+ ULPI bypass control bit. e.g. OMAP3 silicon = ES2.1
Again it would be nicer to have '-' rather than '_' here. It might be worth
prefixing this ti,.
Is prefixing with ti really required? how does
Hello,
I have a couple of minor comments.
On Thu, Feb 07, 2013 at 02:11:37PM +, Anil Kumar wrote:
DevKit8000 is a beagle board clone from Timll, sold by
armkits.com. The DevKit8000 has RS232 serial port, LCD, DVI-D,
S-Video, Ethernet, SD/MMC, keyboard, camera, SPI, I2C, USB and
JTAG
Hi,
I have a few comments on the binding and the way it's parsed.
On Sat, Feb 09, 2013 at 08:44:27PM +, Javier Martinez Canillas wrote:
This patch adds a helper function to parse a device node that
contains all the properties needed to initialize an smsc911x
device connected to an OMAP
Hello,
On Thu, Feb 07, 2013 at 04:02:41PM +, Roger Quadros wrote:
The PHY clock, clock rate, VCC regulator and RESET regulator
can now be provided via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
---
On Thu, Feb 07, 2013 at 04:02:47PM +, Roger Quadros wrote:
Allows the OHCI controller found in OMAP3 and later chips to
be specified via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
Acked-by: Alan Stern st...@rowland.harvard.edu
---
On Thu, Feb 07, 2013 at 04:02:48PM +, Roger Quadros wrote:
Allows the OMAP EHCI controller to be specified via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
Acked-by: Alan Stern st...@rowland.harvard.edu
---
.../devicetree/bindings/usb/omap-ehci.txt | 34
On Thu, Feb 07, 2013 at 04:02:49PM +, Roger Quadros wrote:
Allows the OMAP HS USB host controller to be specified
via device tree.
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
.../devicetree/bindings/mfd/omap-usb-host.txt | 80 ++
Hi Roger,
On Mon, Feb 11, 2013 at 03:14:26PM +, Roger Quadros wrote:
On 02/11/2013 01:40 PM, Mark Rutland wrote:
Hello,
On Thu, Feb 07, 2013 at 04:02:41PM +, Roger Quadros wrote:
The PHY clock, clock rate, VCC regulator and RESET regulator
can now be provided via device tree
+Required properties:
+
+- compatible: should be ti,ohci-omap3
+- reg: should contain one register range i.e. start and length
+- interrupt-parent: phandle to the interrupt controller
I'm not sure that needs to be documented as a required property. It's a
standard property, and if
Hello,
I have a few comments on the devicetree binding and the way it's parsed.
+static const struct of_device_id dbx500_mailbox_match[] = {
+ { .compatible = stericsson,db8500-mailbox,
+ .data = (void *)db8500_mboxes,
+ },
+ { .compatible =
On Tue, Feb 12, 2013 at 08:01:05PM +, Loic PALLARDY wrote:
Hi Mark,
Thanks for your comments.
On 02/12/2013 11:39 AM, Mark Rutland wrote:
Hello,
I have a few comments on the devicetree binding and the way it's parsed.
+static const struct of_device_id dbx500_mailbox_match
Hi Santosh,
On Wed, Mar 13, 2013 at 09:28:22AM +, Santosh Shilimkar wrote:
(Forgot to CC Thomas)
On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar wrote:
With recent arm broadcast time clean-up from Mark Rutland, the dummy
broadcast device is always registered with timer
On Wed, Mar 13, 2013 at 11:24:01AM +, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 03:46 PM, Mark Rutland wrote:
Hi Santosh,
On Wed, Mar 13, 2013 at 09:28:22AM +, Santosh Shilimkar wrote:
(Forgot to CC Thomas)
On Wednesday 13 March 2013 02:36 PM, Santosh Shilimkar
On Wed, Mar 13, 2013 at 03:44:03PM +, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 05:55 PM, Mark Rutland wrote:
On Wed, Mar 13, 2013 at 11:24:01AM +, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 03:46 PM, Mark Rutland wrote:
Hi Santosh,
[..]
Is the problem
On Thu, Mar 14, 2013 at 07:45:14AM +, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 09:48 PM, Mark Rutland wrote:
On Wed, Mar 13, 2013 at 03:44:03PM +, Santosh Shilimkar wrote:
On Wednesday 13 March 2013 05:55 PM, Mark Rutland wrote:
On Wed, Mar 13, 2013 at 11:24:01AM +
Hi Rob,
(adding Marc to Cc as he may have comments).
On Wed, Mar 20, 2013 at 10:34:35PM +, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This converts arm and arm64 to use CLKSRC_OF DT based initialization for
the arch timer. A new function arch_timer_arch_init is added
On Tue, Jun 25, 2013 at 09:35:30AM +0100, Luciano Coelho wrote:
Add device tree bindings documentation for the TI WiLink modules.
Currently only the WLAN part of the WiLink6, WiLink7 and WiLink8
modules is supported.
Signed-off-by: Luciano Coelho coe...@ti.com
---
I created a new
On Fri, Jun 28, 2013 at 10:53:35AM +0100, Luciano Coelho wrote:
On Fri, 2013-06-28 at 10:38 +0100, Mark Rutland wrote:
On Tue, Jun 25, 2013 at 09:35:30AM +0100, Luciano Coelho wrote:
+Optional properties:
+
+
+- refclock: the internal WLAN reference clock
[resending with the correct address for Mike Turquette]
On Fri, Jun 28, 2013 at 10:53:35AM +0100, Luciano Coelho wrote:
On Fri, 2013-06-28 at 10:38 +0100, Mark Rutland wrote:
On Tue, Jun 25, 2013 at 09:35:30AM +0100, Luciano Coelho wrote:
+Optional properties
[resending again with the doubly corrected address for Mike Turquette,
apologies for the spam]
On Fri, Jun 28, 2013 at 10:53:35AM +0100, Luciano Coelho wrote:
On Fri, 2013-06-28 at 10:38 +0100, Mark Rutland wrote:
On Tue, Jun 25, 2013 at 09:35:30AM +0100, Luciano Coelho wrote:
+Optional
On Tue, Jul 30, 2013 at 06:05:52AM +0100, Gururaja Hebbar wrote:
Hi,
On 7/3/2013 2:17 PM, Hebbar Gururaja wrote:
Since AM33xx RTC IP has RTC_IRQWAKEEN to support Alarm Wake-up.
Update the rtc compatible property to ti,am3352-rtc to enable handling
of this feature inside rtc-omap
On Tue, Jul 30, 2013 at 05:21:14PM +0100, Sekhar Nori wrote:
On 7/30/2013 8:25 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 06:05:52AM +0100, Gururaja Hebbar wrote:
Hi,
On 7/3/2013 2:17 PM, Hebbar Gururaja wrote:
Since AM33xx RTC IP has RTC_IRQWAKEEN to support Alarm Wake-up
On Fri, Aug 02, 2013 at 12:07:36PM +0100, Gururaja Hebbar wrote:
On 8/1/2013 10:35 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 05:21:14PM +0100, Sekhar Nori wrote:
On 7/30/2013 8:25 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 06:05:52AM +0100, Gururaja Hebbar wrote:
Hi,
On 7/3
On Fri, Aug 02, 2013 at 12:48:07PM +0100, Gururaja Hebbar wrote:
On 8/2/2013 4:50 PM, Mark Rutland wrote:
On Fri, Aug 02, 2013 at 12:07:36PM +0100, Gururaja Hebbar wrote:
On 8/1/2013 10:35 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 05:21:14PM +0100, Sekhar Nori wrote:
On 7/30/2013 8
On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
drivers/usb/phy/Kconfig| 11 +
On Tue, Aug 06, 2013 at 12:53:11PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
What does the glue layer do? Is it an actual piece of hardware, or
just some platform-specific code?
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
that
the #interrupt-cells property should be 2.
I take it there are no device nodes for which any of these nodes are an
interrupt parent (which would need to be updated)?
If so:
Acked-by: Mark Rutland mark.rutl...@arm.com
Thanks,
Mark.
Signed-off-by: Lars Poeschel poesc...@lemonage.de
On Tue, Aug 06, 2013 at 03:36:33PM +0100, Ivan T. Ivanov wrote:
Hi,
On Tue, 2013-08-06 at 15:03 +0100, Mark Rutland wrote:
On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
On Fri, Jul 26, 2013 at 07:59:15AM +0100, Lokesh Vutla wrote:
Add support for the OMAP5 version of the SHAM module
that is present on OMAP5 and AM43xx SoCs.
This module is very simialar to OMAP4 version of SHAM module,
and adds SHA384 SHA512 hardware-accelerated hash functions to it.
To
{
compatible = arm,cortex-a9;
+ device_type = cpu;
+ reg = 0;
};
};
This looks sane to me:
Acked-by: Mark Rutland mark.rutl...@arm.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message
On Mon, Aug 05, 2013 at 06:08:45AM +0100, Afzal Mohammed wrote:
Hi Muguthan,
On Saturday 03 August 2013 05:19 PM, Mugunthan V N wrote:
On 8/2/2013 7:16 PM, Afzal Mohammed wrote:
+ mac: ethernet@4a10 {
+ compatible = ti,am4372-cpsw,ti,cpsw;
On Tue, Jul 30, 2013 at 12:25:46PM +0100, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+
Hi,
On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/dpll.txt | 70 +++
On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
This node adds support for a clock node which allows control to the
clockdomain enable / disable.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/gate.txt | 41
On Fri, Aug 02, 2013 at 05:25:35PM +0100, Tero Kristo wrote:
From: Keerthy j-keer...@ti.com
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital
On Fri, Aug 02, 2013 at 05:25:37PM +0100, Tero Kristo wrote:
Adding set-rate-parent to clock node now allows a node to forward
clk_set_rate request to its parent clock.
Why do you need this?
Is this a description of the hardware, or configuration for Linux?
It feels like the latter, which
On Fri, Aug 02, 2013 at 05:25:41PM +0100, Tero Kristo wrote:
OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
[Adding Mike Turquette and dt maintainers to Cc]
On Tue, Jul 23, 2013 at 07:24:38AM +0100, Rajendra Nayak wrote:
With clocks for OMAP moving to DT, its now possible to pass all optional clock
data for each device from DT instead of having it in hwmod.
Signed-off-by: Rajendra Nayak
[Adding Mike Turquette and dt maintainers]
On Wed, Aug 14, 2013 at 02:39:44PM +0100, Nishanth Menon wrote:
On 08/14/2013 08:20 AM, Rajendra Nayak wrote:
On Wednesday 14 August 2013 06:18 PM, Nishanth Menon wrote:
Hi Rajendra,
On Tue, Jul 23, 2013 at 1:24 AM, Rajendra Nayak rna...@ti.com
On Wed, Aug 14, 2013 at 02:54:57PM +0100, Rajendra Nayak wrote:
On Wednesday 14 August 2013 07:15 PM, Mark Rutland wrote:
[Adding Mike Turquette and dt maintainers to Cc]
On Tue, Jul 23, 2013 at 07:24:38AM +0100, Rajendra Nayak wrote:
With clocks for OMAP moving to DT, its now possible
On Wed, Aug 14, 2013 at 02:58:25PM +0100, Nishanth Menon wrote:
On 08/14/2013 08:49 AM, Mark Rutland wrote:
[Adding Mike Turquette and dt maintainers]
On Wed, Aug 14, 2013 at 02:39:44PM +0100, Nishanth Menon wrote:
On 08/14/2013 08:20 AM, Rajendra Nayak wrote:
On Wednesday 14 August
On Wed, Aug 14, 2013 at 03:05:25PM +0100, Rajendra Nayak wrote:
On Wednesday 14 August 2013 07:28 PM, Nishanth Menon wrote:
On 08/14/2013 08:49 AM, Mark Rutland wrote:
[Adding Mike Turquette and dt maintainers]
On Wed, Aug 14, 2013 at 02:39:44PM +0100, Nishanth Menon wrote:
On 08/14
Hi,
apologies for the late reply.
On Thu, Jul 25, 2013 at 02:26:51PM +0100, Oleksandr Kozaruk wrote:
Hello,
v8 - removed unused test channels completely, removed die
temperature channels, as it is not known how to convert ADC code
to temperature. There if formula for twl6030, but
Hi Benoit,
On Fri, Aug 16, 2013 at 03:15:57PM +0100, Benoit Cousson wrote:
Hi Gururaja,
On 16/08/2013 13:36, Hebbar, Gururaja wrote:
The syntax of compatible property in DT is to mention the Most specific
match to most generic match.
Since AM335x is the platform with latest IP
On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
On 08/13/2013 01:50 PM, Mark Rutland wrote:
Hi,
On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off
On Mon, Aug 19, 2013 at 02:42:05PM +0100, Tero Kristo wrote:
On 08/13/2013 02:04 PM, Mark Rutland wrote:
On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
This node adds support for a clock node which allows control to the
clockdomain enable / disable.
Signed-off-by: Tero
On Fri, Aug 16, 2013 at 07:12:46PM +0100, Benoit Cousson wrote:
Hi Mark,
On 16/08/2013 19:20, Mark Rutland wrote:
Hi Benoit,
On Fri, Aug 16, 2013 at 03:15:57PM +0100, Benoit Cousson wrote:
Hi Gururaja,
On 16/08/2013 13:36, Hebbar, Gururaja wrote:
The syntax of compatible property
On Mon, Aug 19, 2013 at 03:43:15PM +0100, Tero Kristo wrote:
On 08/19/2013 05:29 PM, Mark Rutland wrote:
On Mon, Aug 19, 2013 at 02:42:05PM +0100, Tero Kristo wrote:
On 08/13/2013 02:04 PM, Mark Rutland wrote:
On Fri, Aug 02, 2013 at 05:25:24PM +0100, Tero Kristo wrote:
This node adds
On Mon, Aug 19, 2013 at 04:09:37PM +0100, Tero Kristo wrote:
On 08/19/2013 05:18 PM, Mark Rutland wrote:
On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
On 08/13/2013 01:50 PM, Mark Rutland wrote:
Hi,
On Fri, Aug 02, 2013 at 05:25:21PM +0100, Tero Kristo wrote:
The OMAP
On Wed, Jul 17, 2013 at 05:23:41PM +0100, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
Add the generic AM33XX SHAM module's device tree data and
enable it for the am335x-evm, am335x-evmsk, and am335x-bone
platforms. Also add Documentation file describing the data
for the
Hi,
I have a few comments, mostly on the DT binding and parsing.
diff --git a/Documentation/devicetree/bindings/arm/omap/irq-crossbar.txt
b/Documentation/devicetree/bindings/arm/omap/irq-crossbar.txt
new file mode 100644
index 000..5d465cf
--- /dev/null
+++
On Wed, Sep 25, 2013 at 10:29:03PM +0100, Brian Norris wrote:
On Wed, Sep 25, 2013 at 01:33:27PM -0700, Olof Johansson wrote:
On Wed, Sep 25, 2013 at 1:05 PM, Brian Norris
computersforpe...@gmail.com wrote:
Olof has given good advice on your DT binding and has (slowly) been
On Mon, Sep 23, 2013 at 08:31:48PM +0100, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 12:56:03PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration
next patch
series addressing other comments from Brian.
+ Mark Rutland mark.rutl...@arm.com
+ Pawel Moll pawel.m...@arm.com
+ Ian Campbell ijc+devicet...@hellion.org.uk
+ Stephen Warren swar...@wwwdotorg.org
CC other DT maintainers, who were missed in this branch of mail-chain
Hi Suman,
Apologies for replying to a subthread, due to an earlier mistake on my
part I don't have the original to hand.
On Fri, Sep 27, 2013 at 05:04:22PM +0100, Kumar Gala wrote:
On Sep 17, 2013, at 2:30 PM, Suman Anna wrote:
All the platform-specific hwlock driver implementations need
Hi Suman,
On Fri, Sep 27, 2013 at 05:06:38PM +0100, Kumar Gala wrote:
On Sep 17, 2013, at 2:30 PM, Suman Anna wrote:
HwSpinlock IP is present only on OMAP4 and other newer SoCs,
which are all device-tree boot only. This patch adds the
base support for parsing the DT nodes, and removes
:
Acked-by: Mark Rutland mark.rutl...@arm.com
+
+Optional properties:
+- dmas: DMA specifier for the rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request name. Should be rx if a dma is present.
+
+Example:
+ /* AM335x
On Mon, Sep 30, 2013 at 04:13:01PM +0100, Joel Fernandes wrote:
From: Mark A. Greer mgr...@animalcreek.com
Add the generic AM33XX AES module's device tree data and
enable it for the am335x-evm, am335x-evmsk, and am335x-bone
platforms. Also add Documentation file describing the data
for the
On Fri, Oct 04, 2013 at 08:49:43PM +0100, Pekon Gupta wrote:
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
1-bit hamming ecc-code
On Fri, Oct 04, 2013 at 08:49:44PM +0100, Pekon Gupta wrote:
OMAP NAND driver support multiple ECC scheme, which can used in following
different flavours, depending on in-build Hardware engines supported by SoC.
+---+---+---+
| ECC
On Fri, Oct 04, 2013 at 08:49:47PM +0100, Pekon Gupta wrote:
DT property values for OMAP based gpmc-nand have been updated
to match changes in commit:
6faf096 ARM: OMAP2+: cleaned-up DT support of various ECC schemes
Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Doesn't
Hello,
On Thu, Sep 26, 2013 at 08:18:28PM +0100, Jyri Sarha wrote:
This patch adds DMA register location to mcasp DT bindings. On am33xx
SoCs the McASP registers are mapped trough L4 interconnect, which is
not accessible by the DMA controller, so McASP data port is mapped
trough L3 to a
On Thu, Sep 26, 2013 at 08:18:29PM +0100, Jyri Sarha wrote:
Extract DMA channels directly from DT as they can not be found from
platform resources anymore. This is a work-around until davinci audio
driver is updated to use dmaengine.
How long will this conversion take?
Signed-off-by: Jyri
On Thu, Sep 26, 2013 at 08:18:30PM +0100, Jyri Sarha wrote:
Makes interrupts property optional as the interrupts are not currently
used by the driver and adds interrupt-names property to name listed
interrupts. Currently know interrupt names are tx and rx.
Signed-off-by: Jyri Sarha
On Thu, Sep 26, 2013 at 08:18:35PM +0100, Jyri Sarha wrote:
This patch adds an optional address range to reg property. The range
describes the register location for DMA controller on am33xx. The both
address ranges are named accordingly in the reg-names property.
Signed-off-by: Hebbar,
On Thu, Sep 26, 2013 at 08:18:36PM +0100, Jyri Sarha wrote:
From: Darren Etheridge detheri...@ti.com
Adds sound, tlv320aic3x, mcasp1, and am335x_evm_audio_pin nodes.
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Jyri
On Thu, Oct 03, 2013 at 05:04:15AM +0100, Suman Anna wrote:
Hi Mark,
On 10/01/2013 03:36 AM, Mark Rutland wrote:
Hi Suman,
Apologies for replying to a subthread, due to an earlier mistake on my
part I don't have the original to hand.
No issues, thanks for your review.
On Fri
On Thu, Oct 03, 2013 at 05:12:15AM +0100, Suman Anna wrote:
Hi Mark,
On Fri, Sep 27, 2013 at 05:06:38PM +0100, Kumar Gala wrote:
On Sep 17, 2013, at 2:30 PM, Suman Anna wrote:
HwSpinlock IP is present only on OMAP4 and other newer SoCs,
which are all device-tree boot only. This
On Thu, Oct 10, 2013 at 07:36:33AM +0100, Archit Taneja wrote:
Add Dynamic Memory Manager (DMM) bindings for OMAP4 and OMAP5 devices. DMM
only requires address and irq information.
Add documentation for the DMM bindings.
Originally worked on by Andy Gross andy...@gmail.com
Cc: Andy
On Tue, Oct 08, 2013 at 01:46:41AM +0100, Mark Brown wrote:
On Mon, Oct 07, 2013 at 10:47:18PM +0100, Mark Rutland wrote:
On Thu, Sep 26, 2013 at 08:18:28PM +0100, Jyri Sarha wrote:
- interrupts : Interrupt number for McASP
The device also seems to be able to generate multiple
On Thu, Oct 10, 2013 at 06:29:59PM +0100, Peter Ujfalusi wrote:
On 10/10/2013 07:59 PM, Mark Rutland wrote:
No, they're not actually of much practical use to us at the minute but
it was generally felt better to include the information and not use it
so that if someone does come up
On Wed, Oct 16, 2013 at 04:18:22PM +0100, Balaji T K wrote:
From: Sekhar Nori nsek...@ti.com
add generic non-removable binding support for omap_hsmmc
Signed-off-by: Sekhar Nori nsek...@ti.com
Signed-off-by: Balaji T K balaj...@ti.com
---
.../devicetree/bindings/mmc/ti-omap-hsmmc.txt
On Thu, Oct 17, 2013 at 11:53:48AM +0100, Balaji T K wrote:
On Thursday 17 October 2013 02:08 PM, Mark Rutland wrote:
On Wed, Oct 16, 2013 at 04:18:22PM +0100, Balaji T K wrote:
From: Sekhar Nori nsek...@ti.com
add generic non-removable binding support for omap_hsmmc
Signed-off
Hi Pekon,
On Tue, Oct 15, 2013 at 06:49:49AM +0100, Pekon Gupta wrote:
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
1-bit hamming
[...]
+ phy-sleep_a_clk = devm_clk_get(phy-dev, sleep_a);
What means the _a in clock name?
They are 2 PHY's on 8074 chip. This drivers is supposed to
operate on PHY 0, thus sleep_a. PHY 1 is using sleep_b. Take a look
here http://www.spinics.net/lists/arm-kernel/msg276945.html
When
On Tue, Oct 15, 2013 at 08:04:20AM +0100, Archit Taneja wrote:
Enable use of DT for DMM/Tiler.
Originally worked on by Andy Gross andy...@gmail.com
Cc: Andy Gross andy...@gmail.com
Cc: DRI Development dri-de...@lists.freedesktop.org
Signed-off-by: Archit Taneja arc...@ti.com
---
Hi Joel,
I realise I'm a little late in replying to this, but there are a few
things that would be nice to fix up.
On Fri, Nov 08, 2013 at 12:37:09AM +, Joel Fernandes wrote:
Add documentation for the generic OMAP DES crypto module describing the device
tree bindings.
Signed-off-by:
On Mon, Nov 11, 2013 at 05:13:35PM +, Joel Fernandes wrote:
On 11/11/2013 05:01 AM, Mark Rutland wrote:
Hi Joel,
I realise I'm a little late in replying to this, but there are a few
things that would be nice to fix up.
On Fri, Nov 08, 2013 at 12:37:09AM +, Joel Fernandes
this looks fine to me. Feel free to add my Ack:
Acked-by: Mark Rutland mark.rutl...@arm.com
Thanks,
Mark.
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On Thu, Nov 14, 2013 at 02:35:30AM +, Tony Lindgren wrote:
Commit 89ce376c6bdc (drivers/net: Use of_match_ptr() macro in smc91x.c)
added minimal device tree support to smc91x, but it's not working on
many platforms because of the lack of some key configuration bits.
Fix the issue by
On Thu, Nov 14, 2013 at 02:35:32AM +, Tony Lindgren wrote:
Some features can be configured by the companion I2C chips,
which may not be available at the probe time. Fix the issue
by returning -EPROBE_DEFER when the MMC controller slots
are not configured.
While at it, let's also add
On Thu, Nov 14, 2013 at 02:35:33AM +, Tony Lindgren wrote:
As we claim to support device tree for mach-omap2, we
should have the necessary flags in the driver to make it
usable.
Cc: Wolfram Sang w...@the-dreams.de
Cc: linux-...@vger.kernel.org
Signed-off-by: Tony Lindgren
On Tue, Oct 22, 2013 at 01:02:53PM +0100, Felipe Balbi wrote:
Hi,
On Tue, Oct 22, 2013 at 10:42:00AM +0200, Sebastian Andrzej Siewior wrote:
On 10/21/2013 10:13 PM, Felipe Balbi wrote:
diff --git a/drivers/input/touchscreen/ti_am335x_tsc.c
b/drivers/input/touchscreen/ti_am335x_tsc.c
On Thu, Nov 14, 2013 at 12:18:47PM +, Sricharan R wrote:
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free
On Thu, Nov 14, 2013 at 12:18:48PM +, Sricharan R wrote:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the
On Thu, Nov 14, 2013 at 04:41:41PM +, Sricharan R wrote:
Hi Mark,
On Thursday 14 November 2013 07:42 PM, Mark Rutland wrote:
On Thu, Nov 14, 2013 at 12:18:48PM +, Sricharan R wrote:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals
On Thu, Nov 14, 2013 at 04:46:36PM +, Sricharan R wrote:
Hi Mark,
On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote:
On Thu, Nov 14, 2013 at 12:18:47PM +, Sricharan R wrote:
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts
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