Re: [PATCH 1/4] drm/atomic: implement drm_atomic_helper_commit_tail for runtime_pm users

On Fri, Jul 14, 2017 at 1:43 AM, Laurent Pinchart wrote: >> Commit 52055bafa1ff ("drm: rcar-du: Move plane commit code from CRTC >> start to CRTC resume") changed the order of the plane commit and CRTC >> enable operations to accommodate the runtime PM

Re: [PATCH v2 00/14] Renesas R-Car VSP: Add H3 ES2.0 support

Hi Kieran, On Thursday 13 Jul 2017 13:25:55 Kieran Bingham wrote: > Hi Laurent, > > Thank you for these patches, bringing life to the outputs of my ES2.0 target > board. > > I have tested them on my board, and including the VSP unit test suite, and > kmscube utilities. > > Feel free to add a

[PATCH v2.1 08/14] v4l: vsp1: Add support for new VSP2-BS, VSP2-DL and VSP2-D instances

New Gen3 SoCs come with two new VSP2 variants names VSP2-BS and VSP2-DL, as well as a new VSP2-D variant on V3M and V3H SoCs. Add new entries for them in the VSP device info table. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham

Re: [PATCH] drm: rcar-du: Setup planes before enabling CRTC to avoid flicker

Hi Kieran, On Wednesday 12 Jul 2017 17:35:53 Kieran Bingham wrote: > On 28/06/17 19:50, Laurent Pinchart wrote: > > Commit 52055bafa1ff ("drm: rcar-du: Move plane commit code from CRTC > > start to CRTC resume") changed the order of the plane commit and CRTC > > enable operations to accommodate

Re: [PATCH 1/4] drm/atomic: implement drm_atomic_helper_commit_tail for runtime_pm users

Hi Maxime, Thank you for the patch. On Thursday 13 Jul 2017 16:41:13 Maxime Ripard wrote: > The current drm_atomic_helper_commit_tail helper works only if the CRTC is > accessible, and documents an alternative implementation that is supposed to > be used if that happens. > > That implementation

Re: [PATCH] drm: rcar-du: Setup planes before enabling CRTC to avoid flicker

Hi Kieran, On Thursday 13 Jul 2017 16:51:18 Kieran Bingham wrote: > Hi Laurent, > > I've just seen Maxime's latest series "[PATCH 0/4] drm/sun4i: Fix a register > access bug" and it relates directly to a comment I had in this patch: > On 12/07/17 17:35, Kieran Bingham wrote: > > > On 28/06/17

Re: [PATCH v2 08/14] v4l: vsp1: Add support for new VSP2-BS, VSP2-DL and VSP2-D instances

Hi Kieran, On Thursday 13 Jul 2017 18:49:19 Kieran Bingham wrote: > On 26/06/17 19:12, Laurent Pinchart wrote: > > New Gen3 SoCs come with two new VSP2 variants names VSP2-BS and VSP2-DL, > > as well as a new VSP2-D variant on V3M and V3H SoCs. Add new entries for > > them in the VSP device info

Re: [PATCH] drm: rcar-du: Fix comments to comply with the kernel coding style

Hi Daniel, On Thursday 13 Jul 2017 14:38:15 Daniel Vetter wrote: > On Wed, Jul 12, 2017 at 08:00:42PM +0300, Laurent Pinchart wrote: > > To avoid mixing comment styles when new comments complying with the > > kernel coding style are introduced, fix all multiline comments in one > > go. > > > >

Re: [PATCH v2 06/14] v4l: vsp1: Add pipe index argument to the VSP-DU API

Hi Kieran, On Thursday 13 Jul 2017 14:16:03 Kieran Bingham wrote: > On 26/06/17 19:12, Laurent Pinchart wrote: > > In the H3 ES2.0 SoC the VSP2-DL instance has two connections to DU > > channels that need to be configured independently. Extend the VSP-DU API > > with a pipeline index to identify

[PATCH] clk: renesas: rcar-gen3: Fix error return code in cpg_sd_clock_recalc_rate

From: Takeshi Kihara In .recalc_rate of struct clk_ops, it is desirable to return 0 if an error occurs, but -EINVAL is returned. This patch fixes it. Fixes: 5b1defde7054 ("clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code") Signed-off-by: Takeshi

Re: [PATCH 1/4] drm/atomic: implement drm_atomic_helper_commit_tail for runtime_pm users

On Thu, Jul 13, 2017 at 04:41:13PM +0200, Maxime Ripard wrote: > The current drm_atomic_helper_commit_tail helper works only if the CRTC is > accessible, and documents an alternative implementation that is supposed to > be used if that happens. > > That implementation is then duplicated by some

Re: [PATCH v2 09/14] v4l: vsp1: Add support for multiple LIF instances

Hi Laurent, On 26/06/17 19:12, Laurent Pinchart wrote: > The VSP2-DL instance (present in the H3 ES2.0 and M3-N SoCs) has two LIF > instances. Adapt the driver infrastructure to support multiple LIFs. > Support for multiple display pipelines will be added separately. > > The change to the entity

Re: [PATCH v2 08/14] v4l: vsp1: Add support for new VSP2-BS, VSP2-DL and VSP2-D instances

Hi Laurent, On 26/06/17 19:12, Laurent Pinchart wrote: > New Gen3 SoCs come with two new VSP2 variants names VSP2-BS and VSP2-DL, > as well as a new VSP2-D variant on V3M and V3H SoCs. Add new entries for > them in the VSP device info table. > > Signed-off-by: Laurent Pinchart

Re: [PATCH v2 02/14] v4l: vsp1: Don't recycle active list at display start

Hi Laurent, On 26/06/17 19:12, Laurent Pinchart wrote: > When the display start interrupt occurs, we know that the hardware has > finished loading the active display list. The driver then proceeds to > recycle the list, assuming it won't be needed anymore. > > This assumption holds true for

Re: [PATCH v2] ARM: dts: iwg20m: Add MMCIF0 support

On Thu, Jul 13, 2017 at 5:39 PM, Chris Paterson wrote: > Define the iwg20m board dependent part of the MMCIF0 device node. > > Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven > v1->v2: > -

Re: [PATCH] drm: rcar-du: Setup planes before enabling CRTC to avoid flicker

On 13/07/17 16:51, Kieran Bingham wrote: > Hi Laurent, > > I've just seen Maxime's latest series "[PATCH 0/4] drm/sun4i: Fix a register > access bug" and it relates directly to a comment I had in this patch: > > On 12/07/17 17:35, Kieran Bingham wrote: >> Hi Laurent, >> >> On 28/06/17 19:50,

RE: [PATCH] pinctrl: sh-pfc: r8a7791: Add missing mmc_data8_b pin group

Hello Geert, > From: linux-gpio-ow...@vger.kernel.org [mailto:linux-gpio- > ow...@vger.kernel.org] On Behalf Of Geert Uytterhoeven > Sent: 12 July 2017 12:59 > > Pins D6 and D7 of the MMC interface can be muxed to two different sets of > pins, but currently only one set is supported. > Add a pin

[PATCH v2] ARM: dts: iwg20m: Add MMCIF0 support

Define the iwg20m board dependent part of the MMCIF0 device node. Signed-off-by: Chris Paterson <chris.paters...@renesas.com> --- This patch is based on: renesas-devel-20170713-v4.12 + pinctrl: sh-pfc: r8a7791: Add R8A7743 support + pinctrl: sh-pfc: r8a7791: Add missing mmc_data8_b pin

[PATCH 3/4] drm/sun4i: engine: Add commit_poll function

On the earlier Allwinner chips, with the first iteration of the display engine, the backend commit bit needs to be polled before making any register access to the backend. Add an operation for that, that will be called in atomic_begin in order to be sure to have that bit cleared before we do any

[PATCH 2/4] drm/sun4i: Use the runtime_pm commit_tail variant

The backend (planes) commit can only happen when the TCON (CRTC) is enabled, which is not guaranteed with the default commit_tail helper. Let's use the runtime_pm version that is designed specifically to deal with that case. Signed-off-by: Maxime Ripard ---

[PATCH 4/4] drm/sun4i: make sure we don't have a commit pending

In the earlier display engine designs, any register access while a commit is pending is forbidden. One of the symptoms is that reading a register will return another, random, register value which can lead to register corruptions if we ever do a read/modify/write cycle. Signed-off-by: Maxime

[PATCH 1/4] drm/atomic: implement drm_atomic_helper_commit_tail for runtime_pm users

The current drm_atomic_helper_commit_tail helper works only if the CRTC is accessible, and documents an alternative implementation that is supposed to be used if that happens. That implementation is then duplicated by some drivers. Instead of documenting it, let's implement an helper that all the

Re: [PATCH v2 07/14] v4l: vsp1: Add support for the BRS entity

On 26/06/17 19:12, Laurent Pinchart wrote: > The Blend/ROP Sub Unit (BRS) is a stripped-down version of the BRU found > in several VSP2 instances. Compared to a regular BRU, it supports two > inputs only, and thus has no ROP unit. > > Add support for the BRS by modeling it as a new entity type,

Re: [PATCH v2 06/14] v4l: vsp1: Add pipe index argument to the VSP-DU API

On 26/06/17 19:12, Laurent Pinchart wrote: > In the H3 ES2.0 SoC the VSP2-DL instance has two connections to DU > channels that need to be configured independently. Extend the VSP-DU API > with a pipeline index to identify which pipeline the caller wants to > operate on. > > Signed-off-by:

Re: [PATCH v2 03/14] v4l: vsp1: Don't set WPF sink pointer

On 26/06/17 19:12, Laurent Pinchart wrote: > The sink pointer is used to configure routing inside the VSP, and as > such must point to the next VSP entity in the pipeline. The WPF being a > pipeline terminal sink, its output route can't be configured. The > routing configuration code already

Re: [PATCH v2 01/14] v4l: vsp1: Fill display list headers without holding dlm spinlock

Hi Laurent, Starts easy ... (I haven't gone through these in numerical order of course :D) On 26/06/17 19:12, Laurent Pinchart wrote: > The display list headers are filled using information from the display > list only. Lower the display list manager spinlock contention by filling > the headers

Re: [PATCH] drm: rcar-du: Fix comments to comply with the kernel coding style

On Wed, Jul 12, 2017 at 08:00:42PM +0300, Laurent Pinchart wrote: > To avoid mixing comment styles when new comments complying with the > kernel coding style are introduced, fix all multiline comments in one > go. > > Signed-off-by: Laurent Pinchart

Re: [PATCH v2 00/14] Renesas R-Car VSP: Add H3 ES2.0 support

Hi Laurent, Thankyou for these patches, bringing life to the outputs of my ES2.0 target board. I have tested them on my board, and including the VSP unit test suite, and kmscube utilities. Feel free to add a Tested-by: Kieran Bingham to all of the

[PATCH] arm64: dts: renesas: salvator-common: Remove extra LVDS port label

The DU LVDS output is on port 3 on R8A7795 but on port 2 on R8A7796. The lvds_connector label thus can't be defined in salvator-common.dtsi, common to the two SoCs. The lvds_connector label is meant for convience to be referenced from panel device tree files, such as r8a77xx-aa104xd12-panel.dtsi

[PATCH v2] arm64: dts: renesas: r8a7796: Add FDP1 instance

The r8a7796 has a single FDP1 instance. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 10 ++

Re: [PATCH 2/2] arm64: dts: r8a7795: salvator-xs: Connect DU dot clocks 0 and 3

On Thu, Jul 13, 2017 at 1:09 PM, Laurent Pinchart wrote: > The DU dot clocks 0 and 3 are provided by the programmable VC6 clock > generator. Connect them to the clock source node. > > Signed-off-by: Laurent Pinchart

Re: [PATCH] drm: rcar-du: Fix comments to comply with the kernel coding style

Hi Laurent, Thanks for this - I think that's a better way forward in this instance now that a few of the locations have been touched, rather than leaving the driver in a mixed state. On 12/07/17 18:00, Laurent Pinchart wrote: > To avoid mixing comment styles when new comments complying with the

Re: [PATCH] arm64: dts: renesas: salvator-xs: Add VC6 clock generator

On Thu, Jul 13, 2017 at 1:06 PM, Laurent Pinchart wrote: > The VC6 is an I2C-controlled programmable clock generator, used on the > board to provide a display dot clock. Add it to DT. > > Signed-off-by: Laurent Pinchart

Re: [PATCH 1/2] arm64: dts: renesas: r8a7796: Add resets property to FCP devices

On Thu, Jul 13, 2017 at 12:58 PM, Laurent Pinchart wrote: > The FCP nodes are missing the resets property. Add it. > > Fixes: 7153c69fb8e1 ("arm64: dts: renesas: r8a7796: Add FCPF and FCPV > instances") > Signed-off-by: Laurent Pinchart

Re: [PATCH 2/2] arm64: dts: renesas: r8a7796: Add resets property to VSP devices

On Thu, Jul 13, 2017 at 12:58 PM, Laurent Pinchart wrote: > The VSP nodes are missing the resets property. Add it. > > Fixes: 5a89c826745f ("arm64: dts: renesas: r8a7796: Add VSP instances") > Signed-off-by: Laurent Pinchart

[PATCH 2/2] arm64: dts: r8a7795: salvator-xs: Connect DU dot clocks 0 and 3

The DU dot clocks 0 and 3 are provided by the programmable VC6 clock generator. Connect them to the clock source node. Signed-off-by: Laurent Pinchart --- arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 6 -- 1 file changed, 4 insertions(+),

[PATCH] arm64: dts: renesas: salvator-xs: Add VC6 clock generator

The VC6 is an I2C-controlled programmable clock generator, used on the board to provide a display dot clock. Add it to DT. Signed-off-by: Laurent Pinchart --- arch/arm64/boot/dts/renesas/salvator-xs.dtsi | 10 ++ 1 file changed, 10

[PATCH 1/2] arm64: dts: renesas: r8a7796: Add resets property to FCP devices

The FCP nodes are missing the resets property. Add it. Fixes: 7153c69fb8e1 ("arm64: dts: renesas: r8a7796: Add FCPF and FCPV instances") Signed-off-by: Laurent Pinchart --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ++ 1 file changed, 6

Re: [PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

On 12 July 2017 at 12:03, Chris Paterson wrote: > Signed-off-by: Chris Paterson > > diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt > b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt > index c32dc5a..703e18c

Re: [PATCH 14/14] pinctrl: sh-pfc: r8a7796: Rename CS1# pin function definitions

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch renames the pin function macro definitions of the GPSR1 and > IPSR4 registers value for the CS1# pin. > > This is a correction because GPSR and

Re: [PATCH v3] mmc: tmio-mmc: fix bad pointer math

On 12 July 2017 at 17:40, Chris Brandt wrote: > The existing code gives an incorrect pointer value. > The buffer pointer 'buf' was of type unsigned short *, and 'count' was a > number in bytes. A cast of buf should have been used. > > However, instead of casting, just

Re: [PATCH 13/14] pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for FSO pins group

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes IPSR{12,17,18} and MOD_SEL0 pin assignment for FSO pins > group. > > This is a correction because GPSR and IPSR register specification for >

Re: [PATCH 12/14] pinctrl: sh-pfc: r8a7796: Fix to delete MOD_SEL0 bit2 register definitions

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the macro definitions of MOD_SEL0 bit2 register deleted. > > This is a correction because MOD_SEL register specification for R8A7796 > SoC

Re: [PATCH 11/14] pinctrl: sh-pfc: r8a7796: Fix to delete SATA_DEVSLP_B pins function definitions

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the macro definitions of SATA_DEVSLP_B pins function > deleted. > > This is a correction to the incorrect implementation of IPSR register >

Re: [PATCH 10/14] pinctrl: sh-pfc: r8a7796: Fix to delete FSCLKST pin and IPSR7 bit[15:12] register definitions

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the macro definitions of FSCLKST pins function and IPSR7 > bit[15:12] register deleted. > > This is a correction because IPSR register

Re: [PATCH 09/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for TCLK{1,2}_{A,B} pins group

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is > selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected > for

Re: [PATCH 08/14] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pins function definitions

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the implementation incorrect of IPSR register value > definitions for MSIOF3_{SS1,SS2}_E pins function. > > This is a correction to the

Re: [PATCH 07/14] pinctrl: sh-pfc: r8a7796: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pin function definitions

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the implementation incorrect of IPSR register value > definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function. > > This is a

Re: [PATCH 06/14] pinctrl: sh-pfc: r8a7796: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function definitions

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the implementation incorrect of IPSR register value > definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function. > > This is a correction to

RE: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

> From: Simon Horman [mailto:ho...@verge.net.au] > Sent: 13 July 2017 09:12 > > On Thu, Jul 13, 2017 at 10:02:29AM +0200, Simon Horman wrote: > > On Wed, Jul 12, 2017 at 01:52:49PM +0200, Geert Uytterhoeven wrote: > > > Hi Chris, > > > > > > On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson > >

Re: [PATCH 05/14] pinctrl: sh-pfc: r8a7796: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to MOD_SEL1 bit10

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1 > bit11 to MOD_SEL1 bit10. > > This is a correction to the incorrect implementation of

Re: [PATCH 04/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group

Hi Kaneko-san, Kihara-san, On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment > for SSI pins group. > > This is a correction to the

Re: [kbuild-all] [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

d to the wrong git tree, please drop us a note to >> help improve the system] >> >> url: >> https://github.com/0day-ci/linux/commits/Chris-Paterson/Add-MMCIF0-support-for-r8a7743-iwg20m/20170713-042814 >> base: https://git.kernel.org/pub/scm/linux/kernel/git/

Re: [PATCH 03/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the implementation incorrect of MOD_SEL2 bit26 value > when SCK5_A pin function is selected for IPSR16 bit[31:28]. > > This is a correction

Re: [PATCH] arm64: dts: r8a7796: Add missing second pair of DMA names to MSIOF nodes

On Thu, Jul 13, 2017 at 10:23:43AM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Jul 13, 2017 at 10:18 AM, Simon Horman wrote: > > On Wed, Jul 12, 2017 at 12:35:53PM +0200, Geert Uytterhoeven wrote: > >> MSIOF0 and MSIOF1 are tied to two DMA controllers through two

Re: [PATCH 02/14] pinctrl: sh-pfc: r8a7796: Fix IPSR register setting when MSIOF3_SS1_E pin was selected

Hi Kaneko-san, On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes to set IPSR register when using MSIOF3_SS1_E pin function > is selected. > > This is a correction to the incorrect

Re: [PATCH] arm64: dts: r8a7796: Add missing second pair of DMA names to MSIOF nodes

Hi Simon, On Thu, Jul 13, 2017 at 10:18 AM, Simon Horman wrote: > On Wed, Jul 12, 2017 at 12:35:53PM +0200, Geert Uytterhoeven wrote: >> MSIOF0 and MSIOF1 are tied to two DMA controllers through two pairs of >> DMA specifiers. However, the second pair of corresponding DMA

Re: [PATCH v2] ARM: shmobile: rcar-gen2: Add support for CPG/MSSR bindings

On Wed, Jul 12, 2017 at 12:39:32PM +0200, Geert Uytterhoeven wrote: > When using the new CPG/MSSR bindings, there is no longer a > "renesas,rcar-gen2-cpg-clocks" node, and the code to obtain the external > clock crystal frequency falls back to a default of 20 MHz. > While this is correct for all

Re: [PATCH] arm64: dts: r8a7796: Add missing second pair of DMA names to MSIOF nodes

On Wed, Jul 12, 2017 at 12:35:53PM +0200, Geert Uytterhoeven wrote: > MSIOF0 and MSIOF1 are tied to two DMA controllers through two pairs of > DMA specifiers. However, the second pair of corresponding DMA names was > missing. > > Fixes: 80fab06e258da762 ("arm64: dts: r8a7796: Add all MSIOF

Re: [PATCH v3] arm64: dts: r8a7795: Add all MSIOF nodes

On Wed, Jul 12, 2017 at 12:34:21PM +0200, Geert Uytterhoeven wrote: > Add the device nodes for all MSIOF SPI controllers, incl. clocks, power > domain, dma, and reset properties. > > Due to a hardware erratum on R-Car H3 ES1.x, using MSIOF for SPI is only > supported on ES2.0 and later. > >

Re: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

On Thu, Jul 13, 2017 at 10:02:29AM +0200, Simon Horman wrote: > On Wed, Jul 12, 2017 at 01:52:49PM +0200, Geert Uytterhoeven wrote: > > Hi Chris, > > > > On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson > > wrote: > > > Define the iwg20m board dependent part of the

Re: [PATCH 0/3] ARM: dts: r8a779[014]: Use R-Car Gen 2 fallback binding for vin nodes

On Thu, Jul 13, 2017 at 07:07:44AM +0200, Niklas Söderlund wrote: > Hi Simon, > > Thanks for your work. > > On 2017-07-11 14:56:46 +0200, Simon Horman wrote: > > Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a779[014] SoCs. > > > > This has no run-time effect for the current

Re: [PATCH 01/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] > value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24]. > > This is a

Re: [PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

On Thu, Jul 13, 2017 at 10:00:11AM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Jul 13, 2017 at 9:54 AM, Simon Horman wrote: > > On Wed, Jul 12, 2017 at 01:20:07PM +0200, Geert Uytterhoeven wrote: > >> On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson > >>

Re: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

On Wed, Jul 12, 2017 at 01:52:49PM +0200, Geert Uytterhoeven wrote: > Hi Chris, > > On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson > wrote: > > Define the iwg20m board dependent part of the MMCIF0 device node. > > > > Signed-off-by: Chris Paterson

Re: [PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

Hi Simon, On Thu, Jul 13, 2017 at 9:54 AM, Simon Horman wrote: > On Wed, Jul 12, 2017 at 01:20:07PM +0200, Geert Uytterhoeven wrote: >> On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson >> wrote: >> > Signed-off-by: Chris Paterson

Re: [PATCH 2/3] ARM: dts: r8a7743: Add MMCIF0 support

On Wed, Jul 12, 2017 at 01:21:20PM +0200, Geert Uytterhoeven wrote: > On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson > wrote: > > Add the MMCIF0 device to the r8a7743 device tree. > > > > Signed-off-by: Chris Paterson > > Reviewed-by:

Re: [PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

On Wed, Jul 12, 2017 at 01:20:07PM +0200, Geert Uytterhoeven wrote: > On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson > wrote: > > Signed-off-by: Chris Paterson > > Reviewed-by: Geert Uytterhoeven Thanks,

Re: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

lp improve the system] > > url: > https://github.com/0day-ci/linux/commits/Chris-Paterson/Add-MMCIF0-support-for-r8a7743-iwg20m/20170713-042814 > base: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next > config: arm-at91_dt_defconfig (attached as .confi

Re: [PATCH v2 2/7] arm64: dts: renesas: r8a7796: Add FCPF and FCPV instances

On Wed, Jul 12, 2017 at 11:45:41AM +0300, Laurent Pinchart wrote: > Hi Geert, > > On Wednesday 12 Jul 2017 09:22:50 Geert Uytterhoeven wrote: > > On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart wrote: > > > The FCPs handle the interface between various IP cores and memory. Add > > > the

Re: [PATCH v2 3/7] arm64: dts: renesas: r8a7796: Add VSP instances

On Wed, Jul 12, 2017 at 09:24:22AM +0200, Geert Uytterhoeven wrote: > Hi Laurent, Simon, > > On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart > wrote: > > The r8a7796 has 5 VSP instances. > > > > Signed-off-by: Laurent Pinchart

Re: [RESEND] [PATCH v2.1 1/2] dt-bindings: display: rcar-du: Add a VSP channel index to the vsps DT property

On Thu, Jul 13, 2017 at 09:46:19AM +0200, Simon Horman wrote: > On Wed, Jul 12, 2017 at 11:43:36AM +0300, Laurent Pinchart wrote: > > On some R-Car SoCs a single VSP can serve multiple DU channels through > > multiple LIF instances in the VSP. The current DT bindings don't support > > specifying

Re: [PATCH v2 0/2] R-Car H3 ES2.0 Salvator-X: Enable DU support in DT

On Wed, Jul 12, 2017 at 11:44:41AM +0300, Laurent Pinchart wrote: > Hi Simon, > > On Wednesday 12 Jul 2017 07:56:15 Simon Horman wrote: > > On Wed, Jul 12, 2017 at 02:20:43AM +0300, Laurent Pinchart wrote: > > > On Tuesday 11 Jul 2017 11:16:17 Simon Horman wrote: > > >> On Mon, Jul 10, 2017 at

Re: [RESEND] [PATCH v2.1 1/2] dt-bindings: display: rcar-du: Add a VSP channel index to the vsps DT property

On Wed, Jul 12, 2017 at 11:43:36AM +0300, Laurent Pinchart wrote: > On some R-Car SoCs a single VSP can serve multiple DU channels through > multiple LIF instances in the VSP. The current DT bindings don't support > specifying that kind of SoC integration scheme. Extend them with a VSP > channel