On Thu, Aug 17, 2017 at 01:16:28PM +0200, Geert Uytterhoeven wrote:
> Document support for the (H)SCIF serial ports in the Renesas R-Car D3
> (r8a77995) SoC.
>
> No driver update is needed.
>
> Signed-off-by: Geert Uytterhoeven
> ---
>
On Thu, Aug 17, 2017 at 01:14:25PM +0200, Geert Uytterhoeven wrote:
> Document support for the Watchdog Timer (WDT) Controller in the Renesas
> R-Car D3 (r8a77995) SoC.
>
> No driver update is needed.
>
> Signed-off-by: Geert Uytterhoeven
> ---
>
Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the usecount of the
node being passed to of_fwnode_graph_get_port_parent(). Preserve the
usecount by using of_get_parent() instead of of_get_next_parent() which
don't decrement the usecount of the node passed to it.
Fixes: 3b27d00e7b6d7c88
On Mon, Aug 21, 2017 at 11:38:17AM +0100, Biju Das wrote:
> Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI
> is identical to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> ---
> v1->v2
> -Modified the listing SoC's description related to SoC
Hejssan Niklas,
Niklas Söderlund wrote:
Hi Sakari,
On 2017-08-21 22:03:02 +0300, Sakari Ailus wrote:
Hi Niklas,
Niklas Söderlund wrote:
Hi Sakari,
On 2017-08-21 16:30:17 +0300, Sakari Ailus wrote:
Hi Niklas,
Niklas Söderlund wrote:
Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the
Hi Sakari,
On 2017-08-21 22:03:02 +0300, Sakari Ailus wrote:
> Hi Niklas,
>
> Niklas Söderlund wrote:
> > Hi Sakari,
> >
> > On 2017-08-21 16:30:17 +0300, Sakari Ailus wrote:
> > > Hi Niklas,
> > >
> > > Niklas Söderlund wrote:
> > > > Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the
Hi Niklas,
Niklas Söderlund wrote:
Hi Sakari,
On 2017-08-21 16:30:17 +0300, Sakari Ailus wrote:
Hi Niklas,
Niklas Söderlund wrote:
Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the usecount of the
node being passed to of_fwnode_graph_get_port_parent(). Preserve the
usecount just like
Hi Niklas,
On Mon, Aug 21, 2017 at 2:51 PM, Niklas Söderlund
wrote:
> Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the usecount of the
> node being passed to of_fwnode_graph_get_port_parent(). Preserve the
> usecount just like it is done in
Hi Sakari,
On 2017-08-21 16:30:17 +0300, Sakari Ailus wrote:
> Hi Niklas,
>
> Niklas Söderlund wrote:
> > Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the usecount of the
> > node being passed to of_fwnode_graph_get_port_parent(). Preserve the
> > usecount just like it is done in
> It works, now :)
Great!
> tmio_mmc_init_ocr()
>
> fails (silently!). And with this the whole RCar3 SDHI, without any error
> message.
I'll check next week about an error message there.
> Many thanks for your help!
You're welcome. If you want, you can even test SDR104 by applying this
Hi Geert,
please consider pulling driver cpufreq driver changes to allow it to
automatically create a cpufreq device. This patch is proposed by
Viresh Kumar. The other patches remove the r8a7795 and r8a7796 from the
creation whitelist so that Viresh's code may be exercised on those
platforms.
Hi Niklas,
Niklas Söderlund wrote:
Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the usecount of the
node being passed to of_fwnode_graph_get_port_parent(). Preserve the
usecount just like it is done in of_graph_get_port_parent().
The of_fwnode_graph_get_port_parent() is called by
Hi Geert,
please consider pulling OPPs table for cpufreq support on the r8a7796 and
r8a7795.
This pull request is based on renesas-arm64-dt-for-v4.14.
These are dependencies for supporting CPUFreq. The remainder of that
work is being posted separately and can be found at:
Hi Geert,
please consider pulling the Z and Z2 clock support for r8a779[56] (v2).
This pull request is based on clk-renesas-for-v4.14-tag1.
These are dependencies for supporting CPUFreq. The remainder of that
work is being posted separately and can be found at:
From: Takeshi Kihara
This patch adds Z2 clock for R8A7796 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Horman
---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
From: Takeshi Kihara
This patch adds Z2 clock divider support for R-Car Gen3 SoC.
Signed-off-by: Takeshi Kihara
[simon: add recalc_rate() helper; use bitops macros]
Signed-off-by: Simon Horman
---
v1
From: Takeshi Kihara
This patch adds Z clock for R8A7795 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Horman
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
From: Takeshi Kihara
This patch adds Z clock for R8A7796 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Horman
---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
Hi,
this patch-set adds Z and Z2 clock support.
These are dependencies for supporting CPUFreq. The remainder of that
work is being posted separately and can be found at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git
topic/rcar-gen3-cpufreq
A description of steps taken to
From: Takeshi Kihara
This patch adds Z2 clock for r8a7795 SoC.
Signed-off-by: Takeshi Kihara
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
From: Takeshi Kihara
This patch adds Z clock divider support for R-Car Gen3 SoC.
Signed-off-by: Takeshi Kihara
[simon: divide parent by 2; use bitops macros]
Signed-off-by: Simon Horman
---
v1 [Simon
Using CONFIG_OF_DYNAMIC=y uncovered an imbalance in the usecount of the
node being passed to of_fwnode_graph_get_port_parent(). Preserve the
usecount just like it is done in of_graph_get_port_parent().
Fixes: 3b27d00e7b6d7c88 ("device property: Move fwnode graph ops to firmware
specific
On 21.08.2017 10:24, Dirk Behme wrote:
On 21.08.2017 10:18, Wolfram Sang wrote:
Hi Dirk,
Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I
will try to test your patch on my Salvator-XS board today.
Ok, thanks :)
Your patch on top of v4.13-rc5 makes SDHI work on my
On Mon, Aug 21, 2017 at 01:25:11PM +0100, Biju Das wrote:
> Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI
> is identical to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
Reviewed-by: Wolfram Sang
Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI
is identical to the R-Car Gen2 family.
Signed-off-by: Biju Das
---
v1->v2
- Modified the listing SoC's description related to SoC
with 1 Clock and 2 Clocks
v2->v3
- Fixed the trailing double
On 9 August 2017 at 20:29, Wolfram Sang
wrote:
> Make use of the 64 bit sdbuf width on Renesas R-Car Gen3. If the
> registers are 8 byte apart, the width is also 64 bit. For all others,
> the width is 32 bit, even if the registers are only 16 bit apart.
>
>
On 9 August 2017 at 21:14, Wolfram Sang
wrote:
> Here is a small series to improve RZ support for SDHI. I don't have that
> platform currently, so I hope Chris has some time to check these simple
> patches. It is based on top of the patch just sent out:
>
> -Original Message-
> From: devicetree-ow...@vger.kernel.org [mailto:devicetree-
> ow...@vger.kernel.org] On Behalf Of Geert Uytterhoeven
> Sent: 21 August 2017 12:30
> To: Biju Das
> Cc: Ulf Hansson ; Rob Herring ;
>
> - Below is the number clocks for each supported SoC:
> -1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
> - R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
> -2: R7S72100
> + Most supported SoCs only have 1 clock. Devices which have more
> +
Hi Biju,
On Mon, Aug 21, 2017 at 12:38 PM, Biju Das wrote:
> Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI
> is identical to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> ---
> v1->v2
> -Modified the listing SoC's
Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI
is identical to the R-Car Gen2 family.
Signed-off-by: Biju Das
---
v1->v2
-Modified the listing SoC's description related to SoC
with 1 Clock and 2 Clocks
This patch is compiled and tested
> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: 21 August 2017 09:25
> To: Biju Das
> Cc: Ulf Hansson ; Rob Herring ;
> Mark Rutland ; Simon Horman
>
Hi Simon,
On Thursday, 13 July 2017 14:21:10 EEST Laurent Pinchart wrote:
> The r8a7796 has a single FDP1 instance.
>
> Signed-off-by: Laurent Pinchart
> Reviewed-by: Kieran Bingham
> Reviewed-by: Geert Uytterhoeven
On Fri, Aug 18, 2017 at 05:28:01PM +0200, Thierry Reding wrote:
> On Fri, Aug 18, 2017 at 12:09:01PM +0200, Simon Horman wrote:
> > Remove support for the SH7372 (SH-Mobile AP4) from the renesas-tpu driver.
> >
> > Commit edf4100906044225 ("ARM: shmobile: sh7372 dtsi: Remove Legacy file")
> >
On Fri, Aug 18, 2017 at 11:16:53AM +0200, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> The current practice is to not group clocks under a "clocks" subnode,
> but just put them together with the other on-SoC devices.
>
> Hence this patch series implements this for the various R-Car
On Fri, Aug 18, 2017 at 11:11:33AM +0200, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> Currently Renesas R-Car Gen2 SoCs use the common clk-rcar-gen2,
> clk-mstp, and clk-div6 drivers, which depend on most clocks being
> described in DT. Especially the module (MSTP) clocks are
On Fri, Aug 18, 2017 at 12:12:38PM +0100, Biju Das wrote:
> The iWave RZ/G1M Q7 SOM supports RTC (TI BQ32000).
> To increase hardware support enable the driver in the
> multi_v7_defconfig multiplatform configuration.
>
> Signed-off-by: Biju Das
Thanks, applied for
On Fri, Aug 18, 2017 at 10:07:26AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Fri, Aug 18, 2017 at 10:02 AM, Simon Horman wrote:
> > On Thu, Aug 17, 2017 at 01:29:14PM +0200, Geert Uytterhoeven wrote:
> >> With W=1:
> >>
> >>
On Wed, Aug 16, 2017 at 03:22:27PM +0200, Ulrich Hecht wrote:
> Adds serial port SCIF1 and the MAX9260 deserializers connected to it.
>
> Signed-off-by: Ulrich Hecht
Hi Ulrich,
I am marking this patch as deferred pending progress on the rest of the
series.
On Mon, Aug 14, 2017 at 12:49:49PM +0100, Biju Das wrote:
> Define the iWave RainboW-G20D-Qseven board dependent part of the
> SDHI1 device node.
>
> Signed-off-by: Biju Das
Acked-by: Wolfram Sang
signature.asc
Description: PGP
> > > +vmmc-supply = <_3p3v>;
> > > +vqmmc-supply = <_3p3v>;
> >
> > Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
> > tested and added later?
>
> Thanks. The current hardware doesn't support 1.8V switching for SDHI0. There
> is a plan to
> add this in future board
> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: 21 August 2017 09:29
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Simon Horman ; Magnus
> Damm
> +
> + {
> + pinctrl-0 = <_pins>;
> + pinctrl-names = "default";
> +
> + vmmc-supply = <_3p3v>;
> + vqmmc-supply = <_3p3v>;
> + cd-gpios = < 11 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
Just to make sure: No 1.8V and UHS support (SDR50/104)? Or is this to be
tested and
On 21.08.2017 10:18, Wolfram Sang wrote:
Hi Dirk,
Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I
will try to test your patch on my Salvator-XS board today.
Ok, thanks :)
Your patch on top of v4.13-rc5 makes SDHI work on my Salvator-XS with a
Please feel free to
> Below is the number clocks for each supported SoC:
> -1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
> - R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
> +1: SH73A0, R8A73A4, R8A7740, R8A7743, R8A7745, R8A7778, R8A7779,
> + R8A7790,
Hi Dirk,
> > Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I
> > will try to test your patch on my Salvator-XS board today.
>
> Ok, thanks :)
Your patch on top of v4.13-rc5 makes SDHI work on my Salvator-XS with a
H3 ES2.0. It detects the eMMC and I can mount SD cards on
From: Kuninori Morimoto
Anton Volkov noticed that engine->dev is NULL before
of_dma_controller_register() in probe.
Thus there might be a NULL pointer dereference in
rcar_dmac_chan_start_xfer while accessing chan->chan.device->dev which
is equal to
Hi Laurent
> I don't think this fully fixes the problem, as the rcar_dmac_isr_error() IRQ
> handler is still registered before all this. Furthermore, at least some of
> the
> initialization at the end of rcar_dmac_chan_probe() has to be moved before
> the
> rcar_dmac_isr_channel() IRQ
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