On Thu, Nov 16, 2017 at 02:46:34PM +0100, Geert Uytterhoeven wrote:
> Document the compatible value for the Renesas R1EX24128ASAS0A two-wire
> serial interface EEPROM, so it can be used in DTS files without causing
> checkpatch warnings.
>
> Signed-off-by: Geert Uytterhoeven
Acked-by: Wolfram Sa
From: Magnus Damm
Hack up the IPMMU driver to enable VM64 mode with 30-bit IOVA.
For this configuration the IPMMU hardware is configured with IMTTBCR.SL=0
and TSZ0 bits set to 0x22. This will enable a 30-bit IOVA space and use
"Initial lookup level 2" (in Table D4-13 of armv8_arm.pdf) also known
iommu/ipmmu-vmsa: IPMMU IOVA prototyping on r8a7796 ES1.0
[PATCH/RFC 01/04] iommu: Hack to dump page table configuration on boot
[PATCH/RFC 02/04] iommu/ipmmu-vmsa: VA64 mode with 32-bit IOVA
[PATCH/RFC 03/04] iommu/ipmmu-vmsa: VA64 mode with 31-bit IOVA
[PATCH/RFC 04/04] iommu/ipmmu-vmsa: VA64 mo
From: Magnus Damm
Hack up the IPMMU driver to enable VM64 mode with 31-bit IOVA.
For this configuration the IPMMU hardware is configured with IMTTBCR.SL=1
and TSZ0 bits set to 0x21. This will enable a 31-bit IOVA space and use
"Initial lookup level 1" (in Table D4-13 of armv8_arm.pdf) also known
From: Magnus Damm
Adjust code to output page table configuration on boot. Not for upstream merge.
Not-Yet-Signed-off-by: Magnus Damm
---
drivers/iommu/io-pgtable-arm.c | 12
drivers/iommu/io-pgtable.c |4
2 files changed, 16 insertions(+)
--- 0001/drivers/iommu/io
From: Magnus Damm
Hack up the IPMMU driver to enable VM64 mode with 32-bit IOVA.
For this configuration the IPMMU hardware is configured with IMTTBCR.SL=1
and TSZ0 bits set to 0x20. This will enable a 32-bit IOVA space and use
"Initial lookup level 1" (in Table D4-13 of armv8_arm.pdf) also known
From: Magnus Damm
Here's a simple prototype hack to get the R-Car M3-N SoC working with
the r8a77965 Salvator-X that is available in my remote access rack.
This code will allow me to test and development IPMMU features on
latest mainline together with new hardware such as r8a77965.
As base the
On Thu, Nov 16, 2017 at 06:22:48PM +, Fabrizio Castro wrote:
> Change the sorting of the part numbers from descending to ascending to
> match with other documentation.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
> ---
> v1->v2:
> * new patch triggered by Geert's comment, see t
On Thu, Nov 16, 2017 at 06:22:49PM +, Fabrizio Castro wrote:
> Add compatible strings for r8a7743 and r8a7745. No driver change
> is needed as "renesas,rcar-gen2-vin" will activate the right code.
> However, it is good practice to document compatible strings for the
> specific SoC as this allow
On Thu, Nov 16, 2017 at 02:46:34PM +0100, Geert Uytterhoeven wrote:
> Document the compatible value for the Renesas R1EX24128ASAS0A two-wire
> serial interface EEPROM, so it can be used in DTS files without causing
> checkpatch warnings.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> Documentatio
On 11/17/2017 03:35 PM, Simon Horman wrote:
> On Thu, Nov 16, 2017 at 10:43:35AM +0100, Geert Uytterhoeven wrote:
>> Hi Uli,
>>
>> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
>> wrote:
>>> The single SDHI controller is connected to eMMC.
>>>
>>> Signed-off-by: Ulrich Hecht
>>
>> Thanks for your
On Fri, Nov 17, 2017 at 06:00:46PM +, Fabrizio Castro wrote:
> this patch has been around for some time now, it was reviewed-by Geert
> Uytterhoeven and acked-by Rob Herring, any news?
Please don't send content free pings and please allow a reasonable time
for review. People get busy, go on
Dear All,
this patch has been around for some time now, it was reviewed-by Geert
Uytterhoeven and acked-by Rob Herring, any news?
Thanks,
Fab
> Subject: [PATCH] dt-bindings: qspi: Add r8a7743/5 to the compatible list
>
> Signed-off-by: Fabrizio Castro
> ---
> Documentation/devicetree/bindings
Hi Marek,
On Fri, Nov 10, 2017 at 10:58:42PM +0100, Marek Vasut wrote:
> From: Phil Edworthy
>
> Most PCIe host controllers support L0s and L1 power states via ASPM.
> The R-Car hardware only supports L0s, so when the system suspends and
> resumes we have to manually handle L1.
> When the system
On Fri, Nov 17, 2017 at 06:32:19AM -0800, Simon Horman wrote:
> On Thu, Nov 16, 2017 at 10:31:31AM +0100, Geert Uytterhoeven wrote:
> > Hi Uli,
> >
> > On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> > wrote:
> > > No devices to add, I2C1 has an external connector only.
> > >
> > > Signed-off-by:
On Fri, Nov 17, 2017 at 06:31:21AM -0800, Simon Horman wrote:
> On Thu, Nov 16, 2017 at 10:27:56AM +0100, Geert Uytterhoeven wrote:
> > Hi Ulrich,
> >
> > On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> > wrote:
> > > Enables EEPROM on I2C0 on the Draak board.
> > >
> > > Signed-off-by: Ulrich He
On Fri, Nov 17, 2017 at 07:11:18PM +0300, Sergei Shtylyov wrote:
> On 11/17/2017 05:19 PM, Simon Horman wrote:
>
> > > > Describe all 6 GPIO controllers in the R8A77970 device tree.
> > > >
> > > > Signed-off-by: Sergei Shtylyov
> > >
> > > Reviewed-by: Geert Uytterhoeven
> >
> > Thanks, appl
From: Kieran Bingham
Hi Geert,
Please consider this updated tag for the next renesas drivers release.
Regards
Kieran
The following changes since commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4:
Linux 4.14 (2017-11-12 10:46:13 -0800)
are available in the git repository at:
git://git.ke
> Here's CAN and CAN FD support for the R-Car D3. This is a by-the-datasheet
> implementation, with the datasheet missing some bits, namely the pin map.
> I filled in the gaps with frog DNA^W^W^Wby deducing the information from
> pin numbers already in the PFC driver, so careful scrutiny is advise
On 11/17/2017 05:19 PM, Simon Horman wrote:
Describe all 6 GPIO controllers in the R8A77970 device tree.
Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
Thanks, applied.
It doesn't build w/o PFC support (and I thought I mde it clearin the cover
letter), so please eith
The entities provide a single .configure operation which configures the
object into the target display list, based on the vsp1_entity_params
selection.
This restricts us to a single function prototype for both static
configuration (the pre-stream INIT stage) and the dynamic runtime stages
for both
Each display list allocates a body to store register values in a dma
accessible buffer from a dma_alloc_wc() allocation. Each of these
results in an entry in the TLB, and a large number of display list
allocations adds pressure to this resource.
Reduce TLB pressure on the IPMMUs by allocating mult
The display list originally allocated a body of 256 entries to store all
of the register lists required for each frame.
This has now been separated into fragments for constant stream setup, and
runtime updates.
Empirical testing shows that the body0 now uses a maximum of 41
registers for each fra
Adapt the dl->body0 object to use an object from the body pool. This
greatly reduces the pressure on the TLB for IPMMU use cases, as all of
the lists use a single allocation for the main body.
The CLU and LUT objects pre-allocate a pool containing three bodies,
allowing a userspace update before t
Extend the display list body with a reference count, allowing bodies to
be kept as long as a reference is maintained. This provides the ability
to keep a cached copy of bodies which will not change, so that they can
be re-applied to multiple display lists.
Signed-off-by: Kieran Bingham
---
This
We are now able to configure a pipeline directly into a local display
list body. Take advantage of this fact, and create a cacheable body to
store the configuration of the pipeline in the video object.
vsp1_video_pipeline_run() is now the last user of the pipe->dl object.
Convert this function to
Currently the entities store their configurations into a display list.
Adapt this such that the code can be configured into a body directly,
allowing greater flexibility and control of the content.
All users of vsp1_dl_list_write() are removed in this process, thus it
too is removed.
A helper, vs
Throughout the codebase, the term 'fragment' is used to represent a
display list body. This term duplicates the 'body' which is already in
use.
The datasheet references these objects as a body, therefore replace all
mentions of a fragment with a body, along with the corresponding
pluralised terms.
The body write function relies on the code never asking it to write more
than the entries available in the list.
Currently with each list body containing 256 entries, this is fine, but
we can reduce this number greatly saving memory. In preparation of this
add a level of protection to catch any bu
Each display list currently allocates an area of DMA memory to store register
settings for the VSP1 to process. Each of these allocations adds pressure to
the IPMMU TLB entries.
We can reduce the pressure by pre-allocating larger areas and dividing the area
across multiple bodies represented as a
On Fri, Nov 17, 2017 at 11:41:28AM +0100, Ulrich Hecht wrote:
> Signed-off-by: Ulrich Hecht
> ---
> Documentation/devicetree/bindings/net/can/rcar_can.txt | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt
On Thu, Nov 16, 2017 at 06:22:49PM +, Fabrizio Castro wrote:
> Add compatible strings for r8a7743 and r8a7745. No driver change
> is needed as "renesas,rcar-gen2-vin" will activate the right code.
> However, it is good practice to document compatible strings for the
> specific SoC as this allow
On Thu, Nov 16, 2017 at 06:22:48PM +, Fabrizio Castro wrote:
> Change the sorting of the part numbers from descending to ascending to
> match with other documentation.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Simon Horman
Hi Laurent,
Just a query on your bikeshedding here.
Choose your colours wisely :)
--
Kieran
On 12/09/17 20:19, Laurent Pinchart wrote:
> Hi Kieran,
>
> On Tuesday, 12 September 2017 00:16:50 EEST Kieran Bingham wrote:
>> On 17/08/17 19:13, Laurent Pinchart wrote:
>>> On Monday 14 Aug 2017 16:1
On Thu, Nov 16, 2017 at 10:43:35AM +0100, Geert Uytterhoeven wrote:
> Hi Uli,
>
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > The single SDHI controller is connected to eMMC.
> >
> > Signed-off-by: Ulrich Hecht
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r
On Thu, Nov 16, 2017 at 10:33:43AM +0100, Geert Uytterhoeven wrote:
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > Adds bindings for the R-Car D3 SoC's SDHI IP.
> >
> > Signed-off-by: Ulrich Hecht
>
> Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
On Thu, Nov 16, 2017 at 10:40:41AM +0100, Geert Uytterhoeven wrote:
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > R-Car D3 has only one SDHI controller.
> >
> > Signed-off-by: Ulrich Hecht
>
> Reviewed-by: Geert Uytterhoeven
Thanks, applied.
On Thu, Nov 16, 2017 at 10:31:31AM +0100, Geert Uytterhoeven wrote:
> Hi Uli,
>
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > No devices to add, I2C1 has an external connector only.
> >
> > Signed-off-by: Ulrich Hecht
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeve
On Thu, Nov 16, 2017 at 10:27:56AM +0100, Geert Uytterhoeven wrote:
> Hi Ulrich,
>
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > Enables EEPROM on I2C0 on the Draak board.
> >
> > Signed-off-by: Ulrich Hecht
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r8a7
On Thu, Nov 16, 2017 at 10:10:27AM +0100, Geert Uytterhoeven wrote:
> Hi Ulrich,
>
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > Defines R-Car D3 I2C controllers 0-3.
> >
> > Signed-off-by: Ulrich Hecht
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r8a77995.
On Wed, Nov 15, 2017 at 04:25:09PM +0100, Ulrich Hecht wrote:
> Tested on Draak.
>
> Signed-off-by: Ulrich Hecht
> ---
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
Hi Ulrich,
there seem to be some review comments for this patch.
I would like you to addr
On Thu, Nov 16, 2017 at 09:41:23AM +0100, Geert Uytterhoeven wrote:
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > Differs from other Gen3 SoCs in that each controller only supports eight
> > channels.
> >
> > Signed-off-by: Ulrich Hecht
>
> Reviewed-by: Geert Uytterhoeven
Thanks
On Thu, Nov 16, 2017 at 09:40:33AM +0100, Geert Uytterhoeven wrote:
> On Wed, Nov 15, 2017 at 4:25 PM, Ulrich Hecht
> wrote:
> > R8A77995's SYS-DMAC is R-Car Gen3-compatible.
> >
> > Signed-off-by: Ulrich Hecht
>
> Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
On Wed, Nov 15, 2017 at 11:55:57AM +0100, Jacopo Mondi wrote:
> Add Capture Engine Unit (CEU) node to device tree.
Other patches in this series (which are not for my tree) appear
to warrant updating. Accordingly I am marking this patch as
"Changes Requested" and am expecting it to be reposted at s
On Wed, Nov 15, 2017 at 05:15:58PM +0100, Geert Uytterhoeven wrote:
> On Mon, Nov 13, 2017 at 10:23 PM, Sergei Shtylyov
> wrote:
> > Specify EtherAVB PHY IRQ in the Eagle board's device tree, now that we
> > have the GPIO support (previously phylib had to resort to polling).
> >
> > Signed-off-b
On Wed, Nov 15, 2017 at 05:12:30PM +0100, Geert Uytterhoeven wrote:
> On Mon, Nov 13, 2017 at 10:23 PM, Sergei Shtylyov
> wrote:
> > Describe all 6 GPIO controllers in the R8A77970 device tree.
> >
> > Signed-off-by: Sergei Shtylyov
>
> Reviewed-by: Geert Uytterhoeven
Thanks, applied.
On Wed, Nov 15, 2017 at 05:52:29PM +0100, Geert Uytterhoeven wrote:
> On Wed, Nov 8, 2017 at 2:09 PM, Vladimir Barinov
> wrote:
> > ULCB-KF has a USB2.0 dual-role channel (CN13).
> > This adds dr_mode property for USB2.0 channel 0 (EHCI/OHCI and HS-USB)
> > as "otg".
> >
> > Signed-off-by: Vladimi
On Wed, Nov 15, 2017 at 05:36:21PM +0100, Geert Uytterhoeven wrote:
> Hi Vladimir,
>
> On Wed, Nov 8, 2017 at 1:21 PM, Vladimir Barinov
> wrote:
> > This supports USB2 PHY channel #0 on ULCB Kingfisher board
> >
> > The dedicated USB0_PWEN pin is used to control CN13 VBUS source from U43
> > powe
On Wed, Nov 15, 2017 at 4:58 PM, Niklas Söderlund
wrote:
> Hi Rob,
>
> Thanks for your feedback, much appreciated!
>
> On 2017-11-15 14:02:26 -0600, Rob Herring wrote:
>> On Sat, Nov 11, 2017 at 01:38:11AM +0100, Niklas Söderlund wrote:
>> > Document the devicetree bindings for the CSI-2 inputs av
Hi Laurent,
On 12/09/17 20:18, Laurent Pinchart wrote:
> Hi Kieran,
>
> On Tuesday, 12 September 2017 00:42:09 EEST Kieran Bingham wrote:
>> On 17/08/17 18:58, Laurent Pinchart wrote:
>>> On Monday 14 Aug 2017 16:13:29 Kieran Bingham wrote:
Currently the entities store their configurations i
On Fri, Nov 10, 2017 at 02:26:05PM +0100, Simon Horman wrote:
> This series adds DT nodes for IPMMU instances on r8a7796 together with
> connections to various r8a7796 on-chip devices such as Audio-DMAC, SYS-DMAC,
> Ethernet-AVB and a bunch of multimedia devices that make use of FCP.
>
> With thes
On Fri, Nov 10, 2017 at 02:25:17PM +0100, Simon Horman wrote:
> This series adds DT nodes for IPMMU instances on r8a7795 together with
> connections to various r8a7795 on-chip devices such as Audio-DMAC, SYS-DMAC,
> Ethernet-AVB, SATA and a bunch of multimedia devices that make use of FCP.
>
> Wit
On Wed, Nov 15, 2017 at 03:29:55PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Fri, Nov 10, 2017 at 2:25 PM, Simon Horman
> wrote:
> > From: Magnus Damm
> >
> > Add r8a7795 IPMMU nodes and keep all disabled by default.
> >
> > This includes all IPMMU devices for r8a7795 ES2.0. Those
> >
On Wed, Nov 15, 2017 at 03:41:14PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Fri, Nov 10, 2017 at 2:26 PM, Simon Horman
> wrote:
> > From: Magnus Damm
> >
> > Add r8a7796 IPMMU nodes and keep all disabled by default.
> >
> > Signed-off-by: Magnus Damm
> > Signed-off-by: Simon Horman
On Fri, Nov 17, 2017 at 11:41 AM, Ulrich Hecht
wrote:
> This patch adds CAN FD[0-1] pinmux support to the r8a77995 SoC.
>
> Signed-off-by: Ulrich Hecht
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.16.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven
On Fri, Nov 17, 2017 at 11:41 AM, Ulrich Hecht
wrote:
> This patch adds CAN[0-1] pinmux support to the r8a77995 SoC.
>
> Signed-off-by: Ulrich Hecht
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.16.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven --
On 11/11/17 01:25, Niklas Söderlund wrote:
> A V4L2 driver for Renesas R-Car MIPI CSI-2 receiver. The driver
> supports the rcar-vin driver on R-Car Gen3 SoCs where separate CSI-2
> hardware blocks are connected between the video sources and the video
> grabbers (VIN).
>
> Driver is based on a pro
On 11/11/17 01:38, Niklas Söderlund wrote:
> The driver registers the video device from the async complete callback
> and unregistered in the async unbind callback. This creates problems if
> if the subdevice is bound, unbound and later rebound. The second time
"unbound and later rebound": that's
On 11/11/17 01:38, Niklas Söderlund wrote:
> The procedure to start or stop streaming using the non-MC single
> subdevice and the MC graph and multiple subdevices are quite different.
> Create a new function to abstract which method is used based on which
> mode the driver is running in and add log
On 11/11/17 01:38, Niklas Söderlund wrote:
> On Gen3 the CSI-2 routing is controlled by the VnCSI_IFMD register. One
> feature of this register is that it's only present in the VIN0 and VIN4
> instances. The register in VIN0 controls the routing for VIN0-3 and the
> register in VIN4 controls routin
On 11/11/17 01:38, Niklas Söderlund wrote:
> Each Gen3 SoC has a limited set of predefined routing possibilities for
> which CSI-2 device and virtual channel can be routed to which VIN
> instance. Prepare to store this information in the struct rvin_info.
>
> Signed-off-by: Niklas Söderlund
Revi
On 11/11/17 01:38, Niklas Söderlund wrote:
> Add the ability to process media device link change request. Link
> enabling is a bit complicated on Gen3, whether or not it's possible to
> enable a link depends on what other links already are enabled. On Gen3
> the 8 VINs are split into two subgroup's
Hi Laurent,
On 16/11/17 01:33, Laurent Pinchart wrote:
> Device unplug being asynchronous, it naturally races with operations
> performed by userspace through ioctls or other file operations on video
> device nodes.
>
> This leads to potential access to freed memory or to other resources
> during
On 11/17/2017 12:06 PM, Geert Uytterhoeven wrote:
Despite commit 55020c8056a8 ("of: Add vendor prefix for ON Semiconductor
Corp.") was made long ago, the latter commit 9f49f6dd0473 ("gpio: pca953x:
add onsemi,pca9654 id") made use of another, undocumented vendor prefix.
Ouch...
Since such pr
Adds CAN controller nodes for r8a77995.
Based on a patch for r8a7796 by Chris Paterson.
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 32 +++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arc
This patch adds CAN[0-1] pinmux support to the r8a77995 SoC.
Signed-off-by: Ulrich Hecht
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77995
Adds external CAN clock node for r8a77995. This clock can be used as
fCAN clock of CAN and CAN FD controller.
Based on a patch for r8a7796 by Chris Paterson.
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch
Adds CAN FD controller node for r8a77995.
Based on a patch for r8a7796 by Chris Paterson.
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arch/ar
This patch adds CAN FD[0-1] pinmux support to the r8a77995 SoC.
Signed-off-by: Ulrich Hecht
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
in
Signed-off-by: Ulrich Hecht
---
Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
index 93c
Hi!
Here's CAN and CAN FD support for the R-Car D3. This is a by-the-datasheet
implementation, with the datasheet missing some bits, namely the pin map.
I filled in the gaps with frog DNA^W^W^Wby deducing the information from
pin numbers already in the PFC driver, so careful scrutiny is advised.
Signed-off-by: Ulrich Hecht
---
Documentation/devicetree/bindings/net/can/rcar_can.txt | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt
b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index 06bb7cc..
Hi Wolfram,
On Wed, Nov 15, 2017 at 03:32:21PM +0100, Wolfram Sang wrote:
> The datasheet was a bit vague, but after consultation with HW designers,
> we came to the conclusion that we should set the SCP bit always when
> dealing only with the ICE bit. A set SCP bit is ignored, and thus fine,
> a
Hi Sakari!
On Fri, Nov 17, 2017 at 02:36:51AM +0200, Sakari Ailus wrote:
> Hi Jacopo,
>
> On Wed, Nov 15, 2017 at 03:25:11PM +0100, jacopo mondi wrote:
> > Hi Sakari,
> >thanks for review!
>
> You're welcome!
>
> > On Wed, Nov 15, 2017 at 02:45:51PM +0200, Sakari Ailus wrote:
> > > Hi Jacopo,
Hi Geert,
On Wed, Nov 15, 2017 at 02:13:43PM +0100, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Wed, Nov 15, 2017 at 11:55 AM, Jacopo Mondi
> wrote:
> > Rename CEU clock to match the new platform driver name used in Migo-R.
> >
> > There are no other sh7722 based devices Migo-R apart, so we can
Hi Sakari!
On Fri, Nov 17, 2017 at 02:43:15AM +0200, Sakari Ailus wrote:
> Hi Jacopo,
>
> On Wed, Nov 15, 2017 at 11:56:01AM +0100, Jacopo Mondi wrote:
> >
[snip]
> > +#include
> > #include
> > #include
> > #include
> > @@ -25,8 +26,8 @@
> > #include
> >
> > #include
> > -#include
>
Hi Sergei,
On Thu, Nov 16, 2017 at 9:18 PM, Sergei Shtylyov
wrote:
> Despite commit 55020c8056a8 ("of: Add vendor prefix for ON Semiconductor
> Corp.") was made long ago, the latter commit 9f49f6dd0473 ("gpio: pca953x:
> add onsemi,pca9654 id") made use of another, undocumented vendor prefix.
Ou
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