Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

> > + { .compatible = "renesas,sdhi-r8a77965", .data = > > _rcar_gen3_compatible, }, Do we need this line... > > { .compatible = "renesas,rcar-gen3-sdhi", .data = > > _rcar_gen3_compatible, }, ... with this generic fallback in place? > > @@ -276,6 +277,7 @@ static void > >

Re: [PATCH 3/5] tty: serial: sh-sci: Hide earlycon config question

On Sun, Apr 15, 2018 at 2:09 PM, Rich Felker wrote: > On Sun, Apr 15, 2018 at 08:58:42PM +0200, Geert Uytterhoeven wrote: >> Hi Rich, >> >> On Sun, Apr 15, 2018 at 2:34 AM, Rich Felker wrote: >> > On Thu, Nov 30, 2017 at 02:12:00PM +0100, Geert Uytterhoeven

Re: igt trouble with planes shared between multiple CRTCs (Re: [PATCH v2 0/8] R-Car DU: Support CRC calculation)

Op 01-05-18 om 10:58 schreef Maarten Lankhorst: > Hey, > > Op 30-04-18 om 16:56 schreef Daniel Vetter: >> On Mon, Apr 30, 2018 at 04:55:24PM +0200, Daniel Vetter wrote: >>> On Sat, Apr 28, 2018 at 12:07:04AM +0300, Laurent Pinchart wrote: Hi Daniel, (Removing the linux-media mailing

Re: [PATCH/RFT 3/3] arm64: dts: r8a77965: Add SDHI device nodes

On Mon, Apr 30, 2018 at 04:48:16AM +0900, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > Add SDHI nodes to the DT of the r8a77965 SoC. > > Based on several similar patches of the R8A7796 device tree > by Simon Horman . > >

Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

On Mon, Apr 30, 2018 at 04:48:15AM +0900, Yoshihiro Kaneko wrote: > From: Masaharu Hayakawa > > This patch adds r8a77965 support in SDHI. > > Signed-off-by: Masaharu Hayakawa > Signed-off-by: Yoshihiro Kaneko

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

On Mon, Apr 30, 2018 at 04:48:14AM +0900, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965 > SoC. > > Signed-off-by: Takeshi Kihara > Signed-off-by:

Re: [PATCH/RFT 0/3] mmc: renesas_sdhi: add support for r8a77965

On Mon, Apr 30, 2018 at 04:48:13AM +0900, Yoshihiro Kaneko wrote: > This series adds SDHI device support for r8a77965. > > This series is based on the next branch of Ulf Hansson's mmc tree. > > Masaharu Hayakawa (1): > mmc: renesas_sdhi: Add r8a77965 support > > Takeshi Kihara (2): >

Re: [PATCH] rcar-vin: remove generic gen3 compatible string

On Wed, Apr 25, 2018 at 01:43:21AM +0200, Niklas Söderlund wrote: > The compatible string "renesas,rcar-gen3-vin" was added before the > Gen3 driver code was added but it's not possible to use. Each SoC in the > Gen3 series require SoC specific knowledge in the driver to function. > Remove it

RE: [PATCH] irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer

Hi Rob, On 01 May 2018 14:29 Rob Herring wrote: > On Mon, Apr 23, 2018 at 02:33:06PM +0100, Phil Edworthy wrote: > > On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each > > configured to have 32 interrupt outputs, so we have a total of 96 GPIO > > interrupts. All of these are

Re: [PATCH] dt-bindings: arm: consistently name r8a77965 as M3-N

On Tue, Apr 24, 2018 at 07:54:42AM +0200, Simon Horman wrote: > There is an inconsistency between the use of M3N and M3-N. > This patch resolves this by consistently using the latter. > > Signed-off-by: Simon Horman > --- > Based on renesas-devel-20180423-v4.17-rc2 >

Re: [PATCH] irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer

On Mon, Apr 23, 2018 at 02:33:06PM +0100, Phil Edworthy wrote: > On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each > configured to have 32 interrupt outputs, so we have a total of 96 GPIO > interrupts. All of these are passed to the GPIO IRQ Muxer, which selects > 8 of the GPIO

Re: [PATCH 3/3] v4l: rcar_fdp1: Fix indentation oddities

Hi Laurent, Thanks for the fixes. On 22/04/18 11:28, Laurent Pinchart wrote: > Indentation is odd in several places, especially when printing messages > to the kernel log. Fix it to match the usual coding style. > > Signed-off-by: Laurent Pinchart

[PATCH v8 4/8] media: vsp1: Convert display lists to use new body pool

Adapt the dl->body0 object to use an object from the body pool. This greatly reduces the pressure on the TLB for IPMMU use cases, as all of the lists use a single allocation for the main body. The CLU and LUT objects pre-allocate a pool containing three bodies, allowing a userspace update before

[PATCH v8 7/8] media: vsp1: Adapt entities to configure into a body

Currently the entities store their configurations into a display list. Adapt this such that the code can be configured into a body directly, allowing greater flexibility and control of the content. All users of vsp1_dl_list_write() are removed in this process, thus it too is removed. A helper,

[PATCH v8 0/8] vsp1: TLB optimisation and DL caching

Each display list currently allocates an area of DMA memory to store register settings for the VSP1 to process. Each of these allocations adds pressure to the IPMMU TLB entries. We can reduce the pressure by pre-allocating larger areas and dividing the area across multiple bodies represented as a

[PATCH v8 3/8] media: vsp1: Provide a body pool

Each display list allocates a body to store register values in a dma accessible buffer from a dma_alloc_wc() allocation. Each of these results in an entry in the IOMMU TLB, and a large number of display list allocations adds pressure to this resource. Reduce TLB pressure on the IPMMUs by

[PATCH v8 2/8] media: vsp1: Protect bodies against overflow

The body write function relies on the code never asking it to write more than the entries available in the list. Currently with each list body containing 256 entries, this is fine, but we can reduce this number greatly saving memory. In preparation of this add a level of protection to catch any

[PATCH v8 1/8] media: vsp1: Reword uses of 'fragment' as 'body'

Throughout the codebase, the term 'fragment' is used to represent a display list body. This term duplicates the 'body' which is already in use. The datasheet references these objects as a body, therefore replace all mentions of a fragment with a body, along with the corresponding pluralised

[PATCH v8 8/8] media: vsp1: Move video configuration to a cached dlb

We are now able to configure a pipeline directly into a local display list body. Take advantage of this fact, and create a cacheable body to store the configuration of the pipeline in the video object. vsp1_video_pipeline_run() is now the last user of the pipe->dl object. Convert this function to

[PATCH v8 6/8] media: vsp1: Refactor display list configure operations

The entities provide a single .configure operation which configures the object into the target display list, based on the vsp1_entity_params selection. Split the configure function into three parts, '.configure_stream()', '.configure_frame()', and '.configure_partition()' to facilitate splitting

[PATCH v8 5/8] media: vsp1: Use reference counting for bodies

Extend the display list body with a reference count, allowing bodies to be kept as long as a reference is maintained. This provides the ability to keep a cached copy of bodies which will not change, so that they can be re-applied to multiple display lists. Signed-off-by: Kieran Bingham

[PATCH v8 01/12] ARM: Allow this header to be included by assembly files

From: Doug Berger The constants defined in this file are equally useful in assembly and C source files. The arm64 architecture version of this file allows inclusion in both assembly and C source files, so this this commit adds that capability to the arm architecture version so

[PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

As we found in sun9i-a80, CPUCFG is a collection of registers that are mapped to the SoC's signals from each individual processor core and associated peripherals. These registers are used for SMP bringup and CPU hotplugging. Signed-off-by: Mylène Josserand

[PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

The R_CPUCFG is a collection of registers needed for SMP bringup on clusters and cluster's reset. For the moment, documentation about this register is found in Allwinner's code only. Signed-off-by: Mylène Josserand Reviewed-by: Chen-Yu Tsai ---

[PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file

Move the assembly code for cluster cache enabling and resuming into an assembly file instead of having it directly in C code. Remove the CFLAGS because we are using the ARM directive "arch" instead. Signed-off-by: Mylène Josserand --- arch/arm/mach-sunxi/Makefile

[PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF

The CNTVOFF register from arch timer is uninitialized. It should be done by the bootloader but it is currently not the case, even for boot CPU because this SoC is booting in secure mode. It leads to an random offset value meaning that each CPU will have a different time, which isn't working very

[PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node

Add CCI-400 node and control-port on CPUs needed by SMP bringup. Signed-off-by: Mylène Josserand Reviewed-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++ 1 file changed, 41 insertions(+) diff

[PATCH v8 07/12] ARM: sunxi: Add initialization of CNTVOFF

Add the initialization of CNTVOFF for sun8i-a83t. For boot CPU, create a new machine that handles this function's call in an "init_early" callback. We need to initialize CNTVOFF before the arch timer's initialization otherwise, it will not be taken into account and fails to boot correctly.

[PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off

To prepare the support for sun8i-a83t, rename the macro that handles the power-off of clusters because it is different from sun9i-a80 to sun8i-a83t. The power off register for clusters are different from a80 and a83t. Signed-off-by: Mylène Josserand Acked-by:

[PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff

Now that a common function is available for CNTVOFF's initialization, let's convert shmobile-apmu code to use this function. Signed-off-by: Mylène Josserand Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven

[PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field

To prepare the support of sun8i-a83t, add a field in the smp_data structure to know if we are on sun9i-a80 or sun8i-a83t. Add also a global variable to retrieve which architecture we are having. Signed-off-by: Mylène Josserand --- arch/arm/mach-sunxi/mc_smp.c | 4

[PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T

Add the support for A83T. A83T SoC has an additional register than A80 to handle CPU configurations: R_CPUS_CFG. Information about the register comes from Allwinner's BSP driver. An important difference is the Power Off Gating register for clusters which is BIT(4) in case of SUN9I-A80 and BIT(0)

[PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

Add the use of enable-method property for SMP support which allows to handle the SMP support for this specific SoC. This commit adds enable-method properties to all CPU nodes. Signed-off-by: Mylène Josserand --- arch/arm/boot/dts/sun8i-a83t.dtsi | 8 1

[PATCH v8 00/12] Sunxi: Add SMP support on A83T

Hello everyone, This is a V8 of my series that adds SMP support for Allwinner sun8i-a83t. Based on sunxi's tree, sunxi/for-next branch. Depends on a patch from Doug Berger that allows to include the "cpu-type" header on assembly files that I included in my series (patch 01). If you have any

Re: [PATCH v2 0/5] Add R8A77980 PCIe support & some driver cleanups

On Tue, May 01, 2018 at 07:55:53AM +0200, Simon Horman wrote: > On Sun, Apr 08, 2018 at 08:57:13PM +0300, Sergei Shtylyov wrote: > > Hello! > > > > Here's a set of 5 patches against the 'pci/rcar' branch of Lorenzo > > Pieralisi's > > 'pci.git' repo. These are the changes needed for better R-Car

Re: [PATCH V5] PCI: rcar: Use runtime PM to control controller clock

On Fri, Apr 13, 2018 at 02:48:19PM +0200, Simon Horman wrote: > On Tue, Apr 10, 2018 at 06:17:04PM +0200, Marek Vasut wrote: > > On 04/10/2018 05:28 PM, Geert Uytterhoeven wrote: > > ... > > > >>> rcar_pcie_get_resources() is called while the device is > > >>> runtime-enabled/resumed, > > >>>

Re: [PATCH V3] PCI: rcar: Clean up the macros

On Tue, May 01, 2018 at 07:53:19AM +0200, Simon Horman wrote: > On Sun, Apr 08, 2018 at 08:04:31PM +0200, Marek Vasut wrote: > > This patch replaces the (1 << n) with BIT(n) and cleans up whitespace, > > no functional change. > > > > Signed-off-by: Marek Vasut > >

Re: igt trouble with planes shared between multiple CRTCs (Re: [PATCH v2 0/8] R-Car DU: Support CRC calculation)

Hey, Op 30-04-18 om 16:56 schreef Daniel Vetter: > On Mon, Apr 30, 2018 at 04:55:24PM +0200, Daniel Vetter wrote: >> On Sat, Apr 28, 2018 at 12:07:04AM +0300, Laurent Pinchart wrote: >>> Hi Daniel, >>> >>> (Removing the linux-media mailing list from CC as it is out of scope) >>> >>> You enquired

Re: [PATCH v7 8/8] media: vsp1: Move video configuration to a cached dlb

Hi Laurent, New plan ... (from the .. why didn't I think of this earlier department) On 30/04/18 18:48, Kieran Bingham wrote: > Hi Laurent, > > On 07/04/18 01:23, Laurent Pinchart wrote: >> Hi Kieran, >> >> Thank you for the patch. >> >> On Thursday, 8 March 2018 02:05:31 EEST Kieran Bingham

Re: [PATCH v3] arm64: dts: renesas: v3msk: add DU/LVDS/HDMI support

On Mon, Apr 23, 2018 at 11:45:49PM +0300, Sergei Shtylyov wrote: > Define the V3M Starter Kit board dependent part of the DU and LVDS device > nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and > Analog Devices ADV7511W HDMI transmitter... > > Based on the original (and