On Tuesday, October 16, 2018, Rob Herring wrote:
> > +Optional properties:
> > + - gpio-controller
> > +Include this in order to enable GPIO functionality. When included,
> both
> > +gpio_cells and gpio_ranges are then required.
> > + - #gpio-cells
> > +Must be 2
> > + - gpio-ranges
On Fri, Oct 05, 2018 at 10:09:51AM -0500, Chris Brandt wrote:
> Add device tree binding documentation and header file for Renesas R7S9210
> (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> ---
> .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 76
> ++
>
Describe MSIOF in the R8A779{7|8}0 device trees.
The DMA props are deliberately omitted as the MSIOF DMA doesn't work on
R8A77970 (due to IPMMU issue) and the RT-DMAC isn't supported on R8A77980.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20181015-v4.19-rc8'
Document the R-Car V3{M|H} (R8A779{7|8}0) SoCs in the Renesas MSIOF
bindings.
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'for-next' branch of Mark Brown's 'spi.git' repo.
Documentation/devicetree/bindings/spi/sh-msiof.txt |2 ++
1 file changed, 2 insertions(+)
Index:
Hi Geert,
On Tue, Oct 16, 2018 at 01:56:53PM +0200, Geert Uytterhoeven wrote:
> Add paths for the Renesas RZ/A and RZ/N series pin controller drivers,
> as they are not under sh-pfc/, but still maintained with the other
> Renesas pin controller drivers.
>
> Signed-off-by: Geert Uytterhoeven
On Tue, Oct 16, 2018 at 01:56:53PM +0200, Geert Uytterhoeven wrote:
> Add paths for the Renesas RZ/A and RZ/N series pin controller drivers,
> as they are not under sh-pfc/, but still maintained with the other
> Renesas pin controller drivers.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by:
Add paths for the Renesas RZ/A and RZ/N series pin controller drivers,
as they are not under sh-pfc/, but still maintained with the other
Renesas pin controller drivers.
Signed-off-by: Geert Uytterhoeven
---
To be queued in sh-pfc-for-v4.21.
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
When submitting a DMA request fails, the driver is supposed to fall back
to PIO. However, this never really worked due to various reasons
(sh-sci driver issues and dmaengine framework limitations).
There are three places where DMA submission can fail, and the driver
should fall back to PIO:
1.
Some VIN channels support less than 24 lanes. As union vin_data always
consumes space for 24 lanes, this wastes memory.
Hence introduce new smaller unions vin_data12 and vin_data16, to
accommodate VIN channels with only 12 or 16 lanes.
This reduces the static pin controller driver size by 320
CC pinctrl
On Tue, Oct 16, 2018 at 12:33 PM Laurent Pinchart
wrote:
> Geert Uytterhoeven has long taken over and I'm not involved anymore with
> the Renesas pinctrl driver. Remove myself from the maintainers list.
>
> Signed-off-by: Laurent Pinchart
Thank you, will queue in sh-pfc-for-v4.21.
On Mon, Oct 15, 2018 at 01:57:13PM -0500, Rob Herring wrote:
> On Fri, Oct 12, 2018 at 01:21:14PM +0200, Thierry Reding wrote:
> > On Mon, Oct 01, 2018 at 10:57:39PM +0300, Sergei Shtylyov wrote:
> > > Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas R-Car PWM
> > > bindings.
Geert Uytterhoeven has long taken over and I'm not involved anymore with
the Renesas pinctrl driver. Remove myself from the maintainers list.
Signed-off-by: Laurent Pinchart
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins
capable of switching voltage, also add pin groups and functions
for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1
bit of the POC Control Register is used to control each interface.
Signed-off-by: Fabrizio Castro
Reviewed-by:
Hi Shimoda-San,
Thanks for the feedback.
>
> Subject: RE: USB2.0 blocks on RZ/G1C
> >
> > Hello Shimoda-San and all,
> >
> > RZ/G1C USB2.0 host/function controller has the below features
> > compared to R-Car Gen2/Gen3 USB2.0 block
> >
> > 1) It has a shared pll reset register for
Hi Phil,
On Tue, Oct 16, 2018 at 08:04:53AM +, Phil Edworthy wrote:
> Hi Jacopo,
>
> On 15 October 2018 16:12 jacopo mondi wrote:
> > On Mon, Oct 15, 2018 at 04:01:47PM +0100, Phil Edworthy wrote:
> > > This fixes the check for unused mdio bus setting and the following
> > > static checker
Hi Jacopo,
On 15 October 2018 16:12 jacopo mondi wrote:
> On Mon, Oct 15, 2018 at 04:01:47PM +0100, Phil Edworthy wrote:
> > This fixes the check for unused mdio bus setting and the following
> > static checker warning:
> > drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select()
> > warn:
Hi Niklas,
On Tue, Oct 16, 2018 at 3:39 AM Niklas Söderlund
wrote:
> From: Niklas Söderlund
> While looking at the Renesas BSP kernel I found patches which improves
> the state of the hardware at probe and after runtime resume.
>
> Patch 1/3 make sure the module clock is enabled after resuming
This patch adds/enables USB2.0 peripheral for R-Car [DE]3 boards.
So, the default mode on each board is:
- R-Car D3 Draak board (has a type-A connector) = host.
- R-Car E3 Ebisu board (has a type-B micro connector) = peripheral.
Signed-off-by: Yoshihiro Shimoda
---
Changed from v1:
- Revise
This patch revises the reg size of each hsusb device node for
r8a7795, r8a7796 and r8a77965.
Reported-by: Biju Das
Fixes: d2422e108812 ("arm64: dts: r8a7795: Add HSUSB device node")
Fixes: 4725f2b88057 ("arm64: dts: renesas: r8a7795: add hsusb ch3 device node")
Fixes: b9535853777f ("arm64: dts:
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