Re: [PATCH] pinctrl: sh-pfc: r8a7795-es1: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D

Hi Kaneko-san, On Thu, Nov 16, 2017 at 4:16 AM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] > value when STP_ISEN_1_D pin function is selected for IPSR16 bit[27:24]. > > This is a correction to the incorrect implementati

[PATCH] pinctrl: sh-pfc: r8a7795-es1: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D

From: Takeshi Kihara This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] value when STP_ISEN_1_D pin function is selected for IPSR16 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7795 SoC specification of R-Car Gen3 Ha