On Monday, January 30, 2017, Laurent Pinchart wrote:
> > It depends on the actual hardware: while per-pin settings are suitable
> > for SoCs that have per-pin hardware configuration (e.g. RZ/A1), it's
> > not suitable for SoCs where that's not the case, and where the
> > hardware has group-wise
Hi Geert,
On Monday 30 Jan 2017 17:08:11 Geert Uytterhoeven wrote:
> On Mon, Jan 30, 2017 at 2:51 PM, Linus Walleij wrote:
> > On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
> >> after having discussed in great detail the RZ series per-pin PFC
> >> hardware peculiarities, this is a proposal
Hi Tony,
On 30/01/2017 16:53, Tony Lindgren wrote:
* Linus Walleij [170130 05:53]:
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
after having discussed in great detail the RZ series per-pin PFC hardware
peculiarities, this is a
* Linus Walleij [170130 05:53]:
> On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi
> wrote:
>
> >after having discussed in great detail the RZ series per-pin PFC hardware
> > peculiarities, this is a proposal for a possible pin-based pin
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
>after having discussed in great detail the RZ series per-pin PFC hardware
> peculiarities, this is a proposal for a possible pin-based pin controller
> driver for SoC devices of Renesas RZ family.
>
> This RFC
Hi Jacopo,
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
>after having discussed in great detail the RZ series per-pin PFC hardware
> peculiarities, this is a proposal for a possible pin-based pin controller
> driver for SoC devices of Renesas RZ family.
Hi Jacopo,
Thanks for the patches.
On Wednesday, January 25, 2017, Jacopo Mondi wrote:
> Right now, the only "SoC" module support implemented is for RZ/A1H (Genmai
> and GR-Peach boards).
I'm going to give it a try on the RZ/A1 RSK board.
> I have tested the correctness of mux settings