Re: [PATCH v3 2/3] mmc: tmio-mmc: add support for 32bit data port

[Wolfram Sang]

> For the VERSION register, the low byte is the version of the IP, but
> the upper byte is a number that the design group that made the part

I know. It is just that I haven't seen this one "in the wild" so far.

> > This SWAP register exists on R-Car as well. Out of curiosity, what is the
> > register value of 0xE804E0E4?
> 
> 0xE804E0E4 = 0x0001
> 
> So...something is there!

I am quite convinced there is this BUSWIDTH register. If you are
interested, try setting this to 0 and see if it works without the 32 bit
register patches.



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Re: [PATCH/RFC 4/4] soc: renesas: Identify SoC and register with the SoC bus

[Arnd Bergmann]

On Friday, October 21, 2016 8:16:00 PM CEST Geert Uytterhoeven wrote:
> On Wed, Oct 19, 2016 at 12:59 PM, Arnd Bergmann  wrote:
> > On Wednesday, October 19, 2016 10:02:57 AM CEST Geert Uytterhoeven wrote:
> >> On Mon, Oct 10, 2016 at 4:23 PM, Arnd Bergmann  wrote:
> > I'd prefer seeing a separate soc driver for that one.
> >> Some SoCs have only CCCR, others have only PRR, some have both.
> >> On some SoCs one of them can be accessed from the RealTime CPU
> >> core (SH) only.
> >> On some SoCs the register is not documented, but present.
> >> If the PRR exists, it's a better choice, as it contains additional 
> >> information
> >> in the high order bits (representing the presence of each big (CA15/CA57),
> >> little (CA7/CA53), and RT (CR7) CPU core). Currently we don't use that
> >> information, though.
> >>
> >> Grouping them in some other way means we would loose the family name,
> >> which is exposed through soc_dev_attr->family.
> >> The usefulness of family names is debatable though, as this is more an
> >> issue of marketing business.
> >
> > How about having a table to look up the family name by the value
> > of the PRR or CCCR then?
> 
> Unfortunately there exist SoCs from different families using the same
> product ID.
> 
> And different SoCs from the same family may have a revision register
> or not (e.g. R-Car H1 has, M1A hasn't).

Is this something we expect to see more of in the future, or can
we expect future chips to handle this more consistently?

> > How about this:
> >
> > The driver could report the hardcoded strings for the SoCs it already
> > knows about (you have the table anyway) and not report the revision
> > unless there is a regmap containing the CCCR or the PRR, in which
> > case you use that. Future SoCs will provide the PRR (I assume
> > CCCR is only used on the older ones) through a syscon regmap
> > that we can use to find out the exact revision as well.
> >
> > The existing DT files can gain the syscon device so you can report
> > the revision on those machines as well, unless you use an old DTB.
> 
> Hmm... That means that if we have to add a driver quirk to distinguish
> between different revisions of the same SoC, we have to update the
> DTB anyway, to add the CCCR/PRR device node.
> We might as well just change the compatible value in that DTB for the
> device that needs the quirk. Which is what we'd like to avoid in the
> first place.

Do you have a specific example in mind? If this is only a theoretical
problem, we can worry about it when we get there, and then decide
if we add a hardcoded register after all.

> > Why not just drop all the #ifdef here? There should be very little
> > overhead in size, especially if all the data is __initconst.
> 
> It still saves ca. 3 KiB for a kernel for a single SoC.

Fair enough, that is more than I was expecting from looking at the
source. It's probably the of_device_id structures for the most part.

Please just add the __maybe_unused then, to save us a patch in case
we make -Wunused-const the default in the future.

Arnd

Re: [PATCH] clk: fix link error for rcar-gen2

[Arnd Bergmann]

On Friday, October 21, 2016 8:01:49 PM CEST Geert Uytterhoeven wrote:
> > diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
> > index 90dd0db7d9c6..762d122eddec 100644
> > --- a/drivers/clk/renesas/Makefile
> > +++ b/drivers/clk/renesas/Makefile
> > @@ -4,11 +4,7 @@ obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o 
> > clk-div6.o
> >  obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
> >  obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
> >  obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
> > -obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
> > -obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
> > -obj-$(CONFIG_ARCH_R8A7792) += clk-rcar-gen2.o clk-div6.o
> > -obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
> > -obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
> > +obj-$(CONFIG_ARCH_RCAR_GEN2)   += clk-rcar-gen2.o clk-div6.o
> >  obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o 
> > rcar-gen3-cpg.o
> >  obj-$(CONFIG_ARCH_R8A7796) += r8a7796-cpg-mssr.o 
> > rcar-gen3-cpg.o
> >  obj-$(CONFIG_ARCH_SH73A0)  += clk-sh73a0.o clk-div6.o
> 
> Please don't fix it this way, as it will make it _harder_ to convert the R-Car
> Gen2 SoCs to the modern CPG/MSSR driver later.
> 

Ok, I see. How about just adding another line for r8a7743 and
dropping that again after the timer_init has been converted?

Arnd

[PATCH v4 7/7] ARM: dts: sk-rzg1m: add Ether support

[Sergei Shtylyov]

Define the SK-RZG1M board dependent part of the Ether device node.
Enable DHCP and NFS root  for the kernel booting.

Based on the original (and large) patch by Dmitry Shifrin
.

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 4:
- added Geert's tag.

Changes in version 2:
- new patch.

 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts |   15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
===
--- renesas.orig/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
+++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -20,7 +20,7 @@
};
 
chosen {
-   bootargs = "ignore_loglevel";
+   bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
 
@@ -42,3 +42,16 @@
  {
status = "okay";
 };
+
+ {
+   phy-handle = <>;
+   renesas,ether-link-active-low;
+   status = "okay";
+
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   interrupt-parent = <>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   micrel,led-mode = <1>;
+   };
+};

[PATCH v4 6/7] ARM: dts: sk-rzg1m: initial device tree

[Sergei Shtylyov]

Add the initial device  tree for the R8A7743 SoC based SK-RZG1M board.
The board has one debug serial port (SCIF0); include support for it, so
that  the serial  console  can work.

Based on the original (and large) patch by Dmitry Shifrin
.

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 4:
- refreshed the patch.

Changes in version 3:
- added Geert's tag.

 arch/arm/boot/dts/Makefile |1 
 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts |   44 +
 2 files changed, 45 insertions(+)

Index: renesas/arch/arm/boot/dts/Makefile
===
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -677,6 +677,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
+   r8a7743-sk-rzg1m.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
===
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Source for the SK-RZG1M board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743.dtsi"
+
+/ {
+   model = "SK-RZG1M";
+   compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x4000>;
+   };
+
+   memory@2 {
+   device_type = "memory";
+   reg = <2 0x 0 0x4000>;
+   };
+};
+
+_clk {
+   clock-frequency = <2000>;
+};
+
+ {
+   status = "okay";
+};

[PATCH v4 5/7] ARM: dts: r8a7743: add IRQC support

[Sergei Shtylyov]

Describe the IRQC interrupt controller in the R8A7743 device tree.

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 4:
- refreshed the patch;
- added Geert's tag.

Changes in version 3:
- updated the "clocks" property for the CPG/MSSR driver.

Changes in version 2:
- new patch.

 arch/arm/boot/dts/r8a7743.dtsi |   19 +++
 1 file changed, 19 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -62,6 +62,25 @@
 IRQ_TYPE_LEVEL_HIGH)>;
};
 
+   irqc: interrupt-controller@e61c {
+   compatible = "renesas,irqc-r8a7743", "renesas,irqc";
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   reg = <0 0xe61c 0 0x200>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   clocks = < CPG_MOD 407>;
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = 

[PATCH v4 4/7] ARM: dts: r8a7743: add Ether support

[Sergei Shtylyov]

Define the generic R8A7743 part of the Ether device node.

Based on the original (and large) patch by Dmitry Shifrin
.

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 4:
- refreshed the patch;
- added Geert's tag.

Changes in version 3:
- resolved a reject;
- updated the "clocks" property for the CPG/MSSR driver.

Changes in version 2:
- new patch.

 arch/arm/boot/dts/r8a7743.dtsi |   12 
 1 file changed, 12 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -413,6 +413,18 @@
power-domains = < R8A7743_PD_ALWAYS_ON>;
status = "disabled";
};
+
+   ether: ethernet@ee70 {
+   compatible = "renesas,ether-r8a7743";
+   reg = <0 0xee70 0 0x400>;
+   interrupts = ;
+   clocks = < CPG_MOD 813>;
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   phy-mode = "rmii";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
};
 
/* External root clock */

[PATCH v4 3/7] ARM: dts: r8a7743: add [H]SCIF{|A|B} support

[Sergei Shtylyov]

Describe [H]SCIF{|A|B} ports in the R8A7743 device tree.

Based on the original (and large) patch by Dmitry Shifrin
.

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 4:
- corrected RBNF in the patch description/subject;
- used the R-Car gen2 bindings instead of the RZ/G family ones;
- refreshed the patch;
- added Geert's tag.

Changes in version 3:
- resolved  a reject;
- updated the "clocks" properties for the CPG/MSSR driver;
- renamed the patch.

Changes in version 2:
- used  the new RZ/G family "compatible" prop values, reformatting where needed;
- fixed the size cells of the SCIFB device nodes' "reg" properties;
- changed the size cells of the "reg" properties to hexadecimal;
- indented the SCIFA1 device node's closing brace correctly
- adjusted the patch description, renamed the patch.

 arch/arm/boot/dts/r8a7743.dtsi |  261 +
 1 file changed, 261 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -152,6 +152,267 @@
#dma-cells = <1>;
dma-channels = <15>;
};
+
+   scifa0: serial@e6c4 {
+   compatible = "renesas,scifa-r8a7743",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c4 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 204>;
+   clock-names = "fck";
+   dmas = < 0x21>, < 0x22>,
+  < 0x21>, < 0x22>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scifa1: serial@e6c5 {
+   compatible = "renesas,scifa-r8a7743",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c5 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 203>;
+   clock-names = "fck";
+   dmas = < 0x25>, < 0x26>,
+  < 0x25>, < 0x26>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scifa2: serial@e6c6 {
+   compatible = "renesas,scifa-r8a7743",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c6 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 202>;
+   clock-names = "fck";
+   dmas = < 0x27>, < 0x28>,
+  < 0x27>, < 0x28>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scifa3: serial@e6c7 {
+   compatible = "renesas,scifa-r8a7743",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c7 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 1106>;
+   clock-names = "fck";
+   dmas = < 0x1b>, < 0x1c>,
+  < 0x1b>, < 0x1c>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scifa4: serial@e6c78000 {
+   compatible = "renesas,scifa-r8a7743",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c78000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 1107>;
+   clock-names = "fck";
+   dmas = < 0x1f>, < 0x20>,
+  < 0x1f>, < 0x20>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scifa5: serial@e6c8 {
+   compatible = "renesas,scifa-r8a7743",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c8 0 0x40>;
+   interrupts = ;
+   

[PATCH v4 2/7] ARM: dts: r8a7743: add SYS-DMAC support

[Sergei Shtylyov]

Describe SYS-DMAC0/1 in the R8A7743 device tree.

Based on the original (and large) patch by Dmitry Shifrin
.

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 4:
- refreshed the patch.

Changes in version 3:
- resolved a reject;
- updated the "clocks" properties for the CPG/MSSR driver.

Changes in version 2:
- added Geert's tag.

 arch/arm/boot/dts/r8a7743.dtsi |   64 +
 1 file changed, 64 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===
--- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -88,6 +88,70 @@
reg = <0 0xe618 0 0x0200>;
#power-domain-cells = <1>;
};
+
+   dmac0: dma-controller@e670 {
+   compatible = "renesas,dmac-r8a7743",
+"renesas,rcar-dmac";
+   reg = <0 0xe670 0 0x2>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14";
+   clocks = < CPG_MOD 219>;
+   clock-names = "fck";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   #dma-cells = <1>;
+   dma-channels = <15>;
+   };
+
+   dmac1: dma-controller@e672 {
+   compatible = "renesas,dmac-r8a7743",
+"renesas,rcar-dmac";
+   reg = <0 0xe672 0 0x2>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14";
+   clocks = < CPG_MOD 218>;
+   clock-names = "fck";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   #dma-cells = <1>;
+   dma-channels = <15>;
+   };
};
 
/* External root clock */

[PATCH v4 1/7] ARM: dts: r8a7743: initial SoC device tree

[Sergei Shtylyov]

The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, CPG,
and the  required clock descriptions.

Based on the original (and large) patch by Dmitry Shifrin
.

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 4:
- removed the CPU1 node, updated the patch description accordingly;
- reformatted the "interrupts" props of the GIC/timer device nodes;
- added Geert's tag.

Changes in version 3:
- changed  the R8A7743 clock header #include;
- replaced the multiple clock nodes with the single CPG node, updated the
  "clocks" property in the CPU0 node, updated the patch description.

Changes in version 2:
- added the IRQC and Ether clocks.

 arch/arm/boot/dts/r8a7743.dtsi |  115 +
 1 file changed, 115 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7743.dtsi
===
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a7743";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a15";
+   reg = <0>;
+   clock-frequency = <15>;
+   clocks = < CPG_CORE R8A7743_CLK_Z>;
+   power-domains = < R8A7743_PD_CA15_CPU0>;
+   next-level-cache = <_CA15>;
+   };
+
+   L2_CA15: cache-controller@0 {
+   compatible = "cache";
+   reg = <0>;
+   cache-unified;
+   cache-level = <2>;
+   power-domains = < R8A7743_PD_CA15_SCU>;
+   };
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   gic: interrupt-controller@f1001000 {
+   compatible = "arm,gic-400";
+   #interrupt-cells = <3>;
+   #address-cells = <0>;
+   interrupt-controller;
+   reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+   interrupts = ;
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   cpg: clock-controller@e615 {
+   compatible = "renesas,r8a7743-cpg-mssr";
+   reg = <0 0xe615 0 0x1000>;
+   clocks = <_clk>, <_extal_clk>;
+   clock-names = "extal", "usb_extal";
+   #clock-cells = <2>;
+   #power-domain-cells = <0>;
+   };
+
+   sysc: system-controller@e618 {
+   compatible = "renesas,r8a7743-sysc";
+   reg = <0 0xe618 0 0x0200>;
+   #power-domain-cells = <1>;
+   };
+   };
+
+   /* External root clock */
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overriden by the board. */
+   clock-frequency = <0>;
+   };
+
+   /* External USB clock - can be overridden by the board */
+   usb_extal_clk: usb_extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <4800>;
+   };
+
+   /* External SCIF clock */
+   scif_clk: scif {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board. */
+   clock-frequency = <0>;
+   };
+};

[PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7743 support

[Sergei Shtylyov]

Add RZ/G1M (R8A7743) Clock  Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
.

Signed-off-by: Sergei Shtylyov 
Acked-by: Rob Herring 
Reviewed-by: Geert Uytterhoeven 

---
Changes in version 3:
- exchanged  Audio-DMAC0/1  entries in r8a7743_mod_clks[];
- renamed the I2C6 entry to IICDVFS;
- fixed the comment to the INTC-SYS entry in r8a7743_crit_mod_clks[];
- removed the useless EXTAL divisor check from r8a7743_cpg_mssr_init();
- added Rob's ACK and Geert's tag.

Changes in version 2:
- documented the R8A7743 device tree binding;
- fixed whitespace errors/warnings reported by checkpatch.pl;
- used  tabs instead of spaces for indentation;
- fixed the PLL3 column name in the PLL table.

 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt |4 
 drivers/clk/renesas/Kconfig  |1 
 drivers/clk/renesas/Makefile |1 
 drivers/clk/renesas/r8a7743-cpg-mssr.c   |  264 +++
 drivers/clk/renesas/renesas-cpg-mssr.c   |6 
 drivers/clk/renesas/renesas-cpg-mssr.h   |1 
 6 files changed, 276 insertions(+), 1 deletion(-)

Index: linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===
--- linux.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,6 +13,7 @@ They provide the following functionaliti
 
 Required Properties:
   - compatible: Must be one of:
+  - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
   - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
   - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
 
@@ -22,7 +23,8 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
 clock-names
   - clock-names: List of external parent clock names. Valid names are:
-  - "extal" (r8a7795, r8a7796)
+  - "extal" (r8a7743, r8a7795, r8a7796)
+  - "usb_extal" (r8a7743)
   - "extalr" (r8a7795, r8a7796)
 
   - #clock-cells: Must be 2
Index: linux/drivers/clk/renesas/Kconfig
===
--- linux.orig/drivers/clk/renesas/Kconfig
+++ linux/drivers/clk/renesas/Kconfig
@@ -1,5 +1,6 @@
 config CLK_RENESAS_CPG_MSSR
bool
+   default y if ARCH_R8A7743
default y if ARCH_R8A7795
default y if ARCH_R8A7796
 
Index: linux/drivers/clk/renesas/Makefile
===
--- linux.orig/drivers/clk/renesas/Makefile
+++ linux/drivers/clk/renesas/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2)+= clk-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)+= clk-rz.o
 obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7743) += r8a7743-cpg-mssr.o rcar-gen2-cpg.o
 obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
Index: linux/drivers/clk/renesas/r8a7743-cpg-mssr.c
===
--- /dev/null
+++ linux/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -0,0 +1,264 @@
+/*
+ * r8a7743 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation; of the License.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A7743_CLK_OSC,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_USB_EXTAL,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL0,
+   CLK_PLL1,
+   CLK_PLL3,
+   CLK_PLL1_DIV2,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal",  CLK_EXTAL),
+   DEF_INPUT("usb_extal",  CLK_USB_EXTAL),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main",   CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+   DEF_BASE(".pll0",   CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+   DEF_BASE(".pll1",   CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+   

Re: [PATCH v6 05/07] iommu/ipmmu-vmsa: Add new IOMMU_DOMAIN_DMA ops

[Robin Murphy]

On 20/10/16 00:36, Magnus Damm wrote:
> From: Magnus Damm 
> 
> Introduce an alternative set of iommu_ops suitable for 64-bit ARM
> as well as 32-bit ARM when CONFIG_IOMMU_DMA=y. Also adjust the
> Kconfig to depend on ARM or IOMMU_DMA.
> 
> Signed-off-by: Magnus Damm 
> ---
> 
>  Changes since V5:
>  - Made domain allocation/free code more consistent - thanks Joerg!
> 
>  Changes since V4:
>  - Added Kconfig hunk to depend on ARM or IOMMU_DMA
> 
>  Changes since V3:
>  - Removed group parameter from ipmmu_init_platform_device()
> 
>  Changes since V2:
>  - Included this new patch from the following series:
>[PATCH 00/04] iommu/ipmmu-vmsa: IPMMU CONFIG_IOMMU_DMA update
>  - Use only a single iommu_ops structure with #ifdef CONFIG_IOMMU_DMA
>  - Folded in #ifdefs to handle CONFIG_ARM and CONFIG_IOMMU_DMA
>  - of_xlate() is now used without #ifdefs
>  - Made sure code compiles on both 32-bit and 64-bit ARM.
> 
>  drivers/iommu/Kconfig  |1 
>  drivers/iommu/ipmmu-vmsa.c |  122 
> +---
>  2 files changed, 115 insertions(+), 8 deletions(-)
> 
> --- 0001/drivers/iommu/Kconfig
> +++ work/drivers/iommu/Kconfig2016-10-20 08:16:40.980607110 +0900
> @@ -274,6 +274,7 @@ config EXYNOS_IOMMU_DEBUG
>  
>  config IPMMU_VMSA
>   bool "Renesas VMSA-compatible IPMMU"
> + depends on ARM || IOMMU_DMA
>   depends on ARM_LPAE
>   depends on ARCH_RENESAS || COMPILE_TEST
>   select IOMMU_API
> --- 0006/drivers/iommu/ipmmu-vmsa.c
> +++ work/drivers/iommu/ipmmu-vmsa.c   2016-10-20 08:16:48.440607110 +0900
> @@ -10,6 +10,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -22,8 +23,10 @@
>  #include 
>  #include 
>  
> +#if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
>  #include 
>  #include 
> +#endif
>  
>  #include "io-pgtable.h"
>  
> @@ -520,14 +523,6 @@ static struct iommu_domain *__ipmmu_doma
>   return >io_domain;
>  }
>  
> -static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
> -{
> - if (type != IOMMU_DOMAIN_UNMANAGED)
> - return NULL;

I *think* that if we did the initial check thus:

if (type != IOMMU_DOMAIN_UNMANAGED ||
(IS_ENABLED(CONFIG_IOMMU_DMA) && type != IOMMU_DOMAIN_DMA))
return NULL;

it shouldn't be necessary to split the function at all - we then just
wrap the {get,put}_cookie() bits in "if (type ==  IOMMU_DOMAIN_DMA)" and
in the 32-bit ARM case they just don't run as that can never be true.

> -
> - return __ipmmu_domain_alloc(type);
> -}
> -
>  static void ipmmu_domain_free(struct iommu_domain *io_domain)
>  {
>   struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
> @@ -714,6 +709,8 @@ error:
>   return ret;
>  }
>  
> +#if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
> +
>  static int ipmmu_add_device(struct device *dev)
>  {
>   struct ipmmu_vmsa_archdata *archdata;
> @@ -807,6 +804,14 @@ static void ipmmu_remove_device(struct d
>   dev->archdata.iommu = NULL;
>  }
>  
> +static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
> +{
> + if (type != IOMMU_DOMAIN_UNMANAGED)
> + return NULL;
> +
> + return __ipmmu_domain_alloc(type);
> +}
> +
>  static const struct iommu_ops ipmmu_ops = {
>   .domain_alloc = ipmmu_domain_alloc,
>   .domain_free = ipmmu_domain_free,
> @@ -821,6 +826,105 @@ static const struct iommu_ops ipmmu_ops
>   .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
>  };
>  
> +#endif /* !CONFIG_ARM && CONFIG_IOMMU_DMA */
> +
> +#ifdef CONFIG_IOMMU_DMA
> +
> +static struct iommu_domain *ipmmu_domain_alloc_dma(unsigned type)
> +{
> + struct iommu_domain *io_domain = NULL;
> +
> + switch (type) {
> + case IOMMU_DOMAIN_UNMANAGED:
> + io_domain = __ipmmu_domain_alloc(type);
> + break;
> +
> + case IOMMU_DOMAIN_DMA:
> + io_domain = __ipmmu_domain_alloc(type);
> + if (io_domain)
> + iommu_get_dma_cookie(io_domain);

Either way, this can fail (in fact if !CONFIG_IOMMU_DMA it can be relied
upon to).

Robin.

> + break;
> + }
> +
> + return io_domain;
> +}
> +
> +static void ipmmu_domain_free_dma(struct iommu_domain *io_domain)
> +{
> + switch (io_domain->type) {
> + case IOMMU_DOMAIN_DMA:
> + iommu_put_dma_cookie(io_domain);
> + /* fall-through */
> + default:
> + ipmmu_domain_free(io_domain);
> + break;
> + }
> +}
> +
> +static int ipmmu_add_device_dma(struct device *dev)
> +{
> + struct iommu_group *group;
> +
> + /* only accept devices with iommus property */
> + if (of_count_phandle_with_args(dev->of_node, "iommus",
> +"#iommu-cells") < 0)
> + return -ENODEV;
> +
> + group = iommu_group_get_for_dev(dev);
> + if (IS_ERR(group))
> + return 

Re: [PATCH v6 06/07] iommu/ipmmu-vmsa: ARM and ARM64 archdata access

[Robin Murphy]

Hi Magnus,

On 20/10/16 00:36, Magnus Damm wrote:
> From: Magnus Damm 
> 
> Not all architectures have an iommu member in their archdata, so
> use #ifdefs support build wit COMPILE_TEST on any architecture.

As an alternative to this we could now use iommu_fwspec in place of the
custom ipmmu_vmsa_archdata - that's deliberately
architecture-independent. I converted the Mediatek drivers[1] as an
example to stand separately from the big SMMU rework, as those are the
ones I'm most familiar with, but it looks like the IPMMU is a similarly
perfect fit.

Of course, that could always come afterwards as a cleanup - I wouldn't
consider it a blocker at this point - but it does look like it might
simplify some of the code being moved around in this series if it were
to be done beforehand.

Robin.

[1]:http://www.mail-archive.com/iommu@lists.linux-foundation.org/msg14577.html

> 
> Signed-off-by: Magnus Damm 
> Reviewed-by: Joerg Roedel 
> ---
> 
>  Changes since V5:
>  - None
> 
>  Changes since V4:
>  - None
> 
>  Changes since V3:
>  - New patch
> 
>  drivers/iommu/ipmmu-vmsa.c |   37 +++--
>  1 file changed, 27 insertions(+), 10 deletions(-)
> 
> --- 0012/drivers/iommu/ipmmu-vmsa.c
> +++ work/drivers/iommu/ipmmu-vmsa.c   2016-09-20 21:59:21.690607110 +0900
> @@ -70,6 +70,25 @@ static struct ipmmu_vmsa_domain *to_vmsa
>   return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
>  }
>  
> +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
> +static struct ipmmu_vmsa_archdata *to_archdata(struct device *dev)
> +{
> + return dev->archdata.iommu;
> +}
> +static void set_archdata(struct device *dev, struct ipmmu_vmsa_archdata *p)
> +{
> + dev->archdata.iommu = p;
> +}
> +#else
> +static struct ipmmu_vmsa_archdata *to_archdata(struct device *dev)
> +{
> + return NULL;
> +}
> +static void set_archdata(struct device *dev, struct ipmmu_vmsa_archdata *p)
> +{
> +}
> +#endif
> +
>  #define TLB_LOOP_TIMEOUT 100 /* 100us */
>  
>  /* 
> -
> @@ -539,7 +558,7 @@ static void ipmmu_domain_free(struct iom
>  static int ipmmu_attach_device(struct iommu_domain *io_domain,
>  struct device *dev)
>  {
> - struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
> + struct ipmmu_vmsa_archdata *archdata = to_archdata(dev);
>   struct ipmmu_vmsa_device *mmu = archdata->mmu;
>   struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
>   unsigned long flags;
> @@ -581,7 +600,7 @@ static int ipmmu_attach_device(struct io
>  static void ipmmu_detach_device(struct iommu_domain *io_domain,
>   struct device *dev)
>  {
> - struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
> + struct ipmmu_vmsa_archdata *archdata = to_archdata(dev);
>   struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
>   unsigned int i;
>  
> @@ -701,7 +720,7 @@ static int ipmmu_init_platform_device(st
>   archdata->mmu = mmu;
>   archdata->utlbs = utlbs;
>   archdata->num_utlbs = num_utlbs;
> - dev->archdata.iommu = archdata;
> + set_archdata(dev, archdata);
>   return 0;
>  
>  error:
> @@ -713,12 +732,11 @@ error:
>  
>  static int ipmmu_add_device(struct device *dev)
>  {
> - struct ipmmu_vmsa_archdata *archdata;
>   struct ipmmu_vmsa_device *mmu = NULL;
>   struct iommu_group *group;
>   int ret;
>  
> - if (dev->archdata.iommu) {
> + if (to_archdata(dev)) {
>   dev_warn(dev, "IOMMU driver already assigned to device %s\n",
>dev_name(dev));
>   return -EINVAL;
> @@ -754,8 +772,7 @@ static int ipmmu_add_device(struct devic
>* - Make the mapping size configurable ? We currently use a 2GB mapping
>*   at a 1GB offset to ensure that NULL VAs will fault.
>*/
> - archdata = dev->archdata.iommu;
> - mmu = archdata->mmu;
> + mmu = to_archdata(dev)->mmu;
>   if (!mmu->mapping) {
>   struct dma_iommu_mapping *mapping;
>  
> @@ -783,7 +800,7 @@ error:
>   if (mmu)
>   arm_iommu_release_mapping(mmu->mapping);
>  
> - dev->archdata.iommu = NULL;
> + set_archdata(dev, NULL);
>  
>   if (!IS_ERR_OR_NULL(group))
>   iommu_group_remove_device(dev);
> @@ -793,7 +810,7 @@ error:
>  
>  static void ipmmu_remove_device(struct device *dev)
>  {
> - struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
> + struct ipmmu_vmsa_archdata *archdata = to_archdata(dev);
>  
>   arm_iommu_detach_device(dev);
>   iommu_group_remove_device(dev);
> @@ -801,7 +818,7 @@ static void ipmmu_remove_device(struct d
>   kfree(archdata->utlbs);
>   kfree(archdata);
>  
> - dev->archdata.iommu = NULL;
> + set_archdata(dev, NULL);
>  }
>  
>  static struct 

Re: [PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state

[Philipp Zabel]

 A. Hi Geert,

Am Freitag, den 21.10.2016, 15:17 +0200 schrieb Geert Uytterhoeven:
> Hi Philipp, Mike, Stephen, Simon, Magnus,
>   (see questions *** below!)
> 
> Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
> state of the mode pins either by a call from the platform code, or
> directly by using a hardcoded register access. This is a bit messy, and
> creates a dependency between driver and platform code.
> 
> This patch series converts the various Renesas R-Car clock drivers
> and support code from reading the mode pin states using a hardcoded
> register access to using a new minimalistic R-Car RST driver.
> 
> All R-Car clock drivers will rely on the presence in DT of a device node
> for the RST module.  Backwards compatibility with old DTBs is retained
> only for R-Car Gen2, which has fallback code using its own private copy
> of rcar_gen2_read_mode_pins().

I think you should add a binding doc even though the DT bindings are
still trivial.

> After this, there is still one remaining user of
> rcar_gen2_read_mode_pins() left in platform code. A patch series to
> remove that user has already been posted, though ("[PATCH/RFT 0/4] ARM:
> shmobile: R-Car Gen2: Allow booting secondary CPU cores in debug mode").
> Since v3, the other user has been removed in commit 9f5ce39ddb8f68b3
> ("ARM: shmobile: rcar-gen2: Obtain extal frequency from DT").
> 
> This series consists of 5 parts:
>   A. Patches 1 and 2 add DT bindings and driver code for the R-Car RST
>  driver,
>   B. Patches 3-11 add device nodes for the RST modules to the R-Car DTS
>  files,
>   C. Patches 12-17 convert the clock drivers to call into the new R-Car
>  RST driver,
>   D. Patches 18-20 remove passing mode pin state to the clock drivers
>  from the platform code,
>   E. Patches 21-23 remove dead code from the clock drivers.
> 
> As is usually the case with moving functionality from platform code to
> DT, there are lots of hard dependencies:
>   - The DT updates in Part B can be merged as soon as the DT bindings in
> Part A have been approved,
>   - The clock driver updates in Part C depend functionally on the driver
> code in Part A, and on the DT updates in Part B,
>   - The board code cleanups in Part D depend on the clock driver updates
> in Part C,
>   - The block driver cleanups in part E depend on the board code
> cleanups in part D.
> 
> Hence to maintain the required lockstep between SoC driver, clock
> drivers, shmobile platform code, and shmobile DT, I propose to queue up
> all patches in a single branch against v4.9-rc1, and send pull requests
> to both Mike/Stephen (clock) and Simon (rest).
> 
> ***
> 
>   - Philip: While this is a driver for a reset-controller, currently it
> doesn't provide any reset-controller functionality. Hence I added it
> to drivers/soc/renesas/. Is that OK for you?

Absolutely, as long as the driver isn't even a reset controller
provider, this is the right place.

regards
Philipp

RE: [RFC 1/5] media: i2c: max2175: Add MAX2175 support

[Ramesh Shanmugasundaram]

Hi Laurent,

Thank you for the review comments.

> On Wednesday 12 Oct 2016 15:10:25 Ramesh Shanmugasundaram wrote:
> > This patch adds driver support for MAX2175 chip. This is Maxim
> > Integrated's RF to Bits tuner front end chip designed for
> > software-defined radio solutions. This driver exposes the tuner as a
> > sub-device instance with standard and custom controls to configure the
> device.
> >
> > Signed-off-by: Ramesh Shanmugasundaram
> >  ---
> >  .../devicetree/bindings/media/i2c/max2175.txt  |   60 +
> >  drivers/media/i2c/Kconfig  |4 +
> >  drivers/media/i2c/Makefile |2 +
> >  drivers/media/i2c/max2175/Kconfig  |8 +
> >  drivers/media/i2c/max2175/Makefile |4 +
> >  drivers/media/i2c/max2175/max2175.c| 1624
> +
> >  drivers/media/i2c/max2175/max2175.h|  124 ++
> >  7 files changed, 1826 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/i2c/max2175.txt
> >  create mode 100644 drivers/media/i2c/max2175/Kconfig  create mode
> > 100644 drivers/media/i2c/max2175/Makefile
> >  create mode 100644 drivers/media/i2c/max2175/max2175.c
> >  create mode 100644 drivers/media/i2c/max2175/max2175.h
> >
> > diff --git a/Documentation/devicetree/bindings/media/i2c/max2175.txt
> > b/Documentation/devicetree/bindings/media/i2c/max2175.txt new file
> > mode
> > 100644
> > index 000..2250d5f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/i2c/max2175.txt
> > @@ -0,0 +1,60 @@
> > +Maxim Integrated MAX2175 RF to Bits tuner
> > +-
> > +
> > +The MAX2175 IC is an advanced analog/digital hybrid-radio receiver
> > +with RF to Bits(r) front-end designed for software-defined radio
> solutions.
> > +
> > +Required properties:
> > +
> > +- compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner.
> > +- clocks: phandle to the fixed xtal clock.
> > +- clock-names: name of the fixed xtal clock.
> > +- port: video interface child port node of a tuner that defines the
> > +local
> 
> As Rob pointed out in his review of patch 3/5, this isn't video.

Agreed & corrected.

> 
> > +  and remote endpoints. The remote endpoint is assumed to be an SDR
> > + device  that is capable of receiving the digital samples from the
> tuner.
> > +
> > +Optional properties:
> > +
> > +- maxim,slave : empty property indicates this is a slave of
> another
> > +master tuner. This is used to define two tuners in
> > +diversity mode (1 master, 1 slave). By default each
> > +tuner is an individual master.
> 
> Would it be useful to make that property a phandle to the master tuner, to
> give drivers a way to access the master ? I haven't checked whether there
> could be use cases for that.

As of now, I cannot find any use case for it from the datasheet. In future, we 
could add if such need arise.

> 
> > +- maxim,refout-load: load capacitance value (in pF) on reference output
> > +drive level. The mapping of these load values to
> > +respective bit values are given below.
> > +0 - Reference output disabled
> > +1 - 10pF load
> > +2 - 20pF load
> > +3 - 30pF load
> > +4 - 40pF load
> > +5 - 60pF load
> > +6 - 70pF load
> 
> As Geert pointed out, you can simply specify the value in pF.

Agreed & corrected.

> 
> > +
> > +Example:
> > +
> > +
> > +Board specific DTS file
> > +
> > +/* Fixed XTAL clock node */
> > +maxim_xtal: maximextal {
> > +   compatible = "fixed-clock";
> > +   #clock-cells = <0>;
> > +   clock-frequency = <36864000>;
> > +};
> > +
> > +/* A tuner device instance under i2c bus */
> > +max2175_0: tuner@60 {
> > +   #clock-cells = <0>;
> 
> Is the tuner a clock provider ? If it isn't you don't need this property.

Thanks. It's a copy/paste mistake :-(. Corrected.

> 
> > +   compatible = "maxim,max2175";
> > +   reg = <0x60>;
> > +   clocks = <_xtal>;
> > +   clock-names = "xtal";
> > +   maxim,refout-load = <10>;
> > +
> > +   port {
> > +   max2175_0_ep: endpoint {
> > +   remote-endpoint = <_rx_v4l2_sdr_device>;
> > +   };
> > +   };
> > +
> > +};
> 
> [snip]
> 
> > diff --git a/drivers/media/i2c/max2175/Makefile
> > b/drivers/media/i2c/max2175/Makefile new file mode 100644 index
> > 000..9bb46ac
> > --- /dev/null
> > +++ b/drivers/media/i2c/max2175/Makefile
> > @@ -0,0 +1,4 @@
> > +#
> > +# Makefile for Maxim RF to Bits tuner device #
> > +obj-$(CONFIG_SDR_MAX2175) += max2175.o
> 
> If there's a single source file you might want to move it to
> drivers/media/i2c/.

MAX2175 is huge with lot more modes and functionality. When more modes are 
added (it's pre-set hex values), 

Re: [PATCH v3 02/10] v4l: ctrls: Add deinterlacing mode control

[Hans Verkuil]

On 09/08/16 00:25, Laurent Pinchart wrote:

The menu control selects the operation mode of a video deinterlacer. The
menu entries are driver specific.

Signed-off-by: Laurent Pinchart 
---
 Documentation/media/uapi/v4l/extended-controls.rst | 4 
 drivers/media/v4l2-core/v4l2-ctrls.c   | 2 ++
 include/uapi/linux/v4l2-controls.h | 1 +
 3 files changed, 7 insertions(+)

diff --git a/Documentation/media/uapi/v4l/extended-controls.rst 
b/Documentation/media/uapi/v4l/extended-controls.rst
index 1f1518e4859d..8e6314e23cd3 100644
--- a/Documentation/media/uapi/v4l/extended-controls.rst
+++ b/Documentation/media/uapi/v4l/extended-controls.rst
@@ -4250,6 +4250,10 @@ Image Process Control IDs
 test pattern images. These hardware specific test patterns can be
 used to test if a device is working properly.

+``V4L2_CID_DEINTERLACING_MODE (menu)``
+The video deinterlacing mode (such as Bob, Weave, ...). The menu items are
+driver specific.
+


I'm fine with the patch but I wonder where these modes will be documented.
I know that some of those modes will be hard to document since the HW docs
might give little or no information, but even that is useful information to
have.

We now have driver-specific documentation as part of the kernel docs, so I
would suggest that that is a good place. If we do that, then this control
documentation should refer there.

For this patch:

Acked-by: Hans Verkuil 

BUT: it can't be merged without an actual driver that uses this, and as
I mentioned on irc I didn't see a patch for that yet.

Regards,

Hans



 .. _dv-controls:

diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c 
b/drivers/media/v4l2-core/v4l2-ctrls.c
index adc2147fcff7..47001e25fd9e 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -885,6 +885,7 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_LINK_FREQ:return "Link Frequency";
case V4L2_CID_PIXEL_RATE:   return "Pixel Rate";
case V4L2_CID_TEST_PATTERN: return "Test Pattern";
+   case V4L2_CID_DEINTERLACING_MODE:   return "Deinterlacing Mode";

/* DV controls */
/* Keep the order of the 'case's the same as in v4l2-controls.h! */
@@ -1058,6 +1059,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum 
v4l2_ctrl_type *type,
case V4L2_CID_DV_RX_RGB_RANGE:
case V4L2_CID_DV_RX_IT_CONTENT_TYPE:
case V4L2_CID_TEST_PATTERN:
+   case V4L2_CID_DEINTERLACING_MODE:
case V4L2_CID_TUNE_DEEMPHASIS:
case V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL:
case V4L2_CID_DETECT_MD_MODE:
diff --git a/include/uapi/linux/v4l2-controls.h 
b/include/uapi/linux/v4l2-controls.h
index b6a357a5f053..0d2e1e01fbd5 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -892,6 +892,7 @@ enum v4l2_jpeg_chroma_subsampling {
 #define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 1)
 #define V4L2_CID_PIXEL_RATE(V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 2)
 #define V4L2_CID_TEST_PATTERN  (V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 3)
+#define V4L2_CID_DEINTERLACING_MODE(V4L2_CID_IMAGE_PROC_CLASS_BASE 
+ 4)


 /*  DV-class control IDs defined by V4L2 */

RE: [PATCH v3 2/3] mmc: tmio-mmc: add support for 32bit data port

[Chris Brandt]

> > > * Does it have a version register (CTL_VERSION)? If so, what does it
> > >   say?
> >
> > 0x820B
> 
> Okay, this is a version I have not seen before.

The SDHI IP came from the SH7269 (SH-2A device).

For the VERSION register, the low byte is the version of the IP, but the upper 
byte is a number that the design group that made the part gives it any time 
they make a change. So, since this IP was from a SH2A team, the numbering might 
look different than what the SH4A or R-Car teams have used in the past.



> This SWAP register exists on R-Car as well. Out of curiosity, what is the
> register value of 0xE804E0E4?

0xE804E0E4 = 0x0001

So...something is there!



Chris

[PATCH v4 10/23] arm64: renesas: r8a7795 dtsi: Add device node for RST module

[Geert Uytterhoeven]

Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - Use "renesas,-rst" instead of "renesas,rst-",
  - Drop "syscon" compatible value,

v2:
  - New.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 8c15040f2540d63a..625dda713548da78 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -321,6 +321,11 @@
#power-domain-cells = <0>;
};
 
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a7795-rst";
+   reg = <0 0xe616 0 0x0200>;
+   };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7795-sysc";
reg = <0 0xe618 0 0x0400>;
-- 
1.9.1

Re: [PATCH 1/6] video: of: Constify node argument to display timing functions

[Tomi Valkeinen]

On 04/10/16 15:31, Laurent Pinchart wrote:
> The node pointer passed to the display timing functions is never
> modified, make it const.
> 
> Signed-off-by: Laurent Pinchart 
> ---
>  drivers/video/of_display_timing.c |  6 +++---
>  include/video/of_display_timing.h | 15 ---
>  2 files changed, 11 insertions(+), 10 deletions(-)
> 
> Cc: David Airlie 
> Cc: Tomi Valkeinen 

Reviewed-by: Tomi Valkeinen 

And ack for merging via drm.

 Tomi



signature.asc
Description: OpenPGP digital signature

[PATCH v4 19/23] ARM: shmobile: r8a7779: Stop passing mode pins state to clock driver

[Geert Uytterhoeven]

Now the R-Car H1 CPG clock driver obtains the state of the mode pins
from the R-Car RST driver, there's no longer a need to pass this state
explicitly. Hence we can just remove the .init_time() callback, the
generic ARM code will take care of calling of_clk_init() and
clocksource_probe().

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 arch/arm/mach-shmobile/setup-r8a7779.c | 27 ---
 1 file changed, 27 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c 
b/arch/arm/mach-shmobile/setup-r8a7779.c
index 0007ff51d180379f..0686112f243525b6 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -14,8 +14,6 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -76,30 +74,6 @@ static void __init r8a7779_init_irq_dt(void)
__raw_writel(0x003fee3f, INT2SMSKCR4);
 }
 
-#define MODEMR 0xffcc0020
-
-static u32 __init r8a7779_read_mode_pins(void)
-{
-   static u32 mode;
-   static bool mode_valid;
-
-   if (!mode_valid) {
-   void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-   BUG_ON(!modemr);
-   mode = ioread32(modemr);
-   iounmap(modemr);
-   mode_valid = true;
-   }
-
-   return mode;
-}
-
-static void __init r8a7779_init_time(void)
-{
-   r8a7779_clocks_init(r8a7779_read_mode_pins());
-   clocksource_probe();
-}
-
 static const char *const r8a7779_compat_dt[] __initconst = {
"renesas,r8a7779",
NULL,
@@ -109,7 +83,6 @@ static void __init r8a7779_init_time(void)
.smp= smp_ops(r8a7779_smp_ops),
.map_io = r8a7779_map_io,
.init_early = shmobile_init_delay,
-   .init_time  = r8a7779_init_time,
.init_irq   = r8a7779_init_irq_dt,
.init_late  = shmobile_init_late,
.dt_compat  = r8a7779_compat_dt,
-- 
1.9.1

[PATCH v4 23/23] clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()

[Geert Uytterhoeven]

The R-Car Gen2 board code no longer calls rcar_gen2_clocks_init().

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - Rebased,

v2:
  - No changes.
---
 drivers/clk/renesas/clk-rcar-gen2.c | 7 ---
 include/linux/clk/renesas.h | 2 --
 2 files changed, 9 deletions(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen2.c 
b/drivers/clk/renesas/clk-rcar-gen2.c
index 3291fd430ad4e215..f39519edc645ca87 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -445,10 +445,3 @@ static void __init rcar_gen2_cpg_clocks_init(struct 
device_node *np)
 }
 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
   rcar_gen2_cpg_clocks_init);
-
-void __init rcar_gen2_clocks_init(u32 mode)
-{
-   cpg_mode = mode;
-
-   of_clk_init(NULL);
-}
diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
index 9e969941f3f62878..9ebf1f8243bb57af 100644
--- a/include/linux/clk/renesas.h
+++ b/include/linux/clk/renesas.h
@@ -20,8 +20,6 @@
 struct device_node;
 struct generic_pm_domain;
 
-void rcar_gen2_clocks_init(u32 mode);
-
 void cpg_mstp_add_clk_domain(struct device_node *np);
 #ifdef CONFIG_CLK_RENESAS_CPG_MSTP
 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev);
-- 
1.9.1

[PATCH v4 14/23] clk: renesas: rcar-gen2: Obtain mode pin values using RST driver

[Geert Uytterhoeven]

Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.

Fall back to our own private copy of rcar_gen2_read_mode_pins() for
backward-compatibility with old DTs.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,
  - Use our own private copy of rcar_gen2_read_mode_pins() instead of
the one in the R-Car Gen2 platform code, as the latter is planned to
be removed,

v3:
  -  Use the R-Car RST driver instead of syscon/regmap and the
 "renesas,modemr" property in DT,

v2:
  - drivers/clk/shmobile/ was renamed to drivers/clk/renesas/.
---
 drivers/clk/renesas/clk-rcar-gen2.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/clk/renesas/clk-rcar-gen2.c 
b/drivers/clk/renesas/clk-rcar-gen2.c
index 00e6aba4b9c09596..3291fd430ad4e215 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct rcar_gen2_cpg {
struct clk_onecell_data data;
@@ -364,6 +365,23 @@ struct cpg_pll_config {
 4, 0, table, >lock);
 }
 
+/*
+ * Reset register definitions.
+ */
+#define MODEMR 0xe6160060
+
+static u32 __init rcar_gen2_read_mode_pins(void)
+{
+   void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+   u32 mode;
+
+   BUG_ON(!modemr);
+   mode = ioread32(modemr);
+   iounmap(modemr);
+
+   return mode;
+}
+
 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
 {
const struct cpg_pll_config *config;
@@ -372,6 +390,13 @@ static void __init rcar_gen2_cpg_clocks_init(struct 
device_node *np)
unsigned int i;
int num_clks;
 
+   if (rcar_rst_read_mode_pins(_mode)) {
+   /* Backward-compatibility with old DT */
+   pr_warn("%s: failed to obtain mode pins from RST\n",
+   np->full_name);
+   cpg_mode = rcar_gen2_read_mode_pins();
+   }
+
num_clks = of_property_count_strings(np, "clock-output-names");
if (num_clks < 0) {
pr_err("%s: failed to count clocks\n", __func__);
-- 
1.9.1

[PATCH v4 20/23] ARM: shmobile: rcar-gen2: Stop passing mode pins state to clock driver

[Geert Uytterhoeven]

Now the R-Car Gen2 CPG clock driver obtains the state of the mode pins
from the R-Car RST driver, there's no longer a need to pass this state
explicitly. Hence we can just call of_clk_init() instead.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,
  - Rebase on top of "ARM: shmobile: rcar-gen2: Obtain extal frequency
from DT",
  - Remove the call to rcar_gen2_read_mode_pins(),

v3:
  - Drop "select MFD_SYSCON", as the clock driver no longer uses syscon,

v2:
  - Kill compiler warning if CONFIG_ARM_ARCH_TIMER is not enabled.
---
 arch/arm/mach-shmobile/setup-rcar-gen2.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index afb9fdcd3d9084e2..b527258e0a62e806 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -15,7 +15,7 @@
  * GNU General Public License for more details.
  */
 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -71,7 +71,6 @@ static unsigned int __init get_extal_freq(void)
 
 void __init rcar_gen2_timer_init(void)
 {
-   u32 mode = rcar_gen2_read_mode_pins();
 #ifdef CONFIG_ARM_ARCH_TIMER
void __iomem *base;
u32 freq;
@@ -130,7 +129,7 @@ void __init rcar_gen2_timer_init(void)
iounmap(base);
 #endif /* CONFIG_ARM_ARCH_TIMER */
 
-   rcar_gen2_clocks_init(mode);
+   of_clk_init(NULL);
clocksource_probe();
 }
 
-- 
1.9.1

[PATCH v4 11/23] arm64: renesas: r8a7796 dtsi: Add device node for RST module

[Geert Uytterhoeven]

Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 9217da9835256573..75c8c55a824835bf 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -233,6 +233,11 @@
#power-domain-cells = <0>;
};
 
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a7796-rst";
+   reg = <0 0xe616 0 0x0200>;
+   };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7796-sysc";
reg = <0 0xe618 0 0x0400>;
-- 
1.9.1

[PATCH v4 21/23] clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()

[Geert Uytterhoeven]

The R-Car M1A board code no longer calls r8a7778_clocks_init().

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 drivers/clk/renesas/clk-r8a7778.c | 13 -
 include/linux/clk/renesas.h   |  1 -
 2 files changed, 14 deletions(-)

diff --git a/drivers/clk/renesas/clk-r8a7778.c 
b/drivers/clk/renesas/clk-r8a7778.c
index 07ea411098a75ad1..886a8380e91247a1 100644
--- a/drivers/clk/renesas/clk-r8a7778.c
+++ b/drivers/clk/renesas/clk-r8a7778.c
@@ -143,16 +143,3 @@ static void __init r8a7778_cpg_clocks_init(struct 
device_node *np)
 
 CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
   r8a7778_cpg_clocks_init);
-
-void __init r8a7778_clocks_init(u32 mode)
-{
-   BUG_ON(!(mode & BIT(19)));
-
-   cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
-(!!(mode & BIT(12)) << 1) |
-(!!(mode & BIT(11)));
-   cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
-   (!!(mode & BIT(1)));
-
-   of_clk_init(NULL);
-}
diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
index ba6fa4148515e5c9..2b663bba1adcc7c1 100644
--- a/include/linux/clk/renesas.h
+++ b/include/linux/clk/renesas.h
@@ -20,7 +20,6 @@
 struct device_node;
 struct generic_pm_domain;
 
-void r8a7778_clocks_init(u32 mode);
 void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
-- 
1.9.1

[PATCH v4 22/23] clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()

[Geert Uytterhoeven]

The R-Car H1 board code no longer calls r8a7779_clocks_init().

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 drivers/clk/renesas/clk-r8a7779.c | 9 -
 include/linux/clk/renesas.h   | 1 -
 2 files changed, 10 deletions(-)

diff --git a/drivers/clk/renesas/clk-r8a7779.c 
b/drivers/clk/renesas/clk-r8a7779.c
index ca7551bcb1153c3d..27fbfafaf2cd0353 100644
--- a/drivers/clk/renesas/clk-r8a7779.c
+++ b/drivers/clk/renesas/clk-r8a7779.c
@@ -89,8 +89,6 @@ struct cpg_clk_config {
  * Initialization
  */
 
-static u32 cpg_mode __initdata;
-
 static struct clk * __init
 r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
   const struct cpg_clk_config *config,
@@ -178,10 +176,3 @@ static void __init r8a7779_cpg_clocks_init(struct 
device_node *np)
 }
 CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
   r8a7779_cpg_clocks_init);
-
-void __init r8a7779_clocks_init(u32 mode)
-{
-   cpg_mode = mode;
-
-   of_clk_init(NULL);
-}
diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
index 2b663bba1adcc7c1..9e969941f3f62878 100644
--- a/include/linux/clk/renesas.h
+++ b/include/linux/clk/renesas.h
@@ -20,7 +20,6 @@
 struct device_node;
 struct generic_pm_domain;
 
-void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
 void cpg_mstp_add_clk_domain(struct device_node *np);
-- 
1.9.1

[PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state

[Geert Uytterhoeven]

Hi Philipp, Mike, Stephen, Simon, Magnus,
(see questions *** below!)

Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
state of the mode pins either by a call from the platform code, or
directly by using a hardcoded register access. This is a bit messy, and
creates a dependency between driver and platform code.

This patch series converts the various Renesas R-Car clock drivers
and support code from reading the mode pin states using a hardcoded
register access to using a new minimalistic R-Car RST driver.

All R-Car clock drivers will rely on the presence in DT of a device node
for the RST module.  Backwards compatibility with old DTBs is retained
only for R-Car Gen2, which has fallback code using its own private copy
of rcar_gen2_read_mode_pins().

After this, there is still one remaining user of
rcar_gen2_read_mode_pins() left in platform code. A patch series to
remove that user has already been posted, though ("[PATCH/RFT 0/4] ARM:
shmobile: R-Car Gen2: Allow booting secondary CPU cores in debug mode").
Since v3, the other user has been removed in commit 9f5ce39ddb8f68b3
("ARM: shmobile: rcar-gen2: Obtain extal frequency from DT").

This series consists of 5 parts:
  A. Patches 1 and 2 add DT bindings and driver code for the R-Car RST
 driver,
  B. Patches 3-11 add device nodes for the RST modules to the R-Car DTS
 files,
  C. Patches 12-17 convert the clock drivers to call into the new R-Car
 RST driver,
  D. Patches 18-20 remove passing mode pin state to the clock drivers
 from the platform code,
  E. Patches 21-23 remove dead code from the clock drivers.

As is usually the case with moving functionality from platform code to
DT, there are lots of hard dependencies:
  - The DT updates in Part B can be merged as soon as the DT bindings in
Part A have been approved,
  - The clock driver updates in Part C depend functionally on the driver
code in Part A, and on the DT updates in Part B,
  - The board code cleanups in Part D depend on the clock driver updates
in Part C,
  - The block driver cleanups in part E depend on the board code
cleanups in part D.

Hence to maintain the required lockstep between SoC driver, clock
drivers, shmobile platform code, and shmobile DT, I propose to queue up
all patches in a single branch against v4.9-rc1, and send pull requests
to both Mike/Stephen (clock) and Simon (rest).

***

  - Philip: While this is a driver for a reset-controller, currently it
doesn't provide any reset-controller functionality. Hence I added it
to drivers/soc/renesas/. Is that OK for you?

  - Mike/Stephen/Simon/Magnus: Are you OK with the suggested merge
approach above?

This series has evolved over time, cfr.:
  - "[PATCH/RFC v3 00/22] soc: renesas: Add R-Car RST driver for
obtaining mode pin state"
(http://www.spinics.net/lists/linux-renesas-soc/msg04289.html),
  - "[PATCH/RFC 00/11] ARM: shmobile: Let CPG use syscon for MD pin
values" (http://www.spinics.net/lists/linux-clk/msg01478.html),
  - "[PATCH 00/10] arm64: renesas: Obtain MD pin values using
syscon/regmap".
(http://www.spinics.net/lists/linux-sh/msg44757.html)

Changes compared to v3:
  - Add Acked-by, Reviewed-by,
  - Add support for R-Car V2H,
  - Add support for RZ/G1M and RZ/G1E,
  - Remove the initcall and the rcar_rst_base check in rcar_rst_init(),
as rcar_rst_init() is only used as a support function for
rcar_rst_read_mode_pins(),
  - Refer to rcar_rst_gen2 for R-Car Gen3 instead of providing an
identical copy,
  - Use our own private copy of rcar_gen2_read_mode_pins() instead of
the one in the R-Car Gen2 platform code, as the latter is planned to
be removed,
  - Rebase on top of "ARM: shmobile: rcar-gen2: Obtain extal frequency
from DT",

Changes compared to v2:
  - Use "renesas,-rst" instead of "renesas,rst-",
  - Drop "syscon" compatible value and "renesas,modemr" property, use a
real driver instead,
  - Add support for R-Car M1A, H1, and M3-W.

Changes compared to v1:
  - Add support for R-Car H3.

This patch series is against v4.9-rc1. When applying it to
renesas-devel-20161021-v4.9-rc1, there's a small conflict in
drivers/soc/renesas/Makefile (both sides added lines).

For your convenience, this series is also available in the
topic/rcar-rst-v4 branch of my renesas-drivers git repository at
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
This has been tested on r8a7778/bockw, r8a7779/marzen, r8a7791/koelsch,
r8a7795/salvator-x, and r8a7796/salvator-x.

Thanks!

Geert Uytterhoeven (23):
  reset: Add renesas,rst DT bindings
  soc: renesas: Add R-Car RST driver
  ARM: dts: r8a7778: Add device node for RESET/WDT module
  ARM: dts: r8a7779: Add device node for RESET/WDT module
  ARM: dts: r8a7790: Add device node for RST module
  ARM: dts: r8a7791: Add device node for RST mod

[PATCH v4 12/23] clk: renesas: r8a7778: Obtain mode pin values using R-Car RST driver

[Geert Uytterhoeven]

Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 drivers/clk/renesas/clk-r8a7778.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/renesas/clk-r8a7778.c 
b/drivers/clk/renesas/clk-r8a7778.c
index 40e3a501a50e200f..07ea411098a75ad1 100644
--- a/drivers/clk/renesas/clk-r8a7778.c
+++ b/drivers/clk/renesas/clk-r8a7778.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct r8a7778_cpg {
struct clk_onecell_data data;
@@ -83,6 +84,18 @@ static void __init r8a7778_cpg_clocks_init(struct 
device_node *np)
struct clk **clks;
unsigned int i;
int num_clks;
+   u32 mode;
+
+   if (rcar_rst_read_mode_pins())
+   return;
+
+   BUG_ON(!(mode & BIT(19)));
+
+   cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
+(!!(mode & BIT(12)) << 1) |
+(!!(mode & BIT(11)));
+   cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
+   (!!(mode & BIT(1)));
 
num_clks = of_property_count_strings(np, "clock-output-names");
if (num_clks < 0) {
-- 
1.9.1

[PATCH v4 15/23] clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driver

[Geert Uytterhoeven]

Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
Reviewed-by: Laurent Pinchart 
---
v4:
  - Add Acked-by, Reviewed-by,

v3:
  - New.
---
 drivers/clk/renesas/r8a7795-cpg-mssr.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index f255e451e8cafbbf..726c3d7940b491b9 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -311,7 +312,12 @@ enum clk_ids {
 static int __init r8a7795_cpg_mssr_init(struct device *dev)
 {
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
-   u32 cpg_mode = rcar_gen3_read_mode_pins();
+   u32 cpg_mode;
+   int error;
+
+   error = rcar_rst_read_mode_pins(_mode);
+   if (error)
+   return error;
 
cpg_pll_config = _pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (!cpg_pll_config->extal_div) {
-- 
1.9.1

[PATCH v4 16/23] clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver

[Geert Uytterhoeven]

Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
Reviewed-by: Laurent Pinchart 
---
v4:
  - Add Acked-by, Reviewed-by,

v3:
  - New.
---
 drivers/clk/renesas/r8a7796-cpg-mssr.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index eb347ed265f2adfa..1c144b21869df39c 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -190,7 +191,12 @@ enum clk_ids {
 static int __init r8a7796_cpg_mssr_init(struct device *dev)
 {
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
-   u32 cpg_mode = rcar_gen3_read_mode_pins();
+   u32 cpg_mode;
+   int error;
+
+   error = rcar_rst_read_mode_pins(_mode);
+   if (error)
+   return error;
 
cpg_pll_config = _pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (!cpg_pll_config->extal_div) {
-- 
1.9.1

[PATCH v4 17/23] clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()

[Geert Uytterhoeven]

All R-Car Gen3 clock drivers now obtain the values of the mode pins from
the R-Car RST driver.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
Reviewed-by: Laurent Pinchart 
---
v4:
  - Add Acked-by, Reviewed-by,

v3:
  - New.
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 17 -
 drivers/clk/renesas/rcar-gen3-cpg.h |  1 -
 2 files changed, 18 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c 
b/drivers/clk/renesas/rcar-gen3-cpg.c
index bb4f2f9a8c2f5ba8..9d76076da4948fc4 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -333,23 +333,6 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct 
device *dev,
 __clk_get_name(parent), 0, mult, div);
 }
 
-/*
- * Reset register definitions.
- */
-#define MODEMR 0xe6160060
-
-u32 __init rcar_gen3_read_mode_pins(void)
-{
-   void __iomem *modemr = ioremap_nocache(MODEMR, 4);
-   u32 mode;
-
-   BUG_ON(!modemr);
-   mode = ioread32(modemr);
-   iounmap(modemr);
-
-   return mode;
-}
-
 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
  unsigned int clk_extalr)
 {
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h 
b/drivers/clk/renesas/rcar-gen3-cpg.h
index f699085147d1aece..f788f481dd42cdf6 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -33,7 +33,6 @@ struct rcar_gen3_cpg_pll_config {
 
 #define CPG_RCKCR  0x240
 
-u32 rcar_gen3_read_mode_pins(void);
 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base);
-- 
1.9.1

[PATCH v4 07/23] ARM: dts: r8a7792: Add device node for RST module

[Geert Uytterhoeven]

Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.

Signed-off-by: Geert Uytterhoeven 
---
v4:
  - New.
---
 arch/arm/boot/dts/r8a7792.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 713141d38b3ea960..6e1f61f65d292b0b 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -118,6 +118,11 @@
  IRQ_TYPE_LEVEL_LOW)>;
};
 
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a7792-rst";
+   reg = <0 0xe616 0 0x0100>;
+   };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe618 0 0x0200>;
-- 
1.9.1

[PATCH v4 13/23] clk: renesas: r8a7779: Obtain mode pin values from R-Car RST driver

[Geert Uytterhoeven]

Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 drivers/clk/renesas/clk-r8a7779.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/clk-r8a7779.c 
b/drivers/clk/renesas/clk-r8a7779.c
index cf2a37df03b15e60..ca7551bcb1153c3d 100644
--- a/drivers/clk/renesas/clk-r8a7779.c
+++ b/drivers/clk/renesas/clk-r8a7779.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -127,6 +128,10 @@ static void __init r8a7779_cpg_clocks_init(struct 
device_node *np)
struct clk **clks;
unsigned int i, plla_mult;
int num_clks;
+   u32 mode;
+
+   if (rcar_rst_read_mode_pins())
+   return;
 
num_clks = of_property_count_strings(np, "clock-output-names");
if (num_clks < 0) {
@@ -148,8 +153,8 @@ static void __init r8a7779_cpg_clocks_init(struct 
device_node *np)
cpg->data.clks = clks;
cpg->data.clk_num = num_clks;
 
-   config = _clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
-   plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
+   config = _clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
+   plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
 
for (i = 0; i < num_clks; ++i) {
const char *name;
-- 
1.9.1

[PATCH v4 18/23] ARM: shmobile: r8a7778: Stop passing mode pins state to clock driver

[Geert Uytterhoeven]

Now the R-Car M1A CPG clock driver obtains the state of the mode pins
from the R-Car RST driver, there's no longer a need to pass this state
explicitly. Hence we can just remove the .init_time() callback, the
generic ARM code will take care of calling of_clk_init().

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 arch/arm/mach-shmobile/setup-r8a7778.c | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c 
b/arch/arm/mach-shmobile/setup-r8a7778.c
index cf236db686a9dd47..7fa4a0b5f6549287 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -15,7 +15,6 @@
  * GNU General Public License for more details.
  */
 
-#include 
 #include 
 #include 
 
@@ -23,19 +22,6 @@
 
 #include "common.h"
 
-#define MODEMR 0xffcc0020
-
-static void __init r8a7778_timer_init(void)
-{
-   u32 mode;
-   void __iomem *modemr = ioremap_nocache(MODEMR, 4);
-
-   BUG_ON(!modemr);
-   mode = ioread32(modemr);
-   iounmap(modemr);
-   r8a7778_clocks_init(mode);
-}
-
 #define INT2SMSKCR00x82288 /* 0xfe782288 */
 #define INT2SMSKCR10x8228c /* 0xfe78228c */
 
@@ -70,6 +56,5 @@ static void __init r8a7778_init_irq_dt(void)
.init_early = shmobile_init_delay,
.init_irq   = r8a7778_init_irq_dt,
.init_late  = shmobile_init_late,
-   .init_time  = r8a7778_timer_init,
.dt_compat  = r8a7778_compat_dt,
 MACHINE_END
-- 
1.9.1

[PATCH v4 06/23] ARM: dts: r8a7791: Add device node for RST module

[Geert Uytterhoeven]

Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - Use "renesas,-rst" instead of "renesas,rst-",
  - Drop "syscon" compatible value,

v2:
  - Correct unit address,
  - Drop RFC status and TODO,
  - Change one-line summary prefix to match current arm-soc practices.
---
 arch/arm/boot/dts/r8a7791.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 162b55c665a3519e..c465c79bcca6e8f3 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1482,6 +1482,11 @@
};
};
 
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a7791-rst";
+   reg = <0 0xe616 0 0x0100>;
+   };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7791-sysc";
reg = <0 0xe618 0 0x0200>;
-- 
1.9.1

[PATCH v4 04/23] ARM: dts: r8a7779: Add device node for RESET/WDT module

[Geert Uytterhoeven]

Add a device node for the RESET/WDT module, which provides a.o. reset
control, mode pin monitoring, and watchdog control.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7779.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b9bbcce69dfbd5b9..4a30b232624e1d24 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -595,4 +595,9 @@
reg = <0xffd85000 0x0200>;
#power-domain-cells = <1>;
};
+
+   rst: reset-controller@ffcc {
+   compatible = "renesas,r8a7779-reset-wdt";
+   reg = <0xffcc 0x48>;
+   };
 };
-- 
1.9.1

RE: [RFC 3/5] media: platform: rcar_drif: Add DRIF support

[Ramesh Shanmugasundaram]

Hi Laurent,

Thank you for the review comments.

> On Tuesday 18 Oct 2016 16:29:24 Geert Uytterhoeven wrote:
> > On Wed, Oct 12, 2016 at 4:10 PM, Ramesh Shanmugasundaram wrote:
> > > This patch adds Digital Radio Interface (DRIF) support to R-Car Gen3
> SoCs.
> > > The driver exposes each instance of DRIF as a V4L2 SDR device. A
> > > DRIF device represents a channel and each channel can have one or
> > > two sub-channels respectively depending on the target board.
> > >
> > > DRIF supports only Rx functionality. It receives samples from a RF
> > > frontend tuner chip it is interfaced with. The combination of DRIF
> > > and the tuner device, which is registered as a sub-device,
> > > determines the receive sample rate and format.
> > >
> > > In order to be compliant as a V4L2 SDR device, DRIF needs to bind
> > > with the tuner device, which can be provided by a third party
> > > vendor. DRIF acts as a slave device and the tuner device acts as a
> > > master transmitting the samples. The driver allows asynchronous
> > > binding of a tuner device that is registered as a v4l2 sub-device.
> > > The driver can learn about the tuner it is interfaced with based on
> > > port endpoint properties of the device in device tree. The V4L2 SDR
> > > device inherits the controls exposed by the tuner device.
> > >
> > > The device can also be configured to use either one or both of the
> > > data pins at runtime based on the master (tuner) configuration.
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
> > > @@ -0,0 +1,109 @@
> > > +Renesas R-Car Gen3 DRIF controller (DRIF)
> > > +-
> > > +
> > > +Required properties:
> > > +
> > > +- compatible: "renesas,drif-r8a7795" if DRIF controller is a part
> > > +of
> > > R8A7795 SoC.
> >
> > "renesas,r8a7795-drif", as Rob already pointed out.
> >
> > > + "renesas,rcar-gen3-drif" for a generic R-Car Gen3
> > > + compatible
> > > device.
> > > + When compatible with the generic version, nodes must
> > > + list
> > > the
> > > + SoC-specific version corresponding to the platform first
> > > + followed by the generic version.
> > > +
> > > +- reg: offset and length of each sub-channel.
> > > +- interrupts: associated with each sub-channel.
> > > +- clocks: phandles and clock specifiers for each sub-channel.
> > > +- clock-names: clock input name strings: "fck0", "fck1".
> > > +- pinctrl-0: pin control group to be used for this controller.
> > > +- pinctrl-names: must be "default".
> > > +- dmas: phandles to the DMA channels for each sub-channel.
> > > +- dma-names: names for the DMA channels: "rx0", "rx1".
> > > +
> > > +Required child nodes:
> > > +-
> > > +- Each DRIF channel can have one or both of the sub-channels
> > > +enabled in a
> > > +  setup. The sub-channels are represented as a child node. The name
> > > +of
> > > the
> > > +  child nodes are "sub-channel0" and "sub-channel1" respectively.
> > > + Each
> > > child
> > > +  node supports the "status" property only, which is used to
> > > enable/disable
> > > +  the respective sub-channel.
> > >
> > > +Example
> > > +
> > > +
> > > +SoC common dtsi file
> > > +
> > > +drif0: rif@e6f4 {
> > > +   compatible = "renesas,drif-r8a7795",
> > > +  "renesas,rcar-gen3-drif";
> > > +   reg = <0 0xe6f4 0 0x64>, <0 0xe6f5 0 0x64>;
> > > +   interrupts = ,
> > > +  ;
> > > +   clocks = < CPG_MOD 515>, < CPG_MOD 514>;
> > > +   clock-names = "fck0", "fck1";
> > > +   dmas = < 0x20>, < 0x22>;
> > > +   dma-names = "rx0", "rx1";
> >
> > I could not find the DMAC channels in the datasheet?
> > Most modules are either tied to dmac0, or two both dmac1 and dmac2.
> > In the latter case, you want to list two sets of dmas, one for each
> DMAC.
> >
> > > +   power-domains = < R8A7795_PD_ALWAYS_ON>;
> > > +   status = "disabled";
> > > +
> > > +   sub-channel0 {
> > > +   status = "disabled";
> > > +   };
> > > +
> > > +   sub-channel1 {
> > > +   status = "disabled";
> > > +   };
> > > +
> > > +};
> >
> > As you're modelling this in DT under a single device node, this means
> > you cannot use runtime PM to manage the module clocks of the
> > individual channels.
> >
> > An alternative could be to have two separate nodes for each channel,
> > and tie them together using a phandle.
> 
> A quick glance at the documentation shows no dependency between the two
> channels at a software level. They both share the same clock and
> synchronization input pins, but from a hardware point of view that seems
> to be it. It thus looks like we could indeed model the two channels as
> separate nodes, without tying them together.

Thanks & I agree with your suggestion to keep each DRIF sub-channels as 
separate node. However, I would 

[PATCH v4 09/23] ARM: dts: r8a7794: Add device node for RST module

[Geert Uytterhoeven]

Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - Use "renesas,-rst" instead of "renesas,rst-",
  - Drop "syscon" compatible value,

v2:
  - Correct unit address,
  - Drop RFC status and TODO,
  - Change one-line summary prefix to match current arm-soc practices.
---
 arch/arm/boot/dts/r8a7794.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 9365580a194facc7..69e4f4fad89b2323 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1375,6 +1375,11 @@
};
};
 
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a7794-rst";
+   reg = <0 0xe616 0 0x0100>;
+   };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7794-sysc";
reg = <0 0xe618 0 0x0200>;
-- 
1.9.1

[PATCH v4 02/23] soc: renesas: Add R-Car RST driver

[Geert Uytterhoeven]

Add a driver for the Renesas R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3
and RZ/G RST module.

For now this driver just provides an API to obtain the state of the mode
pins, as latched at reset time.  As this is typically called from the
probe function of a clock driver, which can run much earlier than any
initcall, calling rcar_rst_read_mode_pins() just forces an early
initialization of the driver.

Despite the current simple and almost identical handling for all
supported SoCs, the driver matches against SoC-specific compatible
values, as the features provided by the hardware module differ a lot
across the various SoC families and members.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,
  - Remove the initcall and the rcar_rst_base check in rcar_rst_init(),
as rcar_rst_init() is only used as a support function for
rcar_rst_read_mode_pins(),
  - Refer to rcar_rst_gen2 for R-Car Gen3 instead of providing an
identical copy,
  - Add RZ/G1M and RZ/G1E,

v3:
  - New.
---
 drivers/soc/renesas/Makefile |  5 ++
 drivers/soc/renesas/rcar-rst.c   | 92 
 include/linux/soc/renesas/rcar-rst.h |  6 +++
 3 files changed, 103 insertions(+)
 create mode 100644 drivers/soc/renesas/rcar-rst.c
 create mode 100644 include/linux/soc/renesas/rcar-rst.h

diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 623039c3514cdc34..86cc78cd1962701a 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -1,3 +1,8 @@
+obj-$(CONFIG_ARCH_RCAR_GEN1)   += rcar-rst.o
+obj-$(CONFIG_ARCH_RCAR_GEN2)   += rcar-rst.o
+obj-$(CONFIG_ARCH_R8A7795) += rcar-rst.o
+obj-$(CONFIG_ARCH_R8A7796) += rcar-rst.o
+
 obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o
 obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o
 obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
new file mode 100644
index ..a6d1c26d31675cf3
--- /dev/null
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -0,0 +1,92 @@
+/*
+ * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct rst_config {
+   unsigned int modemr;/* Mode Monitoring Register Offset */
+};
+
+static const struct rst_config rcar_rst_gen1 __initconst = {
+   .modemr = 0x20,
+};
+
+static const struct rst_config rcar_rst_gen2 __initconst = {
+   .modemr = 0x60,
+};
+
+static const struct of_device_id rcar_rst_matches[] __initconst = {
+   /* RZ/G is handled like R-Car Gen2 */
+   { .compatible = "renesas,r8a7743-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a7745-rst", .data = _rst_gen2 },
+   /* R-Car Gen1 */
+   { .compatible = "renesas,r8a7778-reset-wdt", .data = _rst_gen1 },
+   { .compatible = "renesas,r8a7779-reset-wdt", .data = _rst_gen1 },
+   /* R-Car Gen2 */
+   { .compatible = "renesas,r8a7790-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a7791-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a7792-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a7793-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a7794-rst", .data = _rst_gen2 },
+   /* R-Car Gen3 is handled like R-Car Gen2 */
+   { .compatible = "renesas,r8a7795-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a7796-rst", .data = _rst_gen2 },
+   { /* sentinel */ }
+};
+
+static void __iomem *rcar_rst_base __initdata;
+static u32 saved_mode __initdata;
+
+static int __init rcar_rst_init(void)
+{
+   const struct of_device_id *match;
+   const struct rst_config *cfg;
+   struct device_node *np;
+   void __iomem *base;
+   int error = 0;
+
+   np = of_find_matching_node_and_match(NULL, rcar_rst_matches, );
+   if (!np)
+   return -ENODEV;
+
+   base = of_iomap(np, 0);
+   if (!base) {
+   pr_warn("%s: Cannot map regs\n", np->full_name);
+   error = -ENOMEM;
+   goto out_put;
+   }
+
+   rcar_rst_base = base;
+   cfg = match->data;
+   saved_mode = ioread32(base + cfg->modemr);
+
+   pr_debug("%s: MODE = 0x%08x\n", np->full_name, saved_mode);
+
+out_put:
+   of_node_put(np);
+   return error;
+}
+
+int __init rcar_rst_read_mode_pins(u32 *mode)
+{
+   int error;
+
+   if (!rcar_rst_base) {
+   error = rcar_rst_init();
+   if (error)
+   return error;
+   }
+
+   *mode = saved_mode;
+   return 0;
+}
diff --git a/include/linux/soc/renesas/rcar-rst.h 

[PATCH v4 05/23] ARM: dts: r8a7790: Add device node for RST module

[Geert Uytterhoeven]

Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.

Signed-off-by: Geert Uytterhoeven 
Acked-by: Dirk Behme 
---
v4:
  - Add Acked-by,

v3:
  - Use "renesas,-rst" instead of "renesas,rst-",
  - Drop "syscon" compatible value,

v2:
  - Correct unit address,
  - Drop RFC status and TODO,
  - Change one-line summary prefix to match current arm-soc practices.
---
 arch/arm/boot/dts/r8a7790.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 351fcc2f87df6b28..3f10b0bf1b08fa89 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1471,6 +1471,11 @@
};
};
 
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a7790-rst";
+   reg = <0 0xe616 0 0x0100>;
+   };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7790-sysc";
reg = <0 0xe618 0 0x0200>;
-- 
1.9.1

RE: [RFC 3/5] media: platform: rcar_drif: Add DRIF support

[Ramesh Shanmugasundaram]

Hi Geert,

Thank you for the review comments.

> On Wed, Oct 12, 2016 at 4:10 PM, Ramesh Shanmugasundaram
>  wrote:
> > This patch adds Digital Radio Interface (DRIF) support to R-Car Gen3
> SoCs.
> > The driver exposes each instance of DRIF as a V4L2 SDR device. A DRIF
> > device represents a channel and each channel can have one or two
> > sub-channels respectively depending on the target board.
> >
> > DRIF supports only Rx functionality. It receives samples from a RF
> > frontend tuner chip it is interfaced with. The combination of DRIF and
> > the tuner device, which is registered as a sub-device, determines the
> > receive sample rate and format.
> >
> > In order to be compliant as a V4L2 SDR device, DRIF needs to bind with
> > the tuner device, which can be provided by a third party vendor. DRIF
> > acts as a slave device and the tuner device acts as a master
> > transmitting the samples. The driver allows asynchronous binding of a
> > tuner device that is registered as a v4l2 sub-device. The driver can
> > learn about the tuner it is interfaced with based on port endpoint
> > properties of the device in device tree. The V4L2 SDR device inherits
> > the controls exposed by the tuner device.
> >
> > The device can also be configured to use either one or both of the
> > data pins at runtime based on the master (tuner) configuration.
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
> > @@ -0,0 +1,109 @@
> > +Renesas R-Car Gen3 DRIF controller (DRIF)
> > +-
> > +
> > +Required properties:
> > +
> > +- compatible: "renesas,drif-r8a7795" if DRIF controller is a part of
> R8A7795 SoC.
> 
> "renesas,r8a7795-drif", as Rob already pointed out.

Agreed.

> 
> > + "renesas,rcar-gen3-drif" for a generic R-Car Gen3
> compatible device.
> > + When compatible with the generic version, nodes must list
> the
> > + SoC-specific version corresponding to the platform first
> > + followed by the generic version.
> > +
> > +- reg: offset and length of each sub-channel.
> > +- interrupts: associated with each sub-channel.
> > +- clocks: phandles and clock specifiers for each sub-channel.
> > +- clock-names: clock input name strings: "fck0", "fck1".
> > +- pinctrl-0: pin control group to be used for this controller.
> > +- pinctrl-names: must be "default".
> > +- dmas: phandles to the DMA channels for each sub-channel.
> > +- dma-names: names for the DMA channels: "rx0", "rx1".
> > +
> > +Required child nodes:
> > +-
> > +- Each DRIF channel can have one or both of the sub-channels enabled
> > +in a
> > +  setup. The sub-channels are represented as a child node. The name
> > +of the
> > +  child nodes are "sub-channel0" and "sub-channel1" respectively.
> > +Each child
> > +  node supports the "status" property only, which is used to
> > +enable/disable
> > +  the respective sub-channel.
> 
> > +Example
> > +
> > +
> > +SoC common dtsi file
> > +
> > +drif0: rif@e6f4 {
> > +   compatible = "renesas,drif-r8a7795",
> > +  "renesas,rcar-gen3-drif";
> > +   reg = <0 0xe6f4 0 0x64>, <0 0xe6f5 0 0x64>;
> > +   interrupts = ,
> > +  ;
> > +   clocks = < CPG_MOD 515>, < CPG_MOD 514>;
> > +   clock-names = "fck0", "fck1";
> > +   dmas = < 0x20>, < 0x22>;
> > +   dma-names = "rx0", "rx1";
> 
> I could not find the DMAC channels in the datasheet?

It is mentioned only in v0.5 h/w manual. v0.52 manual introduced DRIF chapter 
but then some of the old references were missing :-(. There are few more doc 
anomalies, which I shall document in the next version of the patch.

> Most modules are either tied to dmac0, or two both dmac1 and dmac2.
> In the latter case, you want to list two sets of dmas, one for each DMAC.

You are right. I have added both dmac1 & 2 now.

> 
> > +   power-domains = < R8A7795_PD_ALWAYS_ON>;
> > +   status = "disabled";
> > +
> > +   sub-channel0 {
> > +   status = "disabled";
> > +   };
> > +
> > +   sub-channel1 {
> > +   status = "disabled";
> > +   };
> > +
> > +};
> 
> As you're modelling this in DT under a single device node, this means you
> cannot use runtime PM to manage the module clocks of the individual
> channels.
> 
> An alternative could be to have two separate nodes for each channel, and
> tie them together using a phandle.

I agree & thanks for the suggestion. Is the below model looks anything closer? 
Appreciate your inputs.

dtsi
---

drif00: rif@e6f4 {
compatible = "renesas,r8a7795-drif",
 
"renesas,rcar-gen3-drif";
reg = <0 0xe6f4 0 0x64>;
interrupts = ;
   

[PATCH] ARM: dts: r8a7779: marzen: Configure pinmuxing for the DU0 input clock

[Laurent Pinchart]

DU0 uses an externally provided clock, but the corresponding pin isn't
correctly muxed. Fix it.

Signed-off-by: Laurent Pinchart 
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Along with the DU reg fix that has already been merged in Simon's tree, this
makes the VGA output on Marzen working again.

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts 
b/arch/arm/boot/dts/r8a7779-marzen.dts
index 541678df90a9..676151b70185 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -170,7 +170,7 @@
 
du_pins: du {
du0 {
-   groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
+   groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", 
"du0_clk_in";
function = "du0";
};
du1 {
-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 0/2] usb: host: xhci: plat: add support for Renesas r8a7796 SoC

[Mathias Nyman]

On 19.10.2016 11:50, Yoshihiro Shimoda wrote:

This patch set is based on the latest Greg's usb.git / usb-next branch.
(commit id = 1001354ca34179f3db924eb66672442a173147dc)

Changes from v1:
  - Revise the comment in patch 1.
  - Don't add a new macro because the macro will be not used in the future.
(Especially, the xhci-rcar driver will need to check SoC revision and
 change the firmware name.)

Yoshihiro Shimoda (2):
   usb: host: xhci: rcar: add a new firmware version for r8a7796
   usb: host: xhci: plat: add support for Renesas r8a7796 SoC

  Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
  drivers/usb/host/xhci-plat.c   | 9 +
  drivers/usb/host/xhci-rcar.c   | 4 
  drivers/usb/host/xhci-rcar.h   | 1 +
  4 files changed, 15 insertions(+)



Thanks, added it to my tree

-Mathias

Re: [PATCH 2/8] drm: bridge: vga-dac: Add adi,adv7123 compatible string

[Archit Taneja]

On 10/21/2016 03:52 PM, Laurent Pinchart wrote:

Hi Archit,

On Friday 21 Oct 2016 10:43:34 Archit Taneja wrote:

On 10/19/2016 07:55 PM, Laurent Pinchart wrote:

The ADV7123 is a transparent VGA DAC. Unlike dumb VGA DACs it can be
controlled through a power save pin, and requires a power supply.
However, on most boards where the device is used neither the power save
signal nor the power supply are controllable.

To avoid developing a separate device-specific driver add an
"adi,adv7123" compatible entry to the dumb-vga-dac driver. This will
allow supporting most ADV7123-based boards easily, while allowing future
development of an adv7123 driver when needed without breaking backward
compatibility.


Shouldn't we have a DT binding doc for ADV7123, even if it's sharing
the dumb vga driver for now?


Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt


Same query for the Thine LVDS encoder.


Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt


Cool, didn't know these already existed :)

Thanks,
Archit




Cc: devicet...@vger.kernel.org
Signed-off-by: Laurent Pinchart

---

 drivers/gpu/drm/bridge/dumb-vga-dac.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c
b/drivers/gpu/drm/bridge/dumb-vga-dac.c index afec232185a7..b33e3f829e4f
100644
--- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
+++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
@@ -204,6 +204,7 @@ static int dumb_vga_remove(struct platform_device
*pdev)>
 static const struct of_device_id dumb_vga_match[] = {

{ .compatible = "dumb-vga-dac" },
+   { .compatible = "adi,adv7123" },
{},
 };
 MODULE_DEVICE_TABLE(of, dumb_vga_match);




--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/8] drm: bridge: vga-dac: Add adi,adv7123 compatible string

[Laurent Pinchart]

Hi Archit,

On Friday 21 Oct 2016 10:43:34 Archit Taneja wrote:
> On 10/19/2016 07:55 PM, Laurent Pinchart wrote:
> > The ADV7123 is a transparent VGA DAC. Unlike dumb VGA DACs it can be
> > controlled through a power save pin, and requires a power supply.
> > However, on most boards where the device is used neither the power save
> > signal nor the power supply are controllable.
> > 
> > To avoid developing a separate device-specific driver add an
> > "adi,adv7123" compatible entry to the dumb-vga-dac driver. This will
> > allow supporting most ADV7123-based boards easily, while allowing future
> > development of an adv7123 driver when needed without breaking backward
> > compatibility.
> 
> Shouldn't we have a DT binding doc for ADV7123, even if it's sharing
> the dumb vga driver for now?

Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt

> Same query for the Thine LVDS encoder.

Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt

> > Cc: devicet...@vger.kernel.org
> > Signed-off-by: Laurent Pinchart
> > 
> > ---
> > 
> >  drivers/gpu/drm/bridge/dumb-vga-dac.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c
> > b/drivers/gpu/drm/bridge/dumb-vga-dac.c index afec232185a7..b33e3f829e4f
> > 100644
> > --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
> > +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
> > @@ -204,6 +204,7 @@ static int dumb_vga_remove(struct platform_device
> > *pdev)> 
> >  static const struct of_device_id dumb_vga_match[] = {
> >  
> > { .compatible = "dumb-vga-dac" },
> > +   { .compatible = "adi,adv7123" },
> > {},
> >  };
> >  MODULE_DEVICE_TABLE(of, dumb_vga_match);

-- 
Regards,

Laurent Pinchart

Re: [PATCH 1/8] drm: bridge: Add LVDS encoder driver

[Laurent Pinchart]

Hi Archit,

On Friday 21 Oct 2016 10:51:59 Archit Taneja wrote:
> On 10/19/2016 07:55 PM, Laurent Pinchart wrote:
> > The LVDS encoder driver is a DRM bridge driver that supports the
> > parallel to LVDS encoders that don't require any configuration. The
> > driver thus doesn't interact with the device, but creates an LVDS
> > connector for the panel and exposes its size and timing based on
> > information retrieved from DT.
> > 
> > Cc: devicet...@vger.kernel.org
> > Signed-off-by: Laurent Pinchart
> > 
> > ---
> > 
> >  .../bindings/display/bridge/lvds-transmitter.txt   |  64 +++
> >  drivers/gpu/drm/bridge/Kconfig |   8 +
> >  drivers/gpu/drm/bridge/Makefile|   1 +
> >  drivers/gpu/drm/bridge/lvds-encoder.c  | 203 
> >  4 files changed, 276 insertions(+)
> >  create mode 100644
> >  Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt
> >  create mode 100644 drivers/gpu/drm/bridge/lvds-encoder.c
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt
> > b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt
> > new file mode 100644
> > index ..fd39ad34c383
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt
> > @@ -0,0 +1,64 @@
> > +Parallel to LVDS Encoder
> > +
> > +
> > +This binding supports the parallel to LVDS encoders that don't require
> > any
> > +configuration.
> > +
> > +LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A.
> > Multiple +incompatible data link layers have been used over time to
> > transmit image data +to LVDS panels. This binding targets devices
> > compatible with the following +specifications only.
> > +
> > +[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999,
> > February
> > +1999 (Version 1.0), Japan Electronic Industry Development Association
> > (JEIDA) +[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95),
> > National +Semiconductor
> > +[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
> > +Electronics Standards Association (VESA)
> > +
> > +Those devices have been marketed under the FPD-Link and FlatLink brand
> > names +among others.
> > +
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "lvds-encoder"
> > +
> > +Required nodes:
> > +
> > +This device has two video ports. Their connections are modeled using the
> > OF +graph bindings specified in
> > Documentation/devicetree/bindings/graph.txt. +
> > +- Video port 0 for parallel input
> > +- Video port 1 for LVDS output
> > +
> > +
> > +Example
> > +---
> > +
> > +lvds-encoder {
> > +   compatible = "lvds-encoder";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   ports {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   port@0 {
> > +   reg = <0>;
> > +
> > +   lvds_enc_in: endpoint {
> > +   remote-endpoint = <_out_rgb>;
> > +   };
> > +   };
> > +
> > +   port@1 {
> > +   reg = <1>;
> > +
> > +   lvds_enc_out: endpoint {
> > +   remote-endpoint = <_panel_in>;
> > +   };
> > +   };
> > +   };
> > +};
> > diff --git a/drivers/gpu/drm/bridge/Kconfig
> > b/drivers/gpu/drm/bridge/Kconfig index 10e12e74fc9f..5dafad7817ad 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -24,6 +24,14 @@ config DRM_DUMB_VGA_DAC
> > 
> > help
> > 
> >   Support for RGB to VGA DAC based bridges
> > 
> > +config DRM_LVDS_ENCODER
> > +   tristate "Transparent parallel to LVDS encoder support"
> > +   depends on OF
> > +   select DRM_KMS_HELPER
> > +   help
> > + Support for transparent parallel to LVDS encoders that don't require
> > + any configuration.
> > +
> > 
> >  config DRM_DW_HDMI
> >  
> > tristate
> > select DRM_KMS_HELPER
> > 
> > diff --git a/drivers/gpu/drm/bridge/Makefile
> > b/drivers/gpu/drm/bridge/Makefile index cdf3a3cf765d..bbaf583581ac 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -2,6 +2,7 @@ ccflags-y := -Iinclude/drm
> > 
> >  obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
> >  obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
> > 
> > +obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
> > 
> >  obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
> >  obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
> >  obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
> > 
> > diff --git a/drivers/gpu/drm/bridge/lvds-encoder.c
> > b/drivers/gpu/drm/bridge/lvds-encoder.c new file mode 100644
> > index ..33e8025c8a6d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/lvds-encoder.c
> > @@ -0,0 +1,203 @@
> > +/*
> > 

[PATCH 3/5] ARM: dts: r8a7779: Remove skeleton.dtsi inclusion

[Geert Uytterhoeven]

As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, 
but no unit name

Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/boot/dts/r8a7779.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b9bbcce69dfbd5b9..cd8c52d5cb850766 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -9,8 +9,6 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
-
 #include 
 #include 
 #include 
@@ -19,6 +17,8 @@
 / {
compatible = "renesas,r8a7779";
interrupt-parent = <>;
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
-- 
1.9.1

[PATCH 4/5] ARM: dts: r8a7740: Remove skeleton.dtsi inclusion

[Geert Uytterhoeven]

As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, 
but no unit name

Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/boot/dts/r8a7740.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 159e04eb1b9e55da..34159a8349def81e 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -8,8 +8,6 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
-
 #include 
 #include 
 #include 
@@ -17,6 +15,8 @@
 / {
compatible = "renesas,r8a7740";
interrupt-parent = <>;
+   #address-cells = <1>;
+   #size-cells = <1>;
 
cpus {
#address-cells = <1>;
-- 
1.9.1