Re: [PATCH v7 00/11] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello,

On Fri, 20 Apr 2018 23:10:11 +0200
Mylène Josserand  wrote:

> Hello everyone,
> 
> This is a V7 of my series that adds SMP support for Allwinner sun8i-a83t.
> Based on sunxi's tree, sunxi/for-next branch.
> Depends on a patch from Doug Berger that allows to include the "cpu-type"
> header on assembly files:
> https://lkml.org/lkml/2018/2/23/1263
> (applied on Broadcom's tree: 
> https://github.com/Broadcom/stblinux/commits/soc/next)

And I forgot to say that I will have a look at the CPU0 hotplug but not
on this series.

Best regards,

Mylène

> 
> If you have any remarks/questions, let me know.
> Thank you in advance,
> Mylène
> 
> Changes from v6:
> - Correct the commit log on patch 07 according to Sergei Shtylyov's
> review.
> - Rename the field "is_sun8i" into "is_a83t".
> - Add all Tested-by and Reviewed-by from previous version.
> 
> Changes from v5:
> - Remove my patch 01 and use the patch of Doug Berger to be able to
> include the cpu-type header on assembly files.
> - Rename smp_init_cntvoff function into secure_cntvoff_init according
> to Marc Zyngier's review.
> - According to Chen-Yu and Maxime's reviews, remove the patch that was
> moving structures. Instead of using an index to retrieve which
> architecture we are having, use a global variable.
> - Merge the 2 patches that move assembly code from C to assembly file.
> - Use a sun8i field instead of sun9i to know on which architecture we
> are using because many modifications/additions of the code are for
> sun8i-a83t.
> - Rework the patch "add is_sun8i field" to add only this field in this
> patch. The part of the patch that was starting to handle the differences
> between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
> support of sun8i-a83t.
> - Add a new patch that refactor the shmobile code to use the new function
> secure_cntvoff_init introduced in this series.
> 
> Changes from v4:
> - Rebased my series according to new Chen-Yu series:
>"ARM: sunxi: Clean and improvements for multi-cluster SMP"
>https://lkml.org/lkml/2018/3/8/886
> - Updated my series according to Marc Zyngier's reviews to add CNTVOFF
> initialization's function into ARM's common part. Thanks to that, other
> platforms such as Renesa can use this function.
> - For boot CPU, create a new machine to handle the CNTVOFF initialization
> using "init_early" callback.
> 
> Changes from v3:
> - Take into account Maxime's reviews:
>   - split the first patch into 4 new patches: add sun9i device tree
>   parsing, rename some variables, add a83t support and finally,
>   add hotplug support.
>   - Move the code of previous patch 07 (to disable CPU0 disabling)
>   into hotplug support patch (see patch 04)
>   - Remove the patch that added PRCM register because it is already
>   available. Because of that, update the device tree parsing to use
>   "sun8i-a83t-r-ccu".
>   - Use a variable to know which SoC we currently have
> - Take into account Chen-Yu's reviews: create two iounmap functions
> to release the resources of the device tree parsing.
> - Take into account Marc's review: Update the code to initialize CNTVOFF
> register. As there is already assembly code in the driver, I decided
> to create an assembly file not to mix assembly and C code.
> For that, I create 3 new patches: move the current assembly code that
> handles the cluster cache enabling into a file, move the cpu_resume entry
> in this file and finally, add a new assembly entry to initialize the timer
> offset for boot CPU and secondary CPUs.
> 
> Changes from v2:
> - Rebased my modifications according to new Chen Yu's patch series
> that adds SMP support for sun9i-a80 (without MCPM).
> - Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
> and PRCM registers for more visibility.
> - The hotplug of CPU0 is currently not working (even after trying what
> Allwinner's code is doing) so remove the possibility of disabling
> this CPU. Created a new patch for it.
> 
> Changes from v1:
> - Add Chen Yu's patch in my series (see path 01)
> - Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
> Create two functions to separate the DT parsing of sun9i-a80 and
> sun8i-a83t.
> - Thanks to Maxime's review: order device tree's nodes according
> to physical addresses, remove unused label and fix registers' sizes.
> Update the commit log and commit title of my last patch (see
> patch 05).
> 
> Mylène Josserand (11):
>   ARM: sunxi: smp: Move assembly code into a file
>   ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
>   ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
>   ARM: dts: sun8i: a83t: Add CCI-400 node
>   ARM: smp: Add initialization of CNTVOFF
>   ARM: sunxi: Add 

[PATCH v7 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Mylène Josserand]

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 32992afa0b12..7974eaba57a7 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -933,6 +933,11 @@
#reset-cells = <1>;
};
 
+   r_cpucfg@1f01c00 {
+   compatible = "allwinner,sun8i-a83t-r-cpucfg";
+   reg = <0x1f01c00 0x400>;
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

[PATCH v7 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node

[Mylène Josserand]

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7974eaba57a7..42539267e329 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <0>;
};
 
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <1>;
};
 
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <2>;
};
 
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <3>;
};
 
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x100>;
};
 
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x101>;
};
 
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x102>;
};
 
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x0170 0x400>;
};
 
+   cci@179 {
+   compatible = "arm,cci-400";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0179 0x1>;
+   ranges = <0x0 0x0179 0x1>;
+
+   cci_control0: slave-if@4000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x4000 0x1000>;
+   };
+
+   cci_control1: slave-if@5000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x5000 0x1000>;
+   };
+
+   pmu@9000 {
+   compatible = "arm,cci-400-pmu,r1";
+   reg = <0x9000 0x5000>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v7 02/11] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

[Mylène Josserand]

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 568307639be8..32992afa0b12 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
};
};
 
+   cpucfg@170 {
+   compatible = "allwinner,sun8i-a83t-cpucfg";
+   reg = <0x0170 0x400>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v7 08/11] ARM: sun9i: smp: Add is_a83t field

[Mylène Josserand]

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/mc_smp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..48e5f4db64b6 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static int is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
const char *enable_method;
int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+   int is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -697,6 +699,8 @@ static int __init sunxi_mc_smp_init(void)
break;
}
 
+   is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
of_node_put(node);
if (ret)
return -ENODEV;
-- 
2.11.0

[PATCH v7 05/11] ARM: smp: Add initialization of CNTVOFF

[Mylène Josserand]

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---
 arch/arm/common/Makefile  |  1 +
 arch/arm/common/secure_cntvoff.S  | 31 +++
 arch/arm/include/asm/secure_cntvoff.h |  8 
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)   += dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
 obj-$(CONFIG_SHARP_PARAM)  += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)  += scoop.o
+obj-$(CONFIG_SMP)  += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o 
vlock.o
 CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index ..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include 
+#include 
+
+ENTRY(secure_cntvoff_init)
+   .arch   armv7-a
+   /*
+* CNTVOFF has to be initialized either from non-secure Hypervisor
+* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+* then it should be handled by the secure code
+*/
+   cps #MON_MODE
+   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
+   orr r0, r1, #1
+   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
+   isb
+   mov r0, #0
+   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+   isb
+   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
+   isb
+   cps #SVC_MODE
+   ret lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h 
b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index ..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

[PATCH v7 06/11] ARM: sunxi: Add initialization of CNTVOFF

[Mylène Josserand]

Add the initialization of CNTVOFF for sun8i-a83t.

For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because of that, this function can't be called in SMP's early_initcall
function which is called after timer's init.

For secondary CPUs, add this function into secondary_startup
assembly entry.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/headsmp.S |  1 +
 arch/arm/mach-sunxi/sunxi.c   | 20 +++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
index 37dc772701f3..32d76be98541 100644
--- a/arch/arm/mach-sunxi/headsmp.S
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
 
 ENTRY(sunxi_mc_smp_secondary_startup)
bl  sunxi_mc_smp_cluster_cache_enable
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(sunxi_mc_smp_secondary_startup)
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..ddc439f6269b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 
 static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
-   "allwinner,sun8i-a83t",
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.dt_compat  = sun8i_board_dt_compat,
 MACHINE_END
 
+void __init sun8i_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+   secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_cntvoff_board_dt_compat[] = {
+   "allwinner,sun8i-a83t",
+   NULL,
+};
+
+DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")
+   .init_early = sun8i_cntvoff_init,
+   .init_time  = sun6i_timer_init,
+   .dt_compat  = sun8i_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
"allwinner,sun9i-a80",
NULL,
-- 
2.11.0

[PATCH v7 07/11] ARM: sun9i: smp: Rename clusters's power-off

[Mylène Josserand]

To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
/* clear cluster power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
/* gate cluster power */
pr_debug("%s: gate cluster power\n", __func__);
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
-- 
2.11.0

[PATCH v7 09/11] ARM: sun8i: smp: Add support for A83T

[Mylène Josserand]

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/Kconfig  |   2 +-
 arch/arm/mach-sunxi/mc_smp.c | 151 ++-
 2 files changed, 137 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
bool
depends on SMP
-   default MACH_SUN9I
+   default MACH_SUN9I || MACH_SUN8I
select ARM_CCI400_PORT_CTRL
select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 48e5f4db64b6..4fd2267ecb04 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST  BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)   BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I   BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)   BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC00xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC10x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   /* assert cpu power-on reset */
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 0)
+   cpu = 4;
+   }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 4)
+   cpu = 0;
+   }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if (cluster >= SUNXI_NR_CLUSTERS)
return -EINVAL;
 
+   /* For 

[PATCH v7 11/11] ARM: shmobile: Convert file to use cntvoff

[Mylène Josserand]

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---
 arch/arm/mach-shmobile/common.h  |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S 
b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include 
 #include 
 
-ENTRY(shmobile_init_cntvoff)
-   /*
-* CNTVOFF has to be initialized either from non-secure Hypervisor
-* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-* then it should be handled by the secure code
-*/
-   cps #MON_MODE
-   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
-   orr r0, r1, #1
-   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
-   instr_sync
-   mov r0, #0
-   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
-   instr_sync
-   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
-   instr_sync
-   cps #SVC_MODE
-   ret lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-   bl  shmobile_init_cntvoff
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
 
-   shmobile_init_cntvoff();
+   secure_cntvoff_init();
 
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

[PATCH v7 10/11] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

[Mylène Josserand]

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 42539267e329..c9b60047b0b8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
 
@@ -75,6 +76,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
 
@@ -83,6 +85,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
 
@@ -91,6 +94,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
 
@@ -101,6 +105,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
 
@@ -109,6 +114,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
 
@@ -117,6 +123,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
 
@@ -125,6 +132,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
-- 
2.11.0

[PATCH v7 01/11] ARM: sunxi: smp: Move assembly code into a file

[Mylène Josserand]

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/Makefile  |  4 +--
 arch/arm/mach-sunxi/headsmp.S | 80 +
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++
 3 files changed, 85 insertions(+), 81 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..7f45071ae74a 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,3 @@
-CFLAGS_mc_smp.o+= -march=armv7-a
-
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index ..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai 
+ * Mylène Josserand 
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+   .arch   armv7-a
+   /*
+* Enable cluster-level coherency, in preparation for turning on the 
MMU.
+*
+* Also enable regional clock gating and L2 data latency settings for
+* Cortex-A15. These settings are from the vendor kernel.
+*/
+   mrc p15, 0, r1, c0, c0, 0
+   movwr2, #(ARM_CPU_PART_MASK & 0x)
+   movtr2, #(ARM_CPU_PART_MASK >> 16)
+   and r1, r1, r2
+   movwr2, #(ARM_CPU_PART_CORTEX_A15 & 0x)
+   movtr2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+   cmp r1, r2
+   bne not_a15
+
+   /* The following is Cortex-A15 specific */
+
+   /* ACTLR2: Enable CPU regional clock gates */
+   mrc p15, 1, r1, c15, c0, 4
+   orr r1, r1, #(0x1 << 31)
+   mcr p15, 1, r1, c15, c0, 4
+
+   /* L2ACTLR */
+   mrc p15, 1, r1, c15, c0, 0
+   /* Enable L2, GIC, and Timer regional clock gates */
+   orr r1, r1, #(0x1 << 26)
+   /* Disable clean/evict from being pushed to external */
+   orr r1, r1, #(0x1<<3)
+   mcr p15, 1, r1, c15, c0, 0
+
+   /* L2CTRL: L2 data RAM latency */
+   mrc p15, 1, r1, c9, c0, 2
+   bic r1, r1, #(0x7 << 0)
+   orr r1, r1, #(0x3 << 0)
+   mcr p15, 1, r1, c9, c0, 2
+
+   /* End of Cortex-A15 specific setup */
+   not_a15:
+
+   /* Get value of sunxi_mc_smp_first_comer */
+   adr r1, first
+   ldr r0, [r1]
+   ldr r0, [r1, r0]
+
+   /* Skip cci_enable_port_for_self if not first comer */
+   cmp r0, #0
+   bxeqlr
+   b   cci_enable_port_for_self
+
+   .align 2
+   first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-   asm volatile (
-   "mrcp15, 0, r1, c0, c0, 0\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0x) "\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-   "andr1, r1, r2\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0x) 
"\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
-

[PATCH v7 00/11] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V7 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files:
https://lkml.org/lkml/2018/2/23/1263
(applied on Broadcom's tree: 
https://github.com/Broadcom/stblinux/commits/soc/next)

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes from v6:
- Correct the commit log on patch 07 according to Sergei Shtylyov's
review.
- Rename the field "is_sun8i" into "is_a83t".
- Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes from v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.

Changes from v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes from v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes from v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
patch 05).

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: sun9i: smp: Add is_a83t field
  ARM: sun8i: smp: Add support for A83T
  ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
  ARM: shmobile: Convert file to use cntvoff

 arch/arm/boot/dts/sun8i-a83t.dtsi|  59 
 arch/arm/common/Makefile |   1 +
 

[PATCH v7 00/11] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V7 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files:
https://lkml.org/lkml/2018/2/23/1263
(applied on Broadcom's tree: 
https://github.com/Broadcom/stblinux/commits/soc/next)

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes from v6:
- Correct the commit log on patch 07 according to Sergei Shtylyov's
review.
- Rename the field "is_sun8i" into "is_a83t".
- Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes from v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.

Changes from v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes from v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes from v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
patch 05).

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: sun9i: smp: Add is_a83t field
  ARM: sun8i: smp: Add support for A83T
  ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
  ARM: shmobile: Convert file to use cntvoff

 arch/arm/boot/dts/sun8i-a83t.dtsi|  59 
 arch/arm/common/Makefile |   1 +
 

Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add MMC support

[Sergei Shtylyov]

On 04/20/2018 12:58 PM, Simon Horman wrote:

>> Define the generic R8A77980 part of the MMC0 (SDHI2) device node.
>>
>> Signed-off-by: Sergei Shtylyov 
>>
>> ---
>>  arch/arm64/boot/dts/renesas/r8a77980.dtsi |   12 
>>  1 file changed, 12 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> @@ -371,6 +371,18 @@
>>  dma-channels = <16>;
>>  };
>>  
>> +mmc0: mmc@ee14 {
> 
> Please use sdhi2: sd@ee14 for consistency with other SoCs
> (I refereed to the r8a7795).

   Mmm... note that this controller has MMC signals (8 data bits, DS, no CD/WP),
see manual v0.55. I think it's more correct to call it MMC0 (trken from the
manual as well)...

MBR, Sergei

Re: [PATCH 0/8] arm: renesas: Change platform dependency to ARCH_RENESAS

[Mark Brown]

On Fri, Apr 20, 2018 at 03:28:26PM +0200, Geert Uytterhoeven wrote:

> The first 6 patches can be applied independently by subsystem
> maintainers.
> The last two patches depend on the first 6 patches, and are thus marked
> RFC.

Would it not make sense to try to apply everything en masse rather than
delaying?  I'm happy to apply the subsystem stuff but if it gets things
done quicker or more efficiently I'm also happy to have the lot merged
as one series.


signature.asc
Description: PGP signature

Re: [PATCH 2/2] arm64: dts: renesas: condor: add eMMC support

[Sergei Shtylyov]

On 04/20/2018 01:03 PM, Simon Horman wrote:

>> Define the Condor board dependent part of the MMC0 (connected to eMMC chip)
>> device node along with the necessary voltage regulators...
>>
>> Signed-off-by: Sergei Shtylyov 
>>
>> ---
>>  arch/arm64/boot/dts/renesas/r8a77980-condor.dts |   43 
>> 
>>  1 file changed, 43 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> ===
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> @@ -27,6 +27,24 @@
>>  /* first 128MB is reserved for secure area. */
>>  reg = <0 0x4800 0 0x7800>;
>>  };
>> +
>> +d3_3v: regulator-0 {
> 
> Please use reg_3p3v: regulator1 for consistency with salvator-common.dtsi

   Hm, not sure why I have to copy what I consider a bad example... the SoCs are
not pin compatible anyway. 

>> +compatible = "regulator-fixed";
>> +regulator-name = "D3.3V";
> 
> And "fixed-3.3V"

   Ugh. That's pretty poor name I think. My names do correspond to the 
schematics
and these only muddle things up, I think...

[...]
>> @@ -70,6 +101,18 @@
>>  function = "avb";
>>  };
>>  
>> +mmc_1_8v_pins: mmc_1_8v {
>> +groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
>> +function = "mmc";
>> +power-source = <1800>;
>> +};
>> +
>> +mmc_3_3v_pins: mmc_3_3v {
>> +groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
>> +function = "mmc";
>> +power-source = <3300>;
>> +};
> 
> Again please make this more consistent with salvator-common.dtsi.

   Ah, you mean the _uhs label name postfix? OK...

[...]

MBR, Sergei

Re: [PATCH 0/3] Add R8A77980/Condor PFC support

[Sergei Shtylyov]

On 03/09/2018 03:04 PM, Sergei Shtylyov wrote:

> Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180308-v4.16-rc4' tag.  We're adding the R8A77980 PFC node
> and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> These patches depend on the R8A77980 PFC support in order to work properly.

  ... and their time has finally come! Please merge.

> [1/3] arm64: dts: renesas: r8a77980: add PFC support
> [2/3] arm64: dts: renesas: condor: add SCIF0 pins
> [3/3] arm64: dts: renesas: condor: add EtherAVB pins

WBR, Sergei

Applied "spi: simplify getting .drvdata" to the spi tree

[Mark Brown]

The patch

   spi: simplify getting .drvdata

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From e1f16b0493a01820a137ebbdd96bf695e427fabe Mon Sep 17 00:00:00 2001
From: Wolfram Sang 
Date: Thu, 19 Apr 2018 16:06:16 +0200
Subject: [PATCH] spi: simplify getting .drvdata

We should get drvdata from struct device directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang 
Acked-by: Michal Simek 
Signed-off-by: Mark Brown 
---
 drivers/spi/spi-cadence.c  | 6 ++
 drivers/spi/spi-zynqmp-gqspi.c | 6 ++
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 5c9516ae4942..de394422b611 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -686,8 +686,7 @@ static int cdns_spi_remove(struct platform_device *pdev)
  */
 static int __maybe_unused cdns_spi_suspend(struct device *dev)
 {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct spi_master *master = platform_get_drvdata(pdev);
+   struct spi_master *master = dev_get_drvdata(dev);
 
return spi_master_suspend(master);
 }
@@ -702,8 +701,7 @@ static int __maybe_unused cdns_spi_suspend(struct device 
*dev)
  */
 static int __maybe_unused cdns_spi_resume(struct device *dev)
 {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct spi_master *master = platform_get_drvdata(pdev);
+   struct spi_master *master = dev_get_drvdata(dev);
struct cdns_spi *xspi = spi_master_get_devdata(master);
 
cdns_spi_init_hw(xspi);
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 26d1ac3bf496..cc4d31033494 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -906,8 +906,7 @@ static int zynqmp_qspi_start_transfer(struct spi_master 
*master,
  */
 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
 {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct spi_master *master = platform_get_drvdata(pdev);
+   struct spi_master *master = dev_get_drvdata(dev);
 
spi_master_suspend(master);
 
@@ -927,8 +926,7 @@ static int __maybe_unused zynqmp_qspi_suspend(struct device 
*dev)
  */
 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
 {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct spi_master *master = platform_get_drvdata(pdev);
+   struct spi_master *master = dev_get_drvdata(dev);
struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
int ret = 0;
 
-- 
2.17.0

Applied "ASoC: atmel: simplify getting .drvdata" to the asoc tree

[Mark Brown]

The patch

   ASoC: atmel: simplify getting .drvdata

has been applied to the asoc tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From c0380478139fce887b948b35dc0dcee0b40bdf09 Mon Sep 17 00:00:00 2001
From: Wolfram Sang 
Date: Thu, 19 Apr 2018 16:06:31 +0200
Subject: [PATCH] ASoC: atmel: simplify getting .drvdata

We should get drvdata from struct device directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang 
Signed-off-by: Mark Brown 
---
 sound/soc/atmel/atmel_ssc_dai.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
index 1c7af0ca98ec..d3b69682d9c2 100644
--- a/sound/soc/atmel/atmel_ssc_dai.c
+++ b/sound/soc/atmel/atmel_ssc_dai.c
@@ -1002,8 +1002,7 @@ static const struct snd_soc_component_driver 
atmel_ssc_component = {
 
 static int asoc_ssc_init(struct device *dev)
 {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct ssc_device *ssc = platform_get_drvdata(pdev);
+   struct ssc_device *ssc = dev_get_drvdata(dev);
int ret;
 
ret = snd_soc_register_component(dev, _ssc_component,
@@ -1033,8 +1032,7 @@ static int asoc_ssc_init(struct device *dev)
 
 static void asoc_ssc_exit(struct device *dev)
 {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct ssc_device *ssc = platform_get_drvdata(pdev);
+   struct ssc_device *ssc = dev_get_drvdata(dev);
 
if (ssc->pdata->use_dma)
atmel_pcm_dma_platform_unregister(dev);
-- 
2.17.0

Applied "ASoC: sh: Drop SUPERH platform dependency" to the asoc tree

[Mark Brown]

The patch

   ASoC: sh: Drop SUPERH platform dependency

has been applied to the asoc tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 4070d91754039e88f7b64e462f3d0d8cdb4be041 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven 
Date: Fri, 20 Apr 2018 16:22:14 +0200
Subject: [PATCH] ASoC: sh: Drop SUPERH platform dependency

The SIU sound peripheral is used only on SuperH SH-Mobile platforms.
As both SUPERH and ARCH_SHMOBILE are set for these platforms, the SUPERH
dependency can be dropped.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Mark Brown 
---
 sound/soc/sh/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
index 1aa5cd77ca24..365f46321147 100644
--- a/sound/soc/sh/Kconfig
+++ b/sound/soc/sh/Kconfig
@@ -28,7 +28,7 @@ config SND_SOC_SH4_FSI
 
 config SND_SOC_SH4_SIU
tristate
-   depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
+   depends on ARCH_SHMOBILE && HAVE_CLK
select DMA_ENGINE
select DMADEVICES
select SH_DMAE
-- 
2.17.0

Re: Potential problem with 31e77c93e432dec7 ("sched/fair: Update blocked load when newly idle")

[Joel Fernandes]

On Fri, Apr 20, 2018 at 9:00 AM, Vincent Guittot
 wrote:
[..]
>
> Le Saturday 14 Apr 2018 à 13:24:20 (+0200), Vincent Guittot a écrit :
>> Hi Niklas,
>>
>> On 13 April 2018 at 00:39, Niklas Söderlund
>>  wrote:
>> > Hi Vincent,
>> >
>> > Thanks for helping trying to figure this out.
>> >
>> > On 2018-04-12 15:30:31 +0200, Vincent Guittot wrote:
>> >
>> > [snip]
>> >
>> >>
>> >> I'd like to narrow the problem a bit more with the 2 patchies aboves. Can 
>> >> you try
>> >> them separatly on top of c18bb396d3d261eb ("Merge 
>> >> git://git.kernel.org/pub/scm/linux/kernel/git/davem/net"))
>> >> and check if one of them fixes the problem ?i
>> >
>> > I tried your suggested changes based on top of c18bb396d3d261eb.
>> >
>> >>
>> >> (They should apply on linux-next as well)
>> >>
>> >> First patch always kick ilb instead of doing ilb on local cpu before 
>> >> entering idle
>> >>
>> >> ---
>> >>  kernel/sched/fair.c | 3 +--
>> >>  1 file changed, 1 insertion(+), 2 deletions(-)
>> >>
>> >> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
>> >> index 0951d1c..b21925b 100644
>> >> --- a/kernel/sched/fair.c
>> >> +++ b/kernel/sched/fair.c
>> >> @@ -9739,8 +9739,7 @@ static void nohz_newidle_balance(struct rq *this_rq)
>> >>* candidate for ilb instead of waking up another idle CPU.
>> >>* Kick an normal ilb if we failed to do the update.
>> >>*/
>> >> - if (!_nohz_idle_balance(this_rq, NOHZ_STATS_KICK, CPU_NEWLY_IDLE))
>> >> - kick_ilb(NOHZ_STATS_KICK);
>> >> + kick_ilb(NOHZ_STATS_KICK);
>> >>   raw_spin_lock(_rq->lock);
>> >>  }
>> >
>> > This change don't seem to effect the issue. I can still get the single
>> > ssh session and the system to lockup by hitting the return key. And
>> > opening a second ssh session immediately unblocks both the first ssh
>> > session and the serial console. And I can still trigger the console
>> > warning by just letting the system be once it locks-up. I do have
>> > just as before reset the system a few times to trigger the issue.
>>
>> You results are similar to Heiner's ones. The problem is still there
>> even if we only kick ilb which mainly send an IPI reschedule to the
>> other CPU if Idle
>>
>
> Could it be possible to record some traces of the problem to get a better view
> of what happens ?
>
> I have a small patch that adds some traces in the functions that seems to 
> create
> the problem
>
> ---
>  kernel/sched/fair.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index 0951d1c..a951464 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -9606,6 +9606,8 @@ static bool _nohz_idle_balance(struct rq *this_rq, 
> unsigned int flags,
>  */
> WRITE_ONCE(nohz.has_blocked, 0);
>
> +   trace_printk("_nohz_idle_balance cpu %d idle %d flag %x", this_cpu, 
> idle, flags);
> +
> /*
>  * Ensures that if we miss the CPU, we must see the has_blocked
>  * store from nohz_balance_enter_idle().
> @@ -9680,6 +9682,8 @@ static bool _nohz_idle_balance(struct rq *this_rq, 
> unsigned int flags,
> if (likely(update_next_balance))
> nohz.next_balance = next_balance;
>
> +   trace_printk("_nohz_idle_balance return %d", ret);
> +
> return ret;
>  }
>
> @@ -9732,6 +9736,8 @@ static void nohz_newidle_balance(struct rq *this_rq)
> time_before(jiffies, READ_ONCE(nohz.next_blocked)))
> return;
>
> +   trace_printk("nohz_newidle_balance start update");
> +
> raw_spin_unlock(_rq->lock);
> /*
>  * This CPU is going to be idle and blocked load of idle CPUs
> --
> 2.7.4
>
>
> Also that would be good to stop tracing when the RCU stall happens
>
> In case you are not familiar with the trace tool, I have put below how to 
> configure ftrace to trace scheudler, irq, timer ... events and stop tracing 
> when dump_backtrace function is called
>
> trace-cmd reset > /dev/null
> trace-cmd start -b 4 -p function -l dump_backtrace:traceoff -e sched -e 
> cpu_idle -e cpu_frequency -e timer -e ipi -e irq -e printk
> trace-cmd start -b 4 -p function -l dump_backtrace
>
> The trace-cmd start has to be called twice to make sure that we will not 
> trace all function
>
> Once the dump happen and the trace is stopped, you can extract the traces with
>
> trace-cmd extract -o 

Just adding to that (and... Feel free to use or ignore these tips)
To prevent the trace_printk from getting lost in the trace flood, you
can also call tracing_stop() from wherever the problem is detected and
look at the last set of messages which is easier. Also you can dump
the ftrace buffer to the kernel logs before the lock up, using
ftrace_dump() and when you do that you probably want to limit the
ftrace buffer size.

thanks,

- Joel

Re: Potential problem with 31e77c93e432dec7 ("sched/fair: Update blocked load when newly idle")

[Vincent Guittot]

Hi Heiner and Niklas,

Le Saturday 14 Apr 2018 à 13:24:20 (+0200), Vincent Guittot a écrit :
> Hi Niklas,
> 
> On 13 April 2018 at 00:39, Niklas Söderlund
>  wrote:
> > Hi Vincent,
> >
> > Thanks for helping trying to figure this out.
> >
> > On 2018-04-12 15:30:31 +0200, Vincent Guittot wrote:
> >
> > [snip]
> >
> >>
> >> I'd like to narrow the problem a bit more with the 2 patchies aboves. Can 
> >> you try
> >> them separatly on top of c18bb396d3d261eb ("Merge 
> >> git://git.kernel.org/pub/scm/linux/kernel/git/davem/net"))
> >> and check if one of them fixes the problem ?i
> >
> > I tried your suggested changes based on top of c18bb396d3d261eb.
> >
> >>
> >> (They should apply on linux-next as well)
> >>
> >> First patch always kick ilb instead of doing ilb on local cpu before 
> >> entering idle
> >>
> >> ---
> >>  kernel/sched/fair.c | 3 +--
> >>  1 file changed, 1 insertion(+), 2 deletions(-)
> >>
> >> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> >> index 0951d1c..b21925b 100644
> >> --- a/kernel/sched/fair.c
> >> +++ b/kernel/sched/fair.c
> >> @@ -9739,8 +9739,7 @@ static void nohz_newidle_balance(struct rq *this_rq)
> >>* candidate for ilb instead of waking up another idle CPU.
> >>* Kick an normal ilb if we failed to do the update.
> >>*/
> >> - if (!_nohz_idle_balance(this_rq, NOHZ_STATS_KICK, CPU_NEWLY_IDLE))
> >> - kick_ilb(NOHZ_STATS_KICK);
> >> + kick_ilb(NOHZ_STATS_KICK);
> >>   raw_spin_lock(_rq->lock);
> >>  }
> >
> > This change don't seem to effect the issue. I can still get the single
> > ssh session and the system to lockup by hitting the return key. And
> > opening a second ssh session immediately unblocks both the first ssh
> > session and the serial console. And I can still trigger the console
> > warning by just letting the system be once it locks-up. I do have
> > just as before reset the system a few times to trigger the issue.
> 
> You results are similar to Heiner's ones. The problem is still there
> even if we only kick ilb which mainly send an IPI reschedule to the
> other CPU if Idle
> 

Could it be possible to record some traces of the problem to get a better view
of what happens ?

I have a small patch that adds some traces in the functions that seems to create
the problem

---
 kernel/sched/fair.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 0951d1c..a951464 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -9606,6 +9606,8 @@ static bool _nohz_idle_balance(struct rq *this_rq, 
unsigned int flags,
 */
WRITE_ONCE(nohz.has_blocked, 0);
 
+   trace_printk("_nohz_idle_balance cpu %d idle %d flag %x", this_cpu, 
idle, flags);
+
/*
 * Ensures that if we miss the CPU, we must see the has_blocked
 * store from nohz_balance_enter_idle().
@@ -9680,6 +9682,8 @@ static bool _nohz_idle_balance(struct rq *this_rq, 
unsigned int flags,
if (likely(update_next_balance))
nohz.next_balance = next_balance;
 
+   trace_printk("_nohz_idle_balance return %d", ret);
+
return ret;
 }
 
@@ -9732,6 +9736,8 @@ static void nohz_newidle_balance(struct rq *this_rq)
time_before(jiffies, READ_ONCE(nohz.next_blocked)))
return;
 
+   trace_printk("nohz_newidle_balance start update");
+
raw_spin_unlock(_rq->lock);
/*
 * This CPU is going to be idle and blocked load of idle CPUs
-- 
2.7.4


Also that would be good to stop tracing when the RCU stall happens

In case you are not familiar with the trace tool, I have put below how to 
configure ftrace to trace scheudler, irq, timer ... events and stop tracing 
when dump_backtrace function is called

trace-cmd reset > /dev/null
trace-cmd start -b 4 -p function -l dump_backtrace:traceoff -e sched -e 
cpu_idle -e cpu_frequency -e timer -e ipi -e irq -e printk
trace-cmd start -b 4 -p function -l dump_backtrace

The trace-cmd start has to be called twice to make sure that we will not trace 
all function

Once the dump happen and the trace is stopped, you can extract the traces with 

trace-cmd extract -o 

Thanks
Vincent

[PATCH 4/4] ARM: dts: r8a77470: Add SCIF DMA support

[Biju Das]

Add SCIF DMA support for R8A77470 SoC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 arch/arm/boot/dts/r8a77470.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 39549f2..baec3ca 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -198,6 +198,9 @@
clocks = < CPG_MOD 721>,
 < CPG_CORE 5>, <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x29>, < 0x2a>,
+  < 0x29>, < 0x2a>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < 32>;
resets = < 721>;
status = "disabled";
@@ -211,6 +214,9 @@
clocks = < CPG_MOD 720>,
 < CPG_CORE 5>, <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x2d>, < 0x2e>,
+  < 0x2d>, < 0x2e>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < 32>;
resets = < 720>;
status = "disabled";
@@ -224,6 +230,9 @@
clocks = < CPG_MOD 719>,
 < CPG_CORE 5>, <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x2b>, < 0x2c>,
+  < 0x2b>, < 0x2c>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < 32>;
resets = < 719>;
status = "disabled";
@@ -237,6 +246,9 @@
clocks = < CPG_MOD 718>,
 < CPG_CORE 5>, <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x2f>, < 0x30>,
+  < 0x2f>, < 0x30>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < 32>;
resets = < 718>;
status = "disabled";
@@ -250,6 +262,9 @@
clocks = < CPG_MOD 715>,
 < CPG_CORE 5>, <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0xfb>, < 0xfc>,
+  < 0xfb>, < 0xfc>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < 32>;
resets = < 715>;
status = "disabled";
@@ -263,6 +278,9 @@
clocks = < CPG_MOD 714>,
 < CPG_CORE 5>, <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0xfd>, < 0xfe>,
+  < 0xfd>, < 0xfe>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < 32>;
resets = < 714>;
status = "disabled";
-- 
2.7.4

[PATCH 3/4] ARM: dts: r8a77470: Add SCIF support

[Biju Das]

Describe SCIF ports in the R8A77470 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 arch/arm/boot/dts/r8a77470.dtsi | 69 +++--
 1 file changed, 67 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 2f89f33..39549f2 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -190,19 +190,84 @@
dma-channels = <15>;
};
 
+   scif0: serial@e6e6 {
+   compatible = "renesas,scif-r8a77470",
+"renesas,rcar-gen2-scif", "renesas,scif";
+   reg = <0 0xe6e6 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 721>,
+< CPG_CORE 5>, <_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < 32>;
+   resets = < 721>;
+   status = "disabled";
+   };
+
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77470",
 "renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
interrupts = ;
-   clocks = < CPG_MOD 720>,
-< CPG_CORE 6>, <_clk>;
+   clocks = < CPG_MOD 720>,
+< CPG_CORE 5>, <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = < 32>;
resets = < 720>;
status = "disabled";
};
 
+   scif2: serial@e6e58000 {
+   compatible = "renesas,scif-r8a77470",
+"renesas,rcar-gen2-scif", "renesas,scif";
+   reg = <0 0xe6e58000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 719>,
+< CPG_CORE 5>, <_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < 32>;
+   resets = < 719>;
+   status = "disabled";
+   };
+
+   scif3: serial@e6ea8000 {
+   compatible = "renesas,scif-r8a77470",
+"renesas,rcar-gen2-scif", "renesas,scif";
+   reg = <0 0xe6ea8000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 718>,
+< CPG_CORE 5>, <_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < 32>;
+   resets = < 718>;
+   status = "disabled";
+   };
+
+   scif4: serial@e6ee {
+   compatible = "renesas,scif-r8a77470",
+"renesas,rcar-gen2-scif", "renesas,scif";
+   reg = <0 0xe6ee 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 715>,
+< CPG_CORE 5>, <_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < 32>;
+   resets = < 715>;
+   status = "disabled";
+   };
+
+   scif5: serial@e6ee8000 {
+   compatible = "renesas,scif-r8a77470",
+"renesas,rcar-gen2-scif", "renesas,scif";
+   reg = <0 0xe6ee8000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 714>,
+< CPG_CORE 5>, <_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < 32>;
+   resets = < 714>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
-- 
2.7.4

[PATCH 0/4] Add SYS-DMAC, IRQC and SCIF to SoC dtsi

[Biju Das]

This patch series add support for SYS-DMAC, External interrupt
Controller(IRQC) and SCIF wth DMA support to the r8a77470 SoC dtsi

This patch series tested against renesas-dev branch 
tag "renesas-dev-20180420-v4.17-rc1"

Biju Das (4):
  ARM: dts: r8a77470: Add SYS-DMAC support
  ARM: dts: r8a77470: Add IRQC support
  ARM: dts: r8a77470: Add SCIF support
  ARM: dts: r8a77470: Add SCIF DMA support

 arch/arm/boot/dts/r8a77470.dtsi | 173 +++-
 1 file changed, 171 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH 2/4] ARM: dts: r8a77470: Add IRQC support

[Biju Das]

Describe the IRQC interrupt controller in the R8A77470 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 arch/arm/boot/dts/r8a77470.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index c39aceb..2f89f33 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -81,6 +81,26 @@
#power-domain-cells = <1>;
};
 
+   irqc: interrupt-controller@e61c {
+   compatible = "renesas,irqc-r8a77470", "renesas,irqc";
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   reg = <0 0xe61c 0 0x200>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   clocks = < CPG_MOD 407>;
+   power-domains = < 32>;
+   resets = < 407>;
+   };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
-- 
2.7.4

[PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support

[Biju Das]

Describe SYS-DMAC0/1 in the R8A77470 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 arch/arm/boot/dts/r8a77470.dtsi | 66 +
 1 file changed, 66 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 4578582..c39aceb 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -104,6 +104,72 @@
reg = <0 0xe630 0 0x2>;
};
 
+   dmac0: dma-controller@e670 {
+   compatible = "renesas,dmac-r8a77470",
+"renesas,rcar-dmac";
+   reg = <0 0xe670 0 0x2>;
+   interrupts = ;
+   interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+   clocks = < CPG_MOD 219>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 219>;
+   #dma-cells = <1>;
+   dma-channels = <15>;
+   };
+
+   dmac1: dma-controller@e672 {
+   compatible = "renesas,dmac-r8a77470",
+"renesas,rcar-dmac";
+   reg = <0 0xe672 0 0x2>;
+   interrupts = ;
+   interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+   clocks = < CPG_MOD 218>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 218>;
+   #dma-cells = <1>;
+   dma-channels = <15>;
+   };
+
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77470",
 "renesas,rcar-gen2-scif", "renesas,scif";
-- 
2.7.4

Re: [PATCH 4/8] sh_eth: Change platform check to CONFIG_ARCH_RENESAS

[Sergei Shtylyov]

On 04/20/2018 04:28 PM, Geert Uytterhoeven wrote:

> Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
> is CONFIG_ARCH_RENESAS a more appropriate platform check than the legacy
> CONFIG_ARCH_SHMOBILE, hence use the former.
> 
> Renesas SuperH SH-Mobile SoCs are still covered by the CONFIG_CPU_SH4
> check.
> 
> This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
> future.
> 
> Signed-off-by: Geert Uytterhoeven 
[...]

Acked-by: Sergei Shtylyov 

MBR, Sergei

Re: [PATCH] sh: mm: Fix unprotected access to struct device

[Rich Felker]

On Fri, Apr 20, 2018 at 11:59:13AM +0200, Geert Uytterhoeven wrote:
> Hi Christoph,
> 
> On Fri, Apr 20, 2018 at 10:31 AM, Christoph Hellwig  
> wrote:
> > On Wed, Apr 18, 2018 at 03:13:14PM +0200, jacopo mondi wrote:
> >> As long as it goes for arch/sh, the only user of dma_alloc_coherent()
> >> is platform_resource_setup_memory(), and it has been fixed by this
> >> patch.
> >
> > Great!
> >
> >> Unfortunately, as Thomas pointed out, there are drivers which calls
> >> into this with the wrong 'struct device' as the sh_eth one he had fixed.
> >
> > Yes, we'll need fixes there.  Other DMA ops implementations also look
> > at struct device, so they generally are buggy.
> >
> >> I would then say that as long as it goes for the NULL case, we should be
> >> fine now.
> >
> > Then I'd say skil that part, please.
> 
> The major reason for keeping the NULL WARN_ON() checks is to make it
> obvious to the developer what is wrong, and fall back to the old behavior.
> 
> Without the checks, the kernel will just crash during early startup,
> without a clue in the (missing) kernel output, usually leading to a
> frustrating bisection experience (if the developer is sufficiently motivated,
> at all).
> 
> Hence my vote for keeping the checks.

Sounds good to me.

Rich

Re: [PATCH 1/8] arm: shmobile: Change platform dependency to ARCH_RENESAS

[Sergei Shtylyov]

On 04/20/2018 04:28 PM, Geert Uytterhoeven wrote:

> Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
> is ARCH_RENESAS a more appropriate platform dependency than the legacy

   "ARCH_RENESAS is", no?

> ARCH_SHMOBILE, hence use the former.
> 
> This will allow to drop ARCH_SHMOBILE on ARM in the near future.
> 
> Signed-off-by: Geert Uytterhoeven 
[...]

MBR, Sergei

[PATCH] ASoC: sh: Drop SUPERH platform dependency

[Geert Uytterhoeven]

The SIU sound peripheral is used only on SuperH SH-Mobile platforms.
As both SUPERH and ARCH_SHMOBILE are set for these platforms, the SUPERH
dependency can be dropped.

Signed-off-by: Geert Uytterhoeven 
---
 sound/soc/sh/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
index c1b7fb91e3063f2b..0ae0800bf3a8b471 100644
--- a/sound/soc/sh/Kconfig
+++ b/sound/soc/sh/Kconfig
@@ -28,7 +28,7 @@ config SND_SOC_SH4_FSI
 
 config SND_SOC_SH4_SIU
tristate
-   depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
+   depends on ARCH_SHMOBILE && HAVE_CLK
select DMA_ENGINE
select DMADEVICES
select SH_DMAE
-- 
2.7.4

[PATCH] video: fbdev: sh_mobile_meram: Drop SUPERH platform dependency

[Geert Uytterhoeven]

Since commit a521422ea4ae6128 ("ARM: shmobile: mackerel: Remove Legacy C
board code"), the only remaining platforms using this driver are SuperH
SH-Mobile SoCs (sh7723).  As both SUPERH and ARCH_SHMOBILE are set for
these platforms, the SUPERH dependency can be dropped.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/video/fbdev/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index d94254263ea5caa7..434e95b9320ead05 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2348,7 +2348,7 @@ source "drivers/video/fbdev/mmp/Kconfig"
 
 config FB_SH_MOBILE_MERAM
tristate "SuperH Mobile MERAM read ahead support"
-   depends on (SUPERH || ARCH_SHMOBILE)
+   depends on ARCH_SHMOBILE
select GENERIC_ALLOCATOR
---help---
  Enable MERAM support for the SuperH controller.
-- 
2.7.4

Re: [PATCH 0/8] arm: renesas: Change platform dependency to ARCH_RENESAS

[Arnd Bergmann]

On Fri, Apr 20, 2018 at 3:28 PM, Geert Uytterhoeven
 wrote:
> Hi all,
>
> Commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
> started the conversion from ARCH_SHMOBILE to ARCH_RENESAS for Renesas
> ARM SoCs.  This patch series completes the conversion, by:
>   1. Updating dependencies for drivers that weren't converted yet,
>   2. Removing the ARCH_SHMOBILE Kconfig symbols on ARM and ARM64.
>
> The first 6 patches can be applied independently by subsystem
> maintainers.
> The last two patches depend on the first 6 patches, and are thus marked
> RFC.

This all looks fine to me.

Acked-by: Arnd Bergmann 

  Arnd

[PATCH/RFC 8/8] arm64: renesas: Remove the ARCH_SHMOBILE Kconfig symbol

[Geert Uytterhoeven]

The Kconfig symbol for Renesas 64-bit ARM SoCs has always been
ARCH_RENESAS, with ARCH_SHMOBILE being selected to reuse drivers shared
with Renesas 32-bit ARM and/or Renesas SuperH SH-Mobile SoCs.

Commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
started the conversion from ARCH_SHMOBILE to ARCH_RENESAS for Renesas
32-bit SoCs.  Now all drivers for Renesas ARM SoCs have gained proper
ARCH_RENESAS platform dependencies, there is no longer a need to select
ARCH_SHMOBILE.

With ARCH_SHMOBILE gone, move the ARCH_RENESAS section up, to restore
alphabetical sort order.

Signed-off-by: Geert Uytterhoeven 
---
This depends on the driver patches in this series, hence the RFC.

JFTR, after this, the following symbols for drivers supporting only
Renesas SuperH "SH-Mobile" SoCs can no longer be selected:
  - CONFIG_KEYBOARD_SH_KEYSC,
  - CONFIG_VIDEO_SH_VOU,
  - CONFIG_VIDEO_RENESAS_CEU,
  - CONFIG_FB_SH_MOBILE_MERAM.
(changes for a renesas_defconfig .config)
---
 arch/arm64/Kconfig.platforms | 42 +++---
 1 file changed, 19 insertions(+), 23 deletions(-)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index d5aeac351fc3a776..49d8ed1ab84766dd 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -145,31 +145,8 @@ config ARCH_REALTEK
  This enables support for the ARMv8 based Realtek chipsets,
  like the RTD1295.
 
-config ARCH_ROCKCHIP
-   bool "Rockchip Platforms"
-   select ARCH_HAS_RESET_CONTROLLER
-   select GPIOLIB
-   select PINCTRL
-   select PINCTRL_ROCKCHIP
-   select ROCKCHIP_TIMER
-   help
- This enables support for the ARMv8 based Rockchip chipsets,
- like the RK3368.
-
-config ARCH_SEATTLE
-   bool "AMD Seattle SoC Family"
-   help
- This enables support for AMD Seattle SOC Family
-
-config ARCH_SHMOBILE
-   bool
-
-config ARCH_SYNQUACER
-   bool "Socionext SynQuacer SoC Family"
-
 config ARCH_RENESAS
bool "Renesas SoC Platforms"
-   select ARCH_SHMOBILE
select PINCTRL
select PM
select PM_GENERIC_DOMAINS
@@ -220,6 +197,25 @@ config ARCH_R8A77995
help
  This enables support for the Renesas R-Car D3 SoC.
 
+config ARCH_ROCKCHIP
+   bool "Rockchip Platforms"
+   select ARCH_HAS_RESET_CONTROLLER
+   select GPIOLIB
+   select PINCTRL
+   select PINCTRL_ROCKCHIP
+   select ROCKCHIP_TIMER
+   help
+ This enables support for the ARMv8 based Rockchip chipsets,
+ like the RK3368.
+
+config ARCH_SEATTLE
+   bool "AMD Seattle SoC Family"
+   help
+ This enables support for AMD Seattle SOC Family
+
+config ARCH_SYNQUACER
+   bool "Socionext SynQuacer SoC Family"
+
 config ARCH_STRATIX10
bool "Altera's Stratix 10 SoCFPGA Family"
help
-- 
2.7.4

[PATCH/RFC 7/8] ARM: shmobile: Remove the ARCH_SHMOBILE Kconfig symbol

[Geert Uytterhoeven]

All drivers for Renesas ARM SoCs have gained proper ARCH_RENESAS
platform dependencies.  Hence finish the conversion from ARCH_SHMOBILE
to ARCH_RENESAS for Renesas 32-bit ARM SoCs, as started by commit
9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS").

Signed-off-by: Geert Uytterhoeven 
---
This depends on the previous patches in this series, hence the RFC.

JFTR, after this, the following symbols for drivers supporting only
Renesas SuperH "SH-Mobile" SoCs can no longer be selected:
  - CONFIG_KEYBOARD_SH_KEYSC,
  - CONFIG_VIDEO_SH_VOU,
  - CONFIG_VIDEO_SH_MOBILE_CEU,
  - CONFIG_DRM_SHMOBILE[*],
  - CONFIG_FB_SH_MOBILE_MERAM.
(changes for a shmobile_defconfig .config)

[*] CONFIG_DRM_SHMOBILE has a dependency on ARM, but it was never wired
up.  From the use of sh_mobile_meram, I guess it was meant for
SH-Mobile AP4 on Mackerel or AP4EVB, which are long gone.
So the only remaining upstream platforms that could make use of it
are legacy SuperH SH-Mobile SoCs?
---
 arch/arm/mach-shmobile/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 96672da02f5f17b9..d892c5b52b6f5627 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,3 @@
-config ARCH_SHMOBILE
-   bool
-
 config PM_RMOBILE
bool
select PM
@@ -30,7 +27,6 @@ menuconfig ARCH_RENESAS
bool "Renesas ARM SoCs"
depends on ARCH_MULTI_V7 && MMU
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
-   select ARCH_SHMOBILE
select ARM_GIC
select GPIOLIB
select HAVE_ARM_SCU if SMP
-- 
2.7.4

[PATCH 1/8] arm: shmobile: Change platform dependency to ARCH_RENESAS

[Geert Uytterhoeven]

Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
is ARCH_RENESAS a more appropriate platform dependency than the legacy
ARCH_SHMOBILE, hence use the former.

This will allow to drop ARCH_SHMOBILE on ARM in the near future.

Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/Kconfig  | 2 +-
 arch/arm/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a7f8e7f4b88fdd03..2d34c0a44877e85b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1467,7 +1467,7 @@ config ARM_PSCI
 config ARCH_NR_GPIO
int
default 2048 if ARCH_SOCFPGA
-   default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
+   default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
ARCH_ZYNQ
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e4e537f27339f7a1..a92f5a876d96839d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -212,7 +212,7 @@ machine-$(CONFIG_ARCH_S3C24XX)  += s3c24xx
 machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
 machine-$(CONFIG_ARCH_S5PV210) += s5pv210
 machine-$(CONFIG_ARCH_SA1100)  += sa1100
-machine-$(CONFIG_ARCH_SHMOBILE)+= shmobile
+machine-$(CONFIG_ARCH_RENESAS) += shmobile
 machine-$(CONFIG_ARCH_SIRF)+= prima2
 machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
 machine-$(CONFIG_ARCH_STI) += sti
-- 
2.7.4

[PATCH 2/8] dmaengine: shdmac: Change platform check to CONFIG_ARCH_RENESAS

[Geert Uytterhoeven]

Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
is CONFIG_ARCH_RENESAS a more appropriate platform check than the legacy
CONFIG_ARCH_SHMOBILE, hence use the former.

Renesas SuperH SH-Mobile SoCs are still covered by the CONFIG_CPU_SH4
check, just like before support for Renesas ARM SoCs was added.

Instead of blindly changing all the #ifdefs, switch the main code block
in sh_dmae_probe() to IS_ENABLED(), as this allows to remove all the
remaining #ifdefs.

This will allow to drop ARCH_SHMOBILE on ARM in the near future.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/dma/sh/shdmac.c | 50 +
 1 file changed, 21 insertions(+), 29 deletions(-)

diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
index 516f5487cc44cf96..8fcaae482ce0949a 100644
--- a/drivers/dma/sh/shdmac.c
+++ b/drivers/dma/sh/shdmac.c
@@ -440,7 +440,6 @@ static bool sh_dmae_reset(struct sh_dmae_device *shdev)
return ret;
 }
 
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 static irqreturn_t sh_dmae_err(int irq, void *data)
 {
struct sh_dmae_device *shdev = data;
@@ -451,7 +450,6 @@ static irqreturn_t sh_dmae_err(int irq, void *data)
sh_dmae_reset(shdev);
return IRQ_HANDLED;
 }
-#endif
 
 static bool sh_dmae_desc_completed(struct shdma_chan *schan,
   struct shdma_desc *sdesc)
@@ -683,11 +681,8 @@ static int sh_dmae_probe(struct platform_device *pdev)
const struct sh_dmae_pdata *pdata;
unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {};
int chan_irq[SH_DMAE_MAX_CHANNELS];
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
unsigned long irqflags = 0;
-   int errirq;
-#endif
-   int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
+   int err, errirq, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
struct sh_dmae_device *shdev;
struct dma_device *dma_dev;
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
@@ -789,33 +784,32 @@ static int sh_dmae_probe(struct platform_device *pdev)
if (err)
goto rst_err;
 
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
-   chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+   if (IS_ENABLED(CONFIG_CPU_SH4) || IS_ENABLED(CONFIG_ARCH_RENESAS)) {
+   chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 
-   if (!chanirq_res)
-   chanirq_res = errirq_res;
-   else
-   irqres++;
+   if (!chanirq_res)
+   chanirq_res = errirq_res;
+   else
+   irqres++;
 
-   if (chanirq_res == errirq_res ||
-   (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
-   irqflags = IRQF_SHARED;
+   if (chanirq_res == errirq_res ||
+   (errirq_res->flags & IORESOURCE_BITS) == 
IORESOURCE_IRQ_SHAREABLE)
+   irqflags = IRQF_SHARED;
 
-   errirq = errirq_res->start;
+   errirq = errirq_res->start;
 
-   err = devm_request_irq(>dev, errirq, sh_dmae_err, irqflags,
-  "DMAC Address Error", shdev);
-   if (err) {
-   dev_err(>dev,
-   "DMA failed requesting irq #%d, error %d\n",
-   errirq, err);
-   goto eirq_err;
+   err = devm_request_irq(>dev, errirq, sh_dmae_err,
+  irqflags, "DMAC Address Error", shdev);
+   if (err) {
+   dev_err(>dev,
+   "DMA failed requesting irq #%d, error %d\n",
+   errirq, err);
+   goto eirq_err;
+   }
+   } else {
+   chanirq_res = errirq_res;
}
 
-#else
-   chanirq_res = errirq_res;
-#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
-
if (chanirq_res->start == chanirq_res->end &&
!platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
/* Special case - all multiplexed */
@@ -881,9 +875,7 @@ static int sh_dmae_probe(struct platform_device *pdev)
 chan_probe_err:
sh_dmae_chan_remove(shdev);
 
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 eirq_err:
-#endif
 rst_err:
spin_lock_irq(_dmae_lock);
list_del_rcu(>node);
-- 
2.7.4

[PATCH 4/8] sh_eth: Change platform check to CONFIG_ARCH_RENESAS

[Geert Uytterhoeven]

Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
is CONFIG_ARCH_RENESAS a more appropriate platform check than the legacy
CONFIG_ARCH_SHMOBILE, hence use the former.

Renesas SuperH SH-Mobile SoCs are still covered by the CONFIG_CPU_SH4
check.

This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
future.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/net/ethernet/renesas/sh_eth.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/renesas/sh_eth.h 
b/drivers/net/ethernet/renesas/sh_eth.h
index a5b792ce2ae7d046..1bf930d4a1e52c18 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -163,7 +163,7 @@ enum {
 };
 
 /* Driver's parameters */
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS)
 #define SH_ETH_RX_ALIGN32
 #else
 #define SH_ETH_RX_ALIGN2
-- 
2.7.4

[PATCH 0/8] arm: renesas: Change platform dependency to ARCH_RENESAS

[Geert Uytterhoeven]

Hi all,

Commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
started the conversion from ARCH_SHMOBILE to ARCH_RENESAS for Renesas
ARM SoCs.  This patch series completes the conversion, by:
  1. Updating dependencies for drivers that weren't converted yet,
  2. Removing the ARCH_SHMOBILE Kconfig symbols on ARM and ARM64.

The first 6 patches can be applied independently by subsystem
maintainers.
The last two patches depend on the first 6 patches, and are thus marked
RFC.

Thanks for your comments!

Geert Uytterhoeven (8):
  arm: shmobile: Change platform dependency to ARCH_RENESAS
  dmaengine: shdmac: Change platform check to CONFIG_ARCH_RENESAS
  [media] v4l: rcar_fdp1: Change platform dependency to ARCH_RENESAS
  sh_eth: Change platform check to CONFIG_ARCH_RENESAS
  staging: emxx_udc: Change platform dependency to ARCH_RENESAS
  ASoC: sh: Update menu title and platform dependency
  [RFC] ARM: shmobile: Remove the ARCH_SHMOBILE Kconfig symbol
  [RFC] arm64: renesas: Remove the ARCH_SHMOBILE Kconfig symbol

 arch/arm/Kconfig  |  2 +-
 arch/arm/Makefile |  2 +-
 arch/arm/mach-shmobile/Kconfig|  4 ---
 arch/arm64/Kconfig.platforms  | 42 +
 drivers/dma/sh/shdmac.c   | 50 +++
 drivers/media/platform/Kconfig|  2 +-
 drivers/net/ethernet/renesas/sh_eth.h |  2 +-
 drivers/staging/emxx_udc/Kconfig  |  2 +-
 sound/soc/sh/Kconfig  |  4 +--
 9 files changed, 47 insertions(+), 63 deletions(-)

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 3/8] [media] v4l: rcar_fdp1: Change platform dependency to ARCH_RENESAS

[Geert Uytterhoeven]

The Renesas Fine Display Processor driver is used on Renesas R-Car SoCs
only.  Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce
ARCH_RENESAS") is ARCH_RENESAS a more appropriate platform dependency
than the legacy ARCH_SHMOBILE, hence use the former.

This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
future.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/media/platform/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index f9235e8f8e962d2e..7ad4725f9d1f9627 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -396,7 +396,7 @@ config VIDEO_SH_VEU
 config VIDEO_RENESAS_FDP1
tristate "Renesas Fine Display Processor"
depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
-   depends on ARCH_SHMOBILE || COMPILE_TEST
+   depends on ARCH_RENESAS || COMPILE_TEST
depends on (!ARCH_RENESAS && !VIDEO_RENESAS_FCP) || VIDEO_RENESAS_FCP
select VIDEOBUF2_DMA_CONTIG
select V4L2_MEM2MEM_DEV
-- 
2.7.4

[PATCH 6/8] ASoC: sh: Update menu title and platform dependency

[Geert Uytterhoeven]

Change the menu title to refer to "Renesas SoCs" instead of "SuperH", as
both SuperH and ARM SoCs are supported.

Since commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS")
is ARCH_RENESAS a more appropriate platform dependency for Renesas ARM
SoCs than the legacy ARCH_SHMOBILE, hence use the former.
Renesas SuperH SH-Mobile SoCs are still covered by the SUPERH
dependency.

This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
future.

Signed-off-by: Geert Uytterhoeven 
---
 sound/soc/sh/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
index 1aa5cd77ca24a06f..c1b7fb91e3063f2b 100644
--- a/sound/soc/sh/Kconfig
+++ b/sound/soc/sh/Kconfig
@@ -1,5 +1,5 @@
-menu "SoC Audio support for SuperH"
-   depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
+menu "SoC Audio support for Renesas SoCs"
+   depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
 
 config SND_SOC_PCM_SH7760
tristate "SoC Audio support for Renesas SH7760"
-- 
2.7.4

Re: [PATCH 0/2] ARM: shmobile: Disable CONFIG_FB_SH_MOBILE_MERAM

[Laurent Pinchart]

Hi Geert,

Thank you for the patches.

For the whole series,

Reviewed-by: Laurent Pinchart 

On Friday, 20 April 2018 16:15:39 EEST Geert Uytterhoeven wrote:
>   Hi Simon, Magnus,
> 
> The last Renesas ARM platform using this driver was removed in commit
> a521422ea4ae6128 ("ARM: shmobile: mackerel: Remove Legacy C board
> code"), hence CONFIG_FB_SH_MOBILE_MERAM can be disabled.
> 
> Thanks!
> 
> Geert Uytterhoeven (2):
>   ARM: shmobile: defconfig: Disable CONFIG_FB_SH_MOBILE_MERAM
>   ARM: multi_v7_defconfig: Disable CONFIG_FB_SH_MOBILE_MERAM
> 
>  arch/arm/configs/multi_v7_defconfig | 1 -
>  arch/arm/configs/shmobile_defconfig | 1 -
>  2 files changed, 2 deletions(-)


-- 
Regards,

Laurent Pinchart

[PATCH 1/2] ARM: shmobile: defconfig: Disable CONFIG_FB_SH_MOBILE_MERAM

[Geert Uytterhoeven]

The last Renesas ARM platform using this driver was removed in commit
a521422ea4ae6128 ("ARM: shmobile: mackerel: Remove Legacy C board
code").

Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/configs/shmobile_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/shmobile_defconfig 
b/arch/arm/configs/shmobile_defconfig
index 90a471ad975cdd62..b49887e86a3d82ea 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -158,7 +158,6 @@ CONFIG_DRM_DUMB_VGA_DAC=y
 CONFIG_DRM_I2C_ADV7511=y
 CONFIG_DRM_I2C_ADV7511_AUDIO=y
 CONFIG_FB_SH_MOBILE_LCDC=y
-CONFIG_FB_SH_MOBILE_MERAM=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 # CONFIG_BACKLIGHT_GENERIC is not set
 CONFIG_BACKLIGHT_PWM=y
-- 
2.7.4

[PATCH 2/2] ARM: multi_v7_defconfig: Disable CONFIG_FB_SH_MOBILE_MERAM

[Geert Uytterhoeven]

The last Renesas ARM platform using this driver was removed in commit
a521422ea4ae6128 ("ARM: shmobile: mackerel: Remove Legacy C board
code").

Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/configs/multi_v7_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index be1f043f4deea94b..aca866286498c09d 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -653,7 +653,6 @@ CONFIG_FB_EFI=y
 CONFIG_FB_WM8505=y
 CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FB_SIMPLE=y
-CONFIG_FB_SH_MOBILE_MERAM=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_LCD_PLATFORM=m
-- 
2.7.4

[PATCH 0/2] ARM: shmobile: Disable CONFIG_FB_SH_MOBILE_MERAM

[Geert Uytterhoeven]

Hi Simon, Magnus,

The last Renesas ARM platform using this driver was removed in commit
a521422ea4ae6128 ("ARM: shmobile: mackerel: Remove Legacy C board
code"), hence CONFIG_FB_SH_MOBILE_MERAM can be disabled.

Thanks!

Geert Uytterhoeven (2):
  ARM: shmobile: defconfig: Disable CONFIG_FB_SH_MOBILE_MERAM
  ARM: multi_v7_defconfig: Disable CONFIG_FB_SH_MOBILE_MERAM

 arch/arm/configs/multi_v7_defconfig | 1 -
 arch/arm/configs/shmobile_defconfig | 1 -
 2 files changed, 2 deletions(-)

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] watchdog: renesas-wdt: Remove R-Car M2-W ES2.x from blacklist

[Guenter Roeck]

On 04/20/2018 05:20 AM, Geert Uytterhoeven wrote:

System restart triggered by watchdog time-out works fine on a Koelsch
board with R-Car M2-W ES2.0.

Signed-off-by: Geert Uytterhoeven 


Reviewed-by: Guenter Roeck 


---
Thanks to Magnus and Shimoda-san for providing board access!
---
  drivers/watchdog/renesas_wdt.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 514db5cc15951125..88d81feba4e60087 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -146,7 +146,7 @@ static const struct soc_device_attribute 
rwdt_quirks_match[] = {
.data = (void *)1,  /* needs single CPU */
}, {
.soc_id = "r8a7791",
-   .revision = "ES[12].*",
+   .revision = "ES1.*",
.data = (void *)1,  /* needs single CPU */
}, {
.soc_id = "r8a7792",

RE: [PATCH] watchdog: renesas-wdt: Remove R-Car M2-W ES2.x from blacklist

[Fabrizio Castro]

> Subject: [PATCH] watchdog: renesas-wdt: Remove R-Car M2-W ES2.x from blacklist
>
> System restart triggered by watchdog time-out works fine on a Koelsch
> board with R-Car M2-W ES2.0.
>
> Signed-off-by: Geert Uytterhoeven 

Acked-by: Fabrizio Castro 

> ---
> Thanks to Magnus and Shimoda-san for providing board access!
> ---
>  drivers/watchdog/renesas_wdt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
> index 514db5cc15951125..88d81feba4e60087 100644
> --- a/drivers/watchdog/renesas_wdt.c
> +++ b/drivers/watchdog/renesas_wdt.c
> @@ -146,7 +146,7 @@ static const struct soc_device_attribute 
> rwdt_quirks_match[] = {
>  .data = (void *)1,/* needs single CPU */
>  }, {
>  .soc_id = "r8a7791",
> -.revision = "ES[12].*",
> +.revision = "ES1.*",
>  .data = (void *)1,/* needs single CPU */
>  }, {
>  .soc_id = "r8a7792",
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

[PATCH v2 2/2] arm64: dts: renesas: Add Renesas Ebisu board support

[Yoshihiro Shimoda]

From: Takeshi Kihara 

Basic support for the Renesas Ebisu board based on R-Car E3:
  - Memory,
  - Main crystal,
  - Serial console,

Signed-off-by: Takeshi Kihara 
[shimoda: rebase and add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm64/boot/dts/renesas/Makefile   |  1 +
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 37 ++
 2 files changed, 38 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile 
b/arch/arm64/boot/dts/renesas/Makefile
index 5ede060..a235961 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -10,4 +10,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
 dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
+dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
 dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
new file mode 100644
index 000..63ee134
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the ebisu board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77990.dtsi"
+
+/ {
+   model = "Renesas Ebisu board based on r8a77990";
+   compatible = "renesas,ebisu", "renesas,r8a77990";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x3800>;
+   };
+};
+
+_clk {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
-- 
1.9.1

[PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Yoshihiro Shimoda]

This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
  - PSCI
  - CPU (single)
  - Cache controller
  - Main clocks and controller
  - Interrupt controller
  - Timer
  - PMU
  - Reset controller
  - Product register
  - System controller
  - UART for console

Inspried by a patch by Takeshi Kihara in the BSP.

Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 127 ++
 1 file changed, 127 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
new file mode 100644
index 000..3a19b9e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the r8a77990 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a77990";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   /* 1 core only at this point */
+   a53_0: cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0>;
+   device_type = "cpu";
+   power-domains = < 5>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   L2_CA53: cache-controller@0 {
+   compatible = "cache";
+   reg = <0>;
+   power-domains = < 21>;
+   cache-unified;
+   cache-level = <2>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   pmu_a53 {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-affinity = <_0>;
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   soc: soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   cpg: clock-controller@e615 {
+   compatible = "renesas,r8a77990-cpg-mssr";
+   reg = <0 0xe615 0 0x1000>;
+   clocks = <_clk>;
+   clock-names = "extal";
+   #clock-cells = <2>;
+   #power-domain-cells = <0>;
+   #reset-cells = <1>;
+   };
+
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a77990-rst";
+   reg = <0 0xe616 0 0x0200>;
+   };
+
+   sysc: system-controller@e618 {
+   compatible = "renesas,r8a77990-sysc";
+   reg = <0 0xe618 0 0x0400>;
+   #power-domain-cells = <1>;
+   };
+
+   scif2: serial@e6e88000 {
+   compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e88000 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 310>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 310>;
+   status = "disabled";
+   };
+
+   gic: interrupt-controller@f101 {
+   compatible = "arm,gic-400";
+   #interrupt-cells = <3>;
+   #address-cells = <0>;
+   interrupt-controller;
+   reg = <0x0 0xf101 0 0x1000>,
+ <0x0 0xf102 0 0x2>,
+ <0x0 0xf104 0 0x2>,
+ <0x0 0xf106 0 0x2>;
+   interrupts = ;
+   clocks = < CPG_MOD 408>;
+   clock-names = "clk";
+   power-domains = < 32>;
+   resets = < 408>;
+   };
+
+   prr: chipid@fff00044 {
+   compatible = "renesas,prr";
+   reg = <0 0xfff00044 0 4>;
+   };
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) 
| 

[PATCH v2 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions

[Yoshihiro Shimoda]

From: Takeshi Kihara 

This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.

Note that internal CPG clocks (S0, S1, S2, S3, SDSRC) are not included,
as they are used as internal clock sources only, and never referenced
from DT.

Signed-off-by: Takeshi Kihara 
[shimoda: add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda 
---
 include/dt-bindings/clock/r8a77990-cpg-mssr.h | 62 +++
 1 file changed, 62 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h 
b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 000..2418e39
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+
+#include 
+
+/* r8a77990 CPG Core Clocks */
+#define R8A77990_CLK_Z20
+#define R8A77990_CLK_ZR1
+#define R8A77990_CLK_ZG2
+#define R8A77990_CLK_ZTR   3
+#define R8A77990_CLK_ZT4
+#define R8A77990_CLK_ZX5
+#define R8A77990_CLK_S0D1  6
+#define R8A77990_CLK_S0D3  7
+#define R8A77990_CLK_S0D6  8
+#define R8A77990_CLK_S0D12 9
+#define R8A77990_CLK_S0D24 10
+#define R8A77990_CLK_S1D1  11
+#define R8A77990_CLK_S1D2  12
+#define R8A77990_CLK_S1D4  13
+#define R8A77990_CLK_S2D1  14
+#define R8A77990_CLK_S2D2  15
+#define R8A77990_CLK_S2D4  16
+#define R8A77990_CLK_S3D1  17
+#define R8A77990_CLK_S3D2  18
+#define R8A77990_CLK_S3D4  19
+#define R8A77990_CLK_S0D6C 20
+#define R8A77990_CLK_S3D1C 21
+#define R8A77990_CLK_S3D2C 22
+#define R8A77990_CLK_S3D4C 23
+#define R8A77990_CLK_LB24
+#define R8A77990_CLK_CL25
+#define R8A77990_CLK_ZB3   26
+#define R8A77990_CLK_ZB3D2 27
+#define R8A77990_CLK_CR28
+#define R8A77990_CLK_CRD2  29
+#define R8A77990_CLK_SD0H  30
+#define R8A77990_CLK_SD0   31
+#define R8A77990_CLK_SD1H  32
+#define R8A77990_CLK_SD1   33
+#define R8A77990_CLK_SD3H  34
+#define R8A77990_CLK_SD3   35
+#define R8A77990_CLK_RPC   36
+#define R8A77990_CLK_RPCD2 37
+#define R8A77990_CLK_ZA2   38
+#define R8A77990_CLK_ZA8   39
+#define R8A77990_CLK_Z2D   40
+#define R8A77990_CLK_CANFD 41
+#define R8A77990_CLK_MSO   42
+#define R8A77990_CLK_R 43
+#define R8A77990_CLK_OSC   44
+#define R8A77990_CLK_LV0   45
+#define R8A77990_CLK_LV1   46
+#define R8A77990_CLK_CSI0  47
+#define R8A77990_CLK_CP49
+#define R8A77990_CLK_CPEX  50
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
-- 
1.9.1

[PATCH v2 0/2] clk: renesas: Add support for R-Car E3

[Yoshihiro Shimoda]

This patch is based on the renesas-devel-20180418-v4.17-rc1 tag of
renesas.git.

Changes from v1:
 - Remove POST3's definition in patch 1.
  Discussed on https://patchwork.kernel.org/patch/10335231/

 - Fix typo and some errors in patch 2.
 - Add Geert-san's Reviewed-by in patch 2.
  Discussed on https://patchwork.kernel.org/patch/10335235/

Takeshi Kihara (1):
  clk: renesas: Add r8a77990 CPG Core Clock Definitions

Yoshihiro Shimoda (1):
  clk: renesas: cpg-mssr: Add support for R-Car E3

 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   3 +-
 drivers/clk/renesas/Kconfig|   5 +
 drivers/clk/renesas/Makefile   |   1 +
 drivers/clk/renesas/r8a77990-cpg-mssr.c| 289 +
 drivers/clk/renesas/renesas-cpg-mssr.c |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h |   1 +
 include/dt-bindings/clock/r8a77990-cpg-mssr.h  |  62 +
 7 files changed, 366 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c
 create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h

-- 
1.9.1

[PATCH v2 0/2] arm64: dts: renesas: Add support for R-Car E3 and Ebisu board

[Yoshihiro Shimoda]

This patch is based on the renesas-devel-20180418-v4.17-rc1 tag of
renesas.git.
This code doesn't use dt-bindings definitions to avoid dependency.

Changes from v1:
 - Change some nodes places in patch 1.
   Discussed on https://patchwork.kernel.org/patch/10335237/


Takeshi Kihara (1):
  arm64: dts: renesas: Add Renesas Ebisu board support

Yoshihiro Shimoda (1):
  arm64: dts: renesas: Add Renesas R8A77990 SoC support

 arch/arm64/boot/dts/renesas/Makefile   |   1 +
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts |  37 +++
 arch/arm64/boot/dts/renesas/r8a77990.dtsi  | 127 +
 3 files changed, 165 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi

-- 
1.9.1

[PATCH v2 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3

[Yoshihiro Shimoda]

Initial support for R-Car E3 (r8a77990), including core and module
clocks.

Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual:
Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018".

Inspried by patches by Takeshi Kihara in the BSP.

Signed-off-by: Yoshihiro Shimoda 
---
 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   3 +-
 drivers/clk/renesas/Kconfig|   5 +
 drivers/clk/renesas/Makefile   |   1 +
 drivers/clk/renesas/r8a77990-cpg-mssr.c| 289 +
 drivers/clk/renesas/renesas-cpg-mssr.c |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h |   1 +
 6 files changed, 304 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt 
b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index c3473df..db542ab 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -26,6 +26,7 @@ Required Properties:
   - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
   - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
   - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
+  - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
   - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
 
   - reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -36,7 +37,7 @@ Required Properties:
   - clock-names: List of external parent clock names. Valid names are:
   - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
-r8a77980, r8a77995)
+r8a77980, r8a77990, r8a77995)
   - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
   - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
 r8a7794)
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f32896fa..f9ba71311 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -19,6 +19,7 @@ config CLK_RENESAS
select CLK_R8A77965 if ARCH_R8A77965
select CLK_R8A77970 if ARCH_R8A77970
select CLK_R8A77980 if ARCH_R8A77980
+   select CLK_R8A77990 if ARCH_R8A77990
select CLK_R8A77995 if ARCH_R8A77995
select CLK_SH73A0 if ARCH_SH73A0
 
@@ -116,6 +117,10 @@ config CLK_R8A77980
bool "R-Car V3H clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
 
+config CLK_R8A77990
+   bool "R-Car E3 clock support" if COMPILE_TEST
+   select CLK_RCAR_GEN3_CPG
+
 config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index a4edea9..fe5bac9 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_SH73A0)   += clk-sh73a0.o
 
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c 
b/drivers/clk/renesas/r8a77990-cpg-mssr.c
new file mode 100644
index 000..bf439e2
--- /dev/null
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -0,0 +1,289 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL0,
+   CLK_PLL1,
+   CLK_PLL3,
+   CLK_PLL0D4,
+   CLK_PLL0D6,
+   CLK_PLL0D8,
+   CLK_PLL0D20,
+   CLK_PLL0D24,
+   CLK_PLL1D2,
+   CLK_PE,
+   CLK_S0,
+   CLK_S1,
+   CLK_S2,
+   CLK_S3,
+   CLK_SDSRC,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal", CLK_EXTAL),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main",  CLK_MAIN, 

[PATCH] watchdog: renesas-wdt: Remove R-Car M2-W ES2.x from blacklist

[Geert Uytterhoeven]

System restart triggered by watchdog time-out works fine on a Koelsch
board with R-Car M2-W ES2.0.

Signed-off-by: Geert Uytterhoeven 
---
Thanks to Magnus and Shimoda-san for providing board access!
---
 drivers/watchdog/renesas_wdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 514db5cc15951125..88d81feba4e60087 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -146,7 +146,7 @@ static const struct soc_device_attribute 
rwdt_quirks_match[] = {
.data = (void *)1,  /* needs single CPU */
}, {
.soc_id = "r8a7791",
-   .revision = "ES[12].*",
+   .revision = "ES1.*",
.data = (void *)1,  /* needs single CPU */
}, {
.soc_id = "r8a7792",
-- 
2.7.4

[PATCH v6 2/3] ARM: dts: r8a7791: Convert to new LVDS DT bindings

[Laurent Pinchart]

The internal LVDS encoder now has DT bindings separate from the DU. Port
the device tree over to the new model.

Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
Fixes: bb21803ea440 ("ARM: dts: r8a7791: add soc node")
Signed-off-by: Laurent Pinchart 
Reviewed-by: Niklas Söderlund 
---
Changes since v5:

- Removed LVDS clock from DU node in Koelsch DT

Changes since v3:

- Added power-domains and resets properties to LVDS nodes

Changes since v2:

- Fixed LVDS compatible string

Changes since v1:

- Remove the DU reg-names property
---
 arch/arm/boot/dts/r8a7791-koelsch.dts | 12 +---
 arch/arm/boot/dts/r8a7791-porter.dts  | 16 +---
 arch/arm/boot/dts/r8a7791.dtsi| 36 +--
 3 files changed, 52 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts 
b/arch/arm/boot/dts/r8a7791-koelsch.dts
index f40321a1c917..9d7213a0b8b8 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -468,10 +468,9 @@
pinctrl-names = "default";
status = "okay";
 
-   clocks = < CPG_MOD 724>, < CPG_MOD 723>, < CPG_MOD 726>,
+   clocks = < CPG_MOD 724>, < CPG_MOD 723>,
 <_clk>, <_clk>;
-   clock-names = "du.0", "du.1", "lvds.0",
- "dclkin.0", "dclkin.1";
+   clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 
ports {
port@0 {
@@ -479,6 +478,13 @@
remote-endpoint = <_in>;
};
};
+   };
+};
+
+ {
+   status = "okay";
+
+   ports {
port@1 {
lvds_connector: endpoint {
};
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts 
b/arch/arm/boot/dts/r8a7791-porter.dts
index c14e6fe9e4f6..ae9ed9ff53ef 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -441,10 +441,9 @@
pinctrl-names = "default";
status = "okay";
 
-   clocks = < CPG_MOD 724>, < CPG_MOD 723>, < CPG_MOD 726>,
+   clocks = < CPG_MOD 724>, < CPG_MOD 723>,
 <_clk>, <_clk>;
-   clock-names = "du.0", "du.1", "lvds.0",
- "dclkin.0", "dclkin.1";
+   clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 
ports {
port@0 {
@@ -455,6 +454,17 @@
};
 };
 
+ {
+   status = "okay";
+
+   ports {
+   port@1 {
+   lvds_connector: endpoint {
+   };
+   };
+   };
+};
+
 _sound {
pinctrl-0 = <_pins _clk_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index f11dab71b03a..506b20885413 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1633,15 +1633,12 @@
 
du: display@feb0 {
compatible = "renesas,du-r8a7791";
-   reg = <0 0xfeb0 0 0x4>,
- <0 0xfeb9 0 0x1c>;
-   reg-names = "du", "lvds.0";
+   reg = <0 0xfeb0 0 0x4>;
interrupts = ,
 ;
clocks = < CPG_MOD 724>,
-< CPG_MOD 723>,
-< CPG_MOD 726>;
-   clock-names = "du.0", "du.1", "lvds.0";
+< CPG_MOD 723>;
+   clock-names = "du.0", "du.1";
status = "disabled";
 
ports {
@@ -1656,6 +1653,33 @@
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+   };
+
+   lvds0: lvds@feb9 {
+   compatible = "renesas,r8a7791-lvds";
+   reg = <0 0xfeb9 0 0x1c>;
+   clocks = < CPG_MOD 726>;
+   power-domains = < R8A7791_PD_ALWAYS_ON>;
+   resets = < 726>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   lvds0_in: endpoint {
+   remote-endpoint = 
<_out_lvds0>;
+   };
+   };
+   

[PATCH v6 1/3] ARM: dts: r8a7790: Convert to new LVDS DT bindings

[Laurent Pinchart]

The internal LVDS encoder now has DT bindings separate from the DU. Port
the device tree over to the new model.

Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
Fixes: 4bdb7aa7dcd0 ("ARM: dts: r8a7790: add soc node")
Signed-off-by: Laurent Pinchart 
Reviewed-by: Niklas Söderlund 
---
Changes since v3:

- Added power-domains and resets properties to LVDS nodes

Changes since v2:

- Fixed LVDS compatible string

Changes since v1:

- Remove the DU reg-names property
---
 arch/arm/boot/dts/r8a7790-lager.dts | 22 ++---
 arch/arm/boot/dts/r8a7790.dtsi  | 65 -
 2 files changed, 74 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts 
b/arch/arm/boot/dts/r8a7790-lager.dts
index ff516cda26c6..53b89e96b60c 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -379,7 +379,7 @@
port@0 {
reg = <0>;
adv7511_in: endpoint {
-   remote-endpoint = 
<_out_lvds0>;
+   remote-endpoint = <_out>;
};
};
 
@@ -467,10 +467,8 @@
status = "okay";
 
clocks = < CPG_MOD 724>, < CPG_MOD 723>, < CPG_MOD 722>,
-< CPG_MOD 726>, < CPG_MOD 725>,
 <_clk>, <_clk>;
-   clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
- "dclkin.0", "dclkin.1";
+   clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
 
ports {
port@0 {
@@ -478,12 +476,26 @@
remote-endpoint = <_in>;
};
};
+   };
+};
+
+ {
+   status = "okay";
+
+   ports {
port@1 {
endpoint {
remote-endpoint = <_in>;
};
};
-   port@2 {
+   };
+};
+
+ {
+   status = "okay";
+
+   ports {
+   port@1 {
lvds_connector: endpoint {
};
};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e4367cecad18..05a0fc23ac88 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1627,18 +1627,13 @@
 
du: display@feb0 {
compatible = "renesas,du-r8a7790";
-   reg = <0 0xfeb0 0 0x7>,
- <0 0xfeb9 0 0x1c>,
- <0 0xfeb94000 0 0x1c>;
-   reg-names = "du", "lvds.0", "lvds.1";
+   reg = <0 0xfeb0 0 0x7>;
interrupts = ,
 ,
 ;
clocks = < CPG_MOD 724>, < CPG_MOD 723>,
-< CPG_MOD 722>, < CPG_MOD 726>,
-< CPG_MOD 725>;
-   clock-names = "du.0", "du.1", "du.2", "lvds.0",
- "lvds.1";
+< CPG_MOD 722>;
+   clock-names = "du.0", "du.1", "du.2";
status = "disabled";
 
ports {
@@ -1653,11 +1648,65 @@
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
+   remote-endpoint = <_in>;
};
};
port@2 {
reg = <2>;
du_out_lvds1: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+   };
+
+   lvds0: lvds@feb9 {
+   compatible = "renesas,r8a7790-lvds";
+   reg = <0 0xfeb9 0 0x1c>;
+   clocks = < CPG_MOD 726>;
+   power-domains = < R8A7790_PD_ALWAYS_ON>;
+   resets = < 726>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   lvds0_in: endpoint {
+   remote-endpoint = 
<_out_lvds0>;

[PATCH v6 0/3] R-Car DU: Fix LVDS output on Gen2 boards

[Laurent Pinchart]

Hello,

This patch series fixes LVDS output support on the Lager, Koelsh, Porter and
Gose boards that broke in v4.17-rc1 due to the combination of the R-Car DU
LVDS driver rework and the DT move of all on-SoC peripherals to a /soc node.

We could handle the problem in the R-Car DU LVDS DT backward compatibility
code, but that fix would only be used for v4.17 as in v4.18 the Gen2 DT will
move to the new LVDS DT bindings. I thus propose merging these three patches
in v4.17 already to fix the problem as this is the simplest solution.

The patches are based on top of v4.17-rc1. Simon, could you please queue them
up as fixes for v4.17 ?

Laurent Pinchart (3):
  ARM: dts: r8a7790: Convert to new LVDS DT bindings
  ARM: dts: r8a7791: Convert to new LVDS DT bindings
  ARM: dts: r8a7793: Convert to new LVDS DT bindings

 arch/arm/boot/dts/r8a7790-lager.dts   | 22 +---
 arch/arm/boot/dts/r8a7790.dtsi| 65 ++-
 arch/arm/boot/dts/r8a7791-koelsch.dts | 12 +--
 arch/arm/boot/dts/r8a7791-porter.dts  | 16 +++--
 arch/arm/boot/dts/r8a7791.dtsi| 36 +++
 arch/arm/boot/dts/r8a7793-gose.dts| 10 --
 arch/arm/boot/dts/r8a7793.dtsi| 37 
 7 files changed, 164 insertions(+), 34 deletions(-)

-- 
Regards,

Laurent Pinchart

[PATCH v6 3/3] ARM: dts: r8a7793: Convert to new LVDS DT bindings

[Laurent Pinchart]

The internal LVDS encoder now has DT bindings separate from the DU. Port
the device tree over to the new model.

Fixes: c6a27fa41fab ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
Fixes: bff8f8c2feb7 ("ARM: dts: r8a7793: add soc node")
Signed-off-by: Laurent Pinchart 
Reviewed-by: Niklas Söderlund 
---
Changes since v3:

- Added power-domains and resets properties to LVDS nodes

Changes since v2:

- Fixed LVDS compatible string

Changes since v1:

- Remove the DU reg-names property
---
 arch/arm/boot/dts/r8a7793-gose.dts | 10 +++---
 arch/arm/boot/dts/r8a7793.dtsi | 37 +++--
 2 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7793-gose.dts 
b/arch/arm/boot/dts/r8a7793-gose.dts
index 9ed6961f2d9a..96e117d8b2cc 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -447,10 +447,9 @@
pinctrl-names = "default";
status = "okay";
 
-   clocks = < CPG_MOD 724>, < CPG_MOD 723>, < CPG_MOD 726>,
+   clocks = < CPG_MOD 724>, < CPG_MOD 723>,
 <_clk>, <_clk>;
-   clock-names = "du.0", "du.1", "lvds.0",
- "dclkin.0", "dclkin.1";
+   clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 
ports {
port@0 {
@@ -458,6 +457,11 @@
remote-endpoint = <_in>;
};
};
+   };
+};
+
+ {
+   ports {
port@1 {
lvds_connector: endpoint {
};
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index f9c5a557107d..4f526030dc7c 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1292,15 +1292,12 @@
 
du: display@feb0 {
compatible = "renesas,du-r8a7793";
-   reg = <0 0xfeb0 0 0x4>,
- <0 0xfeb9 0 0x1c>;
-   reg-names = "du", "lvds.0";
+   reg = <0 0xfeb0 0 0x4>;
interrupts = ,
 ;
clocks = < CPG_MOD 724>,
-< CPG_MOD 723>,
-< CPG_MOD 726>;
-   clock-names = "du.0", "du.1", "lvds.0";
+< CPG_MOD 723>;
+   clock-names = "du.0", "du.1";
status = "disabled";
 
ports {
@@ -1315,6 +1312,34 @@
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+   };
+
+   lvds0: lvds@feb9 {
+   compatible = "renesas,r8a7793-lvds";
+   reg = <0 0xfeb9 0 0x1c>;
+   clocks = < CPG_MOD 726>;
+   power-domains = < R8A7793_PD_ALWAYS_ON>;
+   resets = < 726>;
+
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   lvds0_in: endpoint {
+   remote-endpoint = 
<_out_lvds0>;
+   };
+   };
+   port@1 {
+   reg = <1>;
+   lvds0_out: endpoint {
};
};
};
-- 
Regards,

Laurent Pinchart

Re: [PATCH] arm64: dts: renesas: v3msk: add EtherAVB pins

[Sergei Shtylyov]

On 03/14/2018 11:30 PM, Sergei Shtylyov wrote:

> Add the (previously omitted) EtherAVB pin data to the V3M Starter Kit
> board's device tree.
> 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> The patch is against the 'renesas-devel-20180314-v4.16-rc5' tag of Simon's
> 'renesas.git repo. It depends on the R8A77970 PFC driver patch adding EtherAVB
> pin groups (posted yesterday) in order to work properly...

   The dependency has been now met, please merge this patch.

MBR, Sergei

Re: [PATCH v2] arm64: dts: renesas: eagle: add EtherAVB pins

[Sergei Shtylyov]

Hello!

On 03/14/2018 10:58 PM, Sergei Shtylyov wrote:

> Add the (previously omitted) EtherAVB pin data to the Eagle board's
> device tree.
> 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> The patch is against the 'renesas-devel-20180314-v4.16-rc5' tag of Simon's
> 'renesas.git repo. It depends on the R8A77970 PFC driver patch adding EtherAVB
> pin groups (posted yesterday) in order to work properly...

   The dependency has been now met, please merge this patch.

MBR, Sergei

RE: [PATCH 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Yoshihiro Shimoda]

Hi Simon-san,

> From: Simon Horman, Sent: Friday, April 20, 2018 6:55 PM
> 
> Hi Shimoda-san,
> 
> On Wed, Apr 11, 2018 at 06:37:41PM +0900, Yoshihiro Shimoda wrote:
> > This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
> >   - PSCI
> >   - CPU (single)
> >   - Cache controller
> >   - Main clocks and controller
> >   - Interrupt controller
> >   - Timer
> >   - PMU
> >   - Reset controller
> >   - Product register
> >   - System controller
> >   - UART for console
> >
> > Inspried by a patch by Takeshi Kihara in the BSP.
> >
> > Signed-off-by: Yoshihiro Shimoda 
> 
> Thanks for your patch. I'd like to request a few minor updates
> as per my comments below.

Thank you for the review!

> > ---
> >  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 131 
> > ++
> >  1 file changed, 131 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
> > b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > new file mode 100644
> > index 000..310bfd9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > @@ -0,0 +1,131 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Device Tree Source for the r8a77990 SoC
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "renesas,r8a77990";
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   /* 1 core only at this point */
> > +   a53_0: cpu@0 {
> > +   compatible = "arm,cortex-a53", "arm,armv8";
> > +   reg = <0x0>;
> > +   device_type = "cpu";
> > +   power-domains = < 5>;
> > +   next-level-cache = <_CA53>;
> > +   enable-method = "psci";
> > +   };
> > +
> > +   L2_CA53: cache-controller@0 {
> > +   compatible = "cache";
> > +   reg = <0>;
> > +   power-domains = < 21>;
> > +   cache-unified;
> > +   cache-level = <2>;
> > +   };
> > +   };
> > +
> > +   extal_clk: extal {
> > +   compatible = "fixed-clock";
> > +   #clock-cells = <0>;
> > +   /* This value must be overridden by the board */
> > +   clock-frequency = <0>;
> > +   };
> > +
> > +   psci {
> > +   compatible = "arm,psci-0.2";
> > +   method = "smc";
> > +   };
> > +
> > +   soc: soc {
> > +   compatible = "simple-bus";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   ranges;
> > +
> > +   gic: interrupt-controller@f101 {
> > +   compatible = "arm,gic-400";
> > +   #interrupt-cells = <3>;
> > +   #address-cells = <0>;
> > +   interrupt-controller;
> > +   reg = <0x0 0xf101 0 0x1000>,
> > + <0x0 0xf102 0 0x2>,
> > + <0x0 0xf104 0 0x2>,
> > + <0x0 0xf106 0 0x2>;
> > +   interrupts =  > +   (GIC_CPU_MASK_SIMPLE(1) | 
> > IRQ_TYPE_LEVEL_HIGH)>;
> > +   clocks = < CPG_MOD 408>;
> > +   clock-names = "clk";
> > +   power-domains = < 32>;
> > +   resets = < 408>;
> > +   };
> 
> Please sort sub-nodes of the soc node by:
> 1. Primary key: base address
> 2. Secondary key: IP block
> 
> You can use arch/arm64/boot/dts/renesas/r8a7795.dtsi as a guide.

Oops, I assumed that all nodes are sorted by alphabet order...
I'll fix this in v2.

> > +
> > +   timer {
> > +   compatible = "arm,armv8-timer";
> > +   interrupts =  > +   (GIC_CPU_MASK_SIMPLE(1) | 
> > IRQ_TYPE_LEVEL_LOW)>,
> > + > +   (GIC_CPU_MASK_SIMPLE(1) | 
> > IRQ_TYPE_LEVEL_LOW)>,
> > + > +   (GIC_CPU_MASK_SIMPLE(1) | 
> > IRQ_TYPE_LEVEL_LOW)>,
> > + > +   (GIC_CPU_MASK_SIMPLE(1) | 
> > IRQ_TYPE_LEVEL_LOW)>;
> > +   };
> > +
> > +   pmu_a53 {
> > +   compatible = "arm,cortex-a53-pmu";
> > +   interrupts = ;
> > +   interrupt-affinity = <_0>;
> > +   };
> 
> The timer and pmu_a53 nodes do not have a base address and are thus
> not on the bus. Please move them outside of the SoC node.

I got it. I will fix it in v2.

Best regards,
Yoshihiro Shimoda

Re: [PATCH] soc: renesas: r8a77995-sysc: Cleanups

[Simon Horman]

On Wed, Apr 18, 2018 at 04:58:18PM +0200, Geert Uytterhoeven wrote:
> Minor cleanup of artefacts caused by deriving from r8a7795-sysc.c:
>   - Remove unused inclusion of ,
>   - Make r8a77995_areas[] const.
> 
> Signed-off-by: Geert Uytterhoeven 

Thanks, applied.

Re: [PATCH 2/2] arm64: dts: renesas: condor: add eMMC support

[Simon Horman]

On Sat, Apr 14, 2018 at 10:28:29PM +0300, Sergei Shtylyov wrote:
> Define the Condor board dependent part of the MMC0 (connected to eMMC chip)
> device node along with the necessary voltage regulators...
> 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
>  arch/arm64/boot/dts/renesas/r8a77980-condor.dts |   43 
> 
>  1 file changed, 43 insertions(+)
> 
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -27,6 +27,24 @@
>   /* first 128MB is reserved for secure area. */
>   reg = <0 0x4800 0 0x7800>;
>   };
> +
> + d3_3v: regulator-0 {

Please use reg_3p3v: regulator1 for consistency with salvator-common.dtsi

> + compatible = "regulator-fixed";
> + regulator-name = "D3.3V";

And "fixed-3.3V"

> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vddq_vin01: regulator-1 {

And reg_1p8v: regulator0 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDDQ_VIN01";

And "fixed-1.8V"

> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
>  };
>  
>   {
> @@ -52,6 +70,19 @@
>   clock-frequency = <32768>;
>  };
>  
> + {
> + pinctrl-0 = <_3_3v_pins>;
> + pinctrl-1 = <_1_8v_pins>;
> + pinctrl-names = "default", "state_uhs";
> +
> + vmmc-supply = <_3v>;
> + vqmmc-supply = <_vin01>;
> + mmc-hs200-1_8v;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
>   {
>   status = "okay";
>  };
> @@ -70,6 +101,18 @@
>   function = "avb";
>   };
>  
> + mmc_1_8v_pins: mmc_1_8v {
> + groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> + function = "mmc";
> + power-source = <1800>;
> + };
> +
> + mmc_3_3v_pins: mmc_3_3v {
> + groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> + function = "mmc";
> + power-source = <3300>;
> + };

Again please make this more consistent with salvator-common.dtsi.

> +
>   scif0_pins: scif0 {
>   groups = "scif0_data";
>   function = "scif0";
> 

Re: [PATCH] sh: mm: Fix unprotected access to struct device

[Geert Uytterhoeven]

Hi Christoph,

On Fri, Apr 20, 2018 at 10:31 AM, Christoph Hellwig  wrote:
> On Wed, Apr 18, 2018 at 03:13:14PM +0200, jacopo mondi wrote:
>> As long as it goes for arch/sh, the only user of dma_alloc_coherent()
>> is platform_resource_setup_memory(), and it has been fixed by this
>> patch.
>
> Great!
>
>> Unfortunately, as Thomas pointed out, there are drivers which calls
>> into this with the wrong 'struct device' as the sh_eth one he had fixed.
>
> Yes, we'll need fixes there.  Other DMA ops implementations also look
> at struct device, so they generally are buggy.
>
>> I would then say that as long as it goes for the NULL case, we should be
>> fine now.
>
> Then I'd say skil that part, please.

The major reason for keeping the NULL WARN_ON() checks is to make it
obvious to the developer what is wrong, and fall back to the old behavior.

Without the checks, the kernel will just crash during early startup,
without a clue in the (missing) kernel output, usually leading to a
frustrating bisection experience (if the developer is sufficiently motivated,
at all).

Hence my vote for keeping the checks.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add MMC support

[Simon Horman]

On Sat, Apr 14, 2018 at 10:27:04PM +0300, Sergei Shtylyov wrote:
> Define the generic R8A77980 part of the MMC0 (SDHI2) device node.
> 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
>  arch/arm64/boot/dts/renesas/r8a77980.dtsi |   12 
>  1 file changed, 12 insertions(+)
> 
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -371,6 +371,18 @@
>   dma-channels = <16>;
>   };
>  
> + mmc0: mmc@ee14 {

Please use sdhi2: sd@ee14 for consistency with other SoCs
(I refereed to the r8a7795).

> + compatible = "renesas,sdhi-r8a77980",
> +  "renesas,rcar-gen3-sdhi";
> + reg = <0 0xee14 0 0x2000>;
> + interrupts = ;
> + clocks = < CPG_MOD 314>;
> + power-domains = < 32>;
> + resets = < 314>;
> + max-frequency = <2>;
> + status = "disabled";
> + };
> +
>   gic: interrupt-controller@f101 {
>   compatible = "arm,gic-400";
>   #interrupt-cells = <3>;
> 

Re: [PATCH 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Simon Horman]

Hi Shimoda-san,

On Wed, Apr 11, 2018 at 06:37:41PM +0900, Yoshihiro Shimoda wrote:
> This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
>   - PSCI
>   - CPU (single)
>   - Cache controller
>   - Main clocks and controller
>   - Interrupt controller
>   - Timer
>   - PMU
>   - Reset controller
>   - Product register
>   - System controller
>   - UART for console
> 
> Inspried by a patch by Takeshi Kihara in the BSP.
> 
> Signed-off-by: Yoshihiro Shimoda 

Thanks for your patch. I'd like to request a few minor updates
as per my comments below.

> ---
>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 131 
> ++
>  1 file changed, 131 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
> b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> new file mode 100644
> index 000..310bfd9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -0,0 +1,131 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Device Tree Source for the r8a77990 SoC
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include 
> +#include 
> +
> +/ {
> + compatible = "renesas,r8a77990";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 1 core only at this point */
> + a53_0: cpu@0 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0>;
> + device_type = "cpu";
> + power-domains = < 5>;
> + next-level-cache = <_CA53>;
> + enable-method = "psci";
> + };
> +
> + L2_CA53: cache-controller@0 {
> + compatible = "cache";
> + reg = <0>;
> + power-domains = < 21>;
> + cache-unified;
> + cache-level = <2>;
> + };
> + };
> +
> + extal_clk: extal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + interrupt-parent = <>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic: interrupt-controller@f101 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x0 0xf101 0 0x1000>,
> +   <0x0 0xf102 0 0x2>,
> +   <0x0 0xf104 0 0x2>,
> +   <0x0 0xf106 0 0x2>;
> + interrupts =  + (GIC_CPU_MASK_SIMPLE(1) | 
> IRQ_TYPE_LEVEL_HIGH)>;
> + clocks = < CPG_MOD 408>;
> + clock-names = "clk";
> + power-domains = < 32>;
> + resets = < 408>;
> + };

Please sort sub-nodes of the soc node by:
1. Primary key: base address
2. Secondary key: IP block

You can use arch/arm64/boot/dts/renesas/r8a7795.dtsi as a guide.

> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts =  + (GIC_CPU_MASK_SIMPLE(1) | 
> IRQ_TYPE_LEVEL_LOW)>,
> +   + (GIC_CPU_MASK_SIMPLE(1) | 
> IRQ_TYPE_LEVEL_LOW)>,
> +   + (GIC_CPU_MASK_SIMPLE(1) | 
> IRQ_TYPE_LEVEL_LOW)>,
> +   + (GIC_CPU_MASK_SIMPLE(1) | 
> IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu_a53 {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = ;
> + interrupt-affinity = <_0>;
> + };

The timer and pmu_a53 nodes do not have a base address and are thus
not on the bus. Please move them outside of the SoC node.

> +
> + cpg: clock-controller@e615 {
> + compatible = "renesas,r8a77990-cpg-mssr";
> + reg = <0 0xe615 0 0x1000>;
> + clocks = <_clk>;
> + clock-names = "extal";
> + #clock-cells = <2>;
> + #power-domain-cells = <0>;
> + #reset-cells = <1>;
> + };
> +
> +   

Re: [PATCH v3 5/5] arm64: dts: renesas: eagle: Enable HDMI output

[Simon Horman]

On Thu, Apr 12, 2018 at 10:14:01AM +0200, Jacopo Mondi wrote:
> Enable HDMI output on Renesas R-Car V3M Eagle board.
> 
> The HDMI ouput is enabled connecting the DU LVDS output to the

s/ouput/output/

> transparent LVDS converter THC63LVD1024, and successively routing its
> RGB output to the ADV7511W HDMI encoder.
> 
> Signed-off-by: Niklas Söderlund 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Laurent Pinchart 
> [for THC63LVD1024: ]
> Reviewed-by: Andrzej Hajda 

Thanks, applied.

Re: [PATCH v3 4/5] arm64: dts: renesas: r8a77970: add LVDS support

[Simon Horman]

On Thu, Apr 12, 2018 at 10:14:00AM +0200, Jacopo Mondi wrote:
> From: Sergei Shtylyov 
> 
> Define the generic R8A77970 part of the LVDS device node.
> 
> Signed-off-by: Sergei Shtylyov 

Thanks, applied.

Re: [PATCH v3 3/5] arm64: dts: renesas: r8a77970: add DU support

[Simon Horman]

On Thu, Apr 12, 2018 at 10:13:59AM +0200, Jacopo Mondi wrote:
> From: Sergei Shtylyov 
> 
> Define the generic R8A77970 part of the DU device node.
> 
> Based on the original (and large) patch by Daisuke Matsushita
> .
> 
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 
> Reviewed-by: Laurent Pinchart 

Thanks, applied.

Re: [PATCH v3 2/5] arm64: dts: renesas: r8a77970: add VSPD support

[Simon Horman]

On Thu, Apr 12, 2018 at 10:13:58AM +0200, Jacopo Mondi wrote:
> From: Sergei Shtylyov 
> 
> Describe VSPD0 in the R8A77970 device tree; it will be used by DU in
> the next patch...
> 
> Based on the original (and large) patch by Daisuke Matsushita
> .
> 
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 
> Signed-off-by: Niklas Söderlund 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Laurent Pinchart 

Thanks, applied.

Re: [PATCH v9 0/2] drm: Add Thine THC63LVD1024 LVDS decoder bridge

[Andrzej Hajda]

On 18.04.2018 16:40, Jacopo Mondi wrote:
> As I have another series which is based on this one + Eagle board display
> support, I'm re-sending this one to fix the small issue I pointed out in my
> reply to v8.
>
> Simon: no changes to Eagle DTS series, so the last one sent is still the good
> one.
>
> DRM: I have collected several reviewed-by tags both on driver and bindings.
> Can I send out incremental patches on this series and consider this one to
> be ready to be collected?

Queued to drm-misc-next.

Regards
Andrzej


>
> Thanks
>j
>
> v8 -> v9:
> - Put 'remote' OF node after usage not just in error path during device
>   tree parsing routine
> - Add Rob's Reviewed-by tag to the device tree bindings documentation
>
> v7 -> b8:
> - Make 'vcc' supply mandatory
> - Use 'oe' property name to describe "OE" pin
> - Minor fixes as suggested by Laurent on bindings and driver
>
> v6 -> v7:
> - Use semi-standard names for powerdown and output enable GPIOs as suggested
>   by Rob and Vladimir
> - Use 'regulator_get()' not the optional version, and list only 'vcc' as
>   requested supply
> - Addressed Laurent's review comments and removed Eagle display enablement 
> patch
>   to be sent separately
>
> v5 -> v6:
> - Drop check for CONFIG_OF as it is a Kconfig dependency
> - Add Niklas Reviewed-by tags
> - List [3/3] depenencies below commit message to ease integration
>
> v4 -> v5:
> - Fix punctuation in bindings documentation
> - Add small statement to bindings document to clarify the chip has no
>   control bus
> - Print regulator name in enable/disable routines error path
> - Add Andrzej Reviewed-by tag
>
> v3 -> v4:
> - Rename permutations of "pdwn" to just "pdwn" everywhere in the series
> - Improve power enable/disable routines as suggested by Andrzej and Sergei
> - Change "pdwn" gpio initialization to use the logical output level
> - Change Kconfig description
>
> v2 -> v3:
> - Drop support for "lvds-decoder" and make the driver THC63LVD1024 specific
> -- Rework bindings to describe multiple input/output ports
> -- Rename driver and remove "lvds-decoder" references
> -- Rework Eagle DTS to use new bindings
>
> v1 -> v2:
> - Drop support for THC63LVD1024
>
> Jacopo Mondi (2):
>   dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder
>   drm: bridge: Add thc63lvd1024 LVDS decoder driver
>
>  .../bindings/display/bridge/thine,thc63lvd1024.txt |  60 ++
>  drivers/gpu/drm/bridge/Kconfig |   6 +
>  drivers/gpu/drm/bridge/Makefile|   1 +
>  drivers/gpu/drm/bridge/thc63lvd1024.c  | 205 
> +
>  4 files changed, 272 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
>  create mode 100644 drivers/gpu/drm/bridge/thc63lvd1024.c
>
> --
> 2.7.4
>
>
>
>

Re: [PATCH v3 0/4] regulator: bd9571mwv: Add support for DDR backup mode

[Lee Jones]

On Fri, 20 Apr 2018, Geert Uytterhoeven wrote:
> On Fri, Apr 20, 2018 at 9:49 AM, Lee Jones  wrote:
> > On Wed, 18 Apr 2018, Geert Uytterhoeven wrote:
> >> The ROHM BD9571MWV PMIC on the Renesas Salvator-X(S) and ULCB
> >> development boards supports DDR Backup Power, which means that the DDR
> >> power rails can be kept powered while the main SoC is powered down.
> >
> > Should this set be applied together, or can the MFD patches be applied
> > on their own, without the Regulator patch?
> 
> The regulator patch depends on the MFD patches, so it's best for them to
> go in together.
> 
> > If the former, then we're going to need an Ack from Mark.
> 
> Alternative, as you've already supplied (some form of) your Ack for the firs
> 3 patches, they can go in through Mark? All of it is enhancing the
> regulator part.

Yes, that's fine too:

Acked-by: Lee Jones 

-- 
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 49/61] staging: nvec: simplify getting .drvdata

[Marc Dietrich]

Am Donnerstag, 19. April 2018, 16:06:19 CEST schrieb Wolfram Sang:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 

Acked-by: Marc Dietrich 

> ---
> 
> Build tested only. buildbot is happy. Please apply individually.
> 
>  drivers/staging/nvec/nvec.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
> index 52054a528723..2a5e0dcf4162 100644
> --- a/drivers/staging/nvec/nvec.c
> +++ b/drivers/staging/nvec/nvec.c
> @@ -925,8 +925,7 @@ static int tegra_nvec_remove(struct platform_device
> *pdev) static int nvec_suspend(struct device *dev)
>  {
>   int err;
> - struct platform_device *pdev = to_platform_device(dev);
> - struct nvec_chip *nvec = platform_get_drvdata(pdev);
> + struct nvec_chip *nvec = dev_get_drvdata(dev);
>   struct nvec_msg *msg;
>   char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND };
> 
> @@ -946,8 +945,7 @@ static int nvec_suspend(struct device *dev)
> 
>  static int nvec_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct nvec_chip *nvec = platform_get_drvdata(pdev);
> + struct nvec_chip *nvec = dev_get_drvdata(dev);
> 
>   dev_dbg(nvec->dev, "resuming\n");
>   tegra_init_i2c_slave(nvec);

Re: [PATCH] mmc: renesas_sdhi_internal_dmac: add R8A77980 to whitelist

[Sergei Shtylyov]

Hello!

On 4/20/2018 10:08 AM, Ulf Hansson wrote:


I've successfully tested eMMC on R8A77980/Condor. R8A77980 has a single
SDHI core anyway, so can't be a subject of the known RX DMA errata...


   Should have been s/of/to/, I think.


Lucky you ;)


Signed-off-by: Sergei Shtylyov 


Reviewed-by: Wolfram Sang 


Seems like this one also should go for fixes/stable then?


   In its current form it's only good for the next branch. Recasting/merging 
it for the fixes branch will result in the rejects in the next branch where 
you have already merged Wolfram's patches. The decision is up to you, of course...



Kind regards
Uffe


MBR, Sergei

Re: [PATCH] sh: mm: Fix unprotected access to struct device

[Christoph Hellwig]

On Wed, Apr 18, 2018 at 03:13:14PM +0200, jacopo mondi wrote:
> As long as it goes for arch/sh, the only user of dma_alloc_coherent()
> is platform_resource_setup_memory(), and it has been fixed by this
> patch.

Great!

> 
> Unfortunately, as Thomas pointed out, there are drivers which calls
> into this with the wrong 'struct device' as the sh_eth one he had fixed.

Yes, we'll need fixes there.  Other DMA ops implementations also look
at struct device, so they generally are buggy.

> I would then say that as long as it goes for the NULL case, we should be
> fine now.

Then I'd say skil that part, please.

Re: [PATCH] sh: mm: Fix unprotected access to struct device

[Christoph Hellwig]

On Tue, Apr 17, 2018 at 03:54:07PM +0200, Thomas Petazzoni wrote:
> 
>   dma_alloc_coherent(>dev, memsize, _handle, GFP_KERNEL);
> 
> and one to switch to the WARN_ON + if(dev) model. But I don't really
> care either way, so:
> 
> Reviewed-by: Thomas Petazzoni 

Yes, these should be separate patches.  And I actually hope we can
do with the NULL dev check, but that is a different sub-thread.

Re: [PATCH 43/61] pwm: simplify getting .drvdata

[Nicolas Ferre]

On 19/04/2018 at 16:06, Wolfram Sang wrote:

We should get drvdata from struct device directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang 


Acked-by: Nicolas Ferre 


---

Build tested only. buildbot is happy. Please apply individually.

  drivers/pwm/pwm-atmel-tcb.c | 6 ++
  drivers/pwm/pwm-rcar.c  | 3 +--
  2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index 4fb1be246c44..0d0f8376bc35 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -460,8 +460,7 @@ MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
  #ifdef CONFIG_PM_SLEEP
  static int atmel_tcb_pwm_suspend(struct device *dev)
  {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
+   struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
void __iomem *base = tcbpwm->tc->regs;
int i;
  
@@ -478,8 +477,7 @@ static int atmel_tcb_pwm_suspend(struct device *dev)
  
  static int atmel_tcb_pwm_resume(struct device *dev)

  {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
+   struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
void __iomem *base = tcbpwm->tc->regs;
int i;
  
diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c

index 91d11f2e2fef..748f614d5375 100644
--- a/drivers/pwm/pwm-rcar.c
+++ b/drivers/pwm/pwm-rcar.c
@@ -261,8 +261,7 @@ MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
  #ifdef CONFIG_PM_SLEEP
  static struct pwm_device *rcar_pwm_dev_to_pwm_dev(struct device *dev)
  {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
+   struct rcar_pwm_chip *rcar_pwm = dev_get_drvdata(dev);
struct pwm_chip *chip = _pwm->chip;
  
  	return >pwms[0];





--
Nicolas Ferre

Re: [PATCH v3 0/4] regulator: bd9571mwv: Add support for DDR backup mode

[Geert Uytterhoeven]

Hi Lee,

On Fri, Apr 20, 2018 at 9:49 AM, Lee Jones  wrote:
> On Wed, 18 Apr 2018, Geert Uytterhoeven wrote:
>> The ROHM BD9571MWV PMIC on the Renesas Salvator-X(S) and ULCB
>> development boards supports DDR Backup Power, which means that the DDR
>> power rails can be kept powered while the main SoC is powered down.
>
> Should this set be applied together, or can the MFD patches be applied
> on their own, without the Regulator patch?

The regulator patch depends on the MFD patches, so it's best for them to
go in together.

> If the former, then we're going to need an Ack from Mark.

Alternative, as you've already supplied (some form of) your Ack for the firs
3 patches, they can go in through Mark? All of it is enhancing the
regulator part.

I don't care much which path the patches take, though.

Thanks!

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 61/61] ASoC: atmel: simplify getting .drvdata

[Nicolas Ferre]

On 19/04/2018 at 16:06, Wolfram Sang wrote:

We should get drvdata from struct device directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang 


Acked-by: Nicolas Ferre 


---

Build tested only. buildbot is happy. Please apply individually.

  sound/soc/atmel/atmel_ssc_dai.c | 6 ++
  1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
index a1e2c5682dcd..4a0275a6505d 100644
--- a/sound/soc/atmel/atmel_ssc_dai.c
+++ b/sound/soc/atmel/atmel_ssc_dai.c
@@ -1002,8 +1002,7 @@ static const struct snd_soc_component_driver 
atmel_ssc_component = {
  
  static int asoc_ssc_init(struct device *dev)

  {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct ssc_device *ssc = platform_get_drvdata(pdev);
+   struct ssc_device *ssc = dev_get_drvdata(dev);
int ret;
  
  	ret = snd_soc_register_component(dev, _ssc_component,

@@ -1033,8 +1032,7 @@ static int asoc_ssc_init(struct device *dev)
  
  static void asoc_ssc_exit(struct device *dev)

  {
-   struct platform_device *pdev = to_platform_device(dev);
-   struct ssc_device *ssc = platform_get_drvdata(pdev);
+   struct ssc_device *ssc = dev_get_drvdata(dev);
  
  	if (ssc->pdata->use_dma)

atmel_pcm_dma_platform_unregister(dev);




--
Nicolas Ferre

Re: [PATCH v3 0/4] regulator: bd9571mwv: Add support for DDR backup mode

[Lee Jones]

On Wed, 18 Apr 2018, Geert Uytterhoeven wrote:

>   Hi all,
> 
> The ROHM BD9571MWV PMIC on the Renesas Salvator-X(S) and ULCB
> development boards supports DDR Backup Power, which means that the DDR
> power rails can be kept powered while the main SoC is powered down.

Should this set be applied together, or can the MFD patches be applied
on their own, without the Regulator patch?

If the former, then we're going to need an Ack from Mark.

-- 
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 55/61] usb: mtu3: simplify getting .drvdata

[Chunfeng Yun]

hi,

On Thu, 2018-04-19 at 16:06 +0200, Wolfram Sang wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 
> ---
> 
> Build tested only. buildbot is happy. Please apply individually.
> 
>  drivers/usb/mtu3/mtu3_plat.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
> index 628d5ce356ca..46551f6d16fd 100644
> --- a/drivers/usb/mtu3/mtu3_plat.c
> +++ b/drivers/usb/mtu3/mtu3_plat.c
> @@ -447,8 +447,7 @@ static int mtu3_remove(struct platform_device *pdev)
>   */
>  static int __maybe_unused mtu3_suspend(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
> + struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
>  
>   dev_dbg(dev, "%s\n", __func__);
>  
> @@ -466,8 +465,7 @@ static int __maybe_unused mtu3_suspend(struct device *dev)
>  
>  static int __maybe_unused mtu3_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
> + struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
>   int ret;
>  
>   dev_dbg(dev, "%s\n", __func__);

Acked-by: Chunfeng Yun 

Thanks

Re: [PATCH 44/61] rtc: simplify getting .drvdata

[Michal Simek]

On 19.4.2018 16:06, Wolfram Sang wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 
> ---
> 
> Build tested only. buildbot is happy. Please apply individually.
> 
>  drivers/rtc/rtc-bq4802.c   |  6 ++
>  drivers/rtc/rtc-ds1216.c   |  6 ++
>  drivers/rtc/rtc-ds1511.c   |  9 +++--
>  drivers/rtc/rtc-ds1553.c   | 15 +--
>  drivers/rtc/rtc-ds1685.c   | 21 +++--
>  drivers/rtc/rtc-ds1742.c   |  6 ++
>  drivers/rtc/rtc-lpc32xx.c  | 16 ++--
>  drivers/rtc/rtc-m48t59.c   | 41 -
>  drivers/rtc/rtc-mv.c   |  3 +--
>  drivers/rtc/rtc-mxc.c  | 21 +++--
>  drivers/rtc/rtc-pcap.c | 15 +--
>  drivers/rtc/rtc-sh.c   | 15 +--
>  drivers/rtc/rtc-stk17ta8.c | 15 +--
>  drivers/rtc/rtc-test.c |  3 +--
>  drivers/rtc/rtc-zynqmp.c   | 10 --

Acked-by: Michal Simek  (for zynqmp)

Thanks,
Michal

Re: [PATCH 53/61] tty: serial: simplify getting .drvdata

[Michal Simek]

On 19.4.2018 16:06, Wolfram Sang wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 
> ---
> 
> Build tested only. buildbot is happy. Please apply individually.
> 
>  drivers/tty/serial/imx.c  | 18 ++
>  drivers/tty/serial/qcom_geni_serial.c |  6 ++
>  drivers/tty/serial/st-asc.c   |  6 ++
>  drivers/tty/serial/xilinx_uartps.c|  6 ++

Acked-by: Michal Simek  (for xilinx)

Thanks,
Michal

Re: [PATCH 46/61] spi: simplify getting .drvdata

[Michal Simek]

On 19.4.2018 16:06, Wolfram Sang wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 
> ---
> 
> Build tested only. buildbot is happy. Please apply individually.
> 
>  drivers/spi/spi-cadence.c  | 6 ++
>  drivers/spi/spi-zynqmp-gqspi.c | 6 ++
>  2 files changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
> index 5c9516ae4942..de394422b611 100644
> --- a/drivers/spi/spi-cadence.c
> +++ b/drivers/spi/spi-cadence.c
> @@ -686,8 +686,7 @@ static int cdns_spi_remove(struct platform_device *pdev)
>   */
>  static int __maybe_unused cdns_spi_suspend(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct spi_master *master = platform_get_drvdata(pdev);
> + struct spi_master *master = dev_get_drvdata(dev);
>  
>   return spi_master_suspend(master);
>  }
> @@ -702,8 +701,7 @@ static int __maybe_unused cdns_spi_suspend(struct device 
> *dev)
>   */
>  static int __maybe_unused cdns_spi_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct spi_master *master = platform_get_drvdata(pdev);
> + struct spi_master *master = dev_get_drvdata(dev);
>   struct cdns_spi *xspi = spi_master_get_devdata(master);
>  
>   cdns_spi_init_hw(xspi);
> diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
> index 18aeaceee286..3608db4ff368 100644
> --- a/drivers/spi/spi-zynqmp-gqspi.c
> +++ b/drivers/spi/spi-zynqmp-gqspi.c
> @@ -918,8 +918,7 @@ static int zynqmp_qspi_start_transfer(struct spi_master 
> *master,
>   */
>  static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct spi_master *master = platform_get_drvdata(pdev);
> + struct spi_master *master = dev_get_drvdata(dev);
>  
>   spi_master_suspend(master);
>  
> @@ -939,8 +938,7 @@ static int __maybe_unused zynqmp_qspi_suspend(struct 
> device *dev)
>   */
>  static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct spi_master *master = platform_get_drvdata(pdev);
> + struct spi_master *master = dev_get_drvdata(dev);
>   struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
>   int ret = 0;
>  
> 

Acked-by: Michal Simek 

Thanks,
Michal

Re: [PATCH 47/61] staging: greybus: simplify getting .drvdata

[Johan Hovold]

On Thu, Apr 19, 2018 at 04:06:17PM +0200, Wolfram Sang wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 

Acked-by: Johan Hovold 

Re: [PATCH 59/61] watchdog: simplify getting .drvdata

[Michal Simek]

On 19.4.2018 16:06, Wolfram Sang wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 
> ---
> 
> Build tested only. buildbot is happy. Please apply individually.
> 
>  drivers/watchdog/cadence_wdt.c   | 6 ++
>  drivers/watchdog/of_xilinx_wdt.c | 6 ++

Acked-by: Michal Simek 

Thanks,
Michal

Re: [PATCH 10/61] gpio: simplify getting .drvdata

[Michal Simek]

Hi Wolfram,

On 19.4.2018 16:05, Wolfram Sang wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
> 
> Signed-off-by: Wolfram Sang 
> ---
> 
> Build tested only. buildbot is happy. Please apply individually.
> 
>  drivers/gpio/gpio-dwapb.c |  6 ++
>  drivers/gpio/gpio-lynxpoint.c |  3 +--
>  drivers/gpio/gpio-omap.c  | 12 
>  drivers/gpio/gpio-tegra.c |  6 ++
>  drivers/gpio/gpio-zynq.c  |  6 ++
>  5 files changed, 11 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
> index 226977f78482..caaabb79e31f 100644
> --- a/drivers/gpio/gpio-dwapb.c
> +++ b/drivers/gpio/gpio-dwapb.c
> @@ -732,8 +732,7 @@ static int dwapb_gpio_remove(struct platform_device *pdev)
>  #ifdef CONFIG_PM_SLEEP
>  static int dwapb_gpio_suspend(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
> + struct dwapb_gpio *gpio = dev_get_drvdata(dev);
>   struct gpio_chip *gc= >ports[0].gc;
>   unsigned long flags;
>   int i;
> @@ -777,8 +776,7 @@ static int dwapb_gpio_suspend(struct device *dev)
>  
>  static int dwapb_gpio_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
> + struct dwapb_gpio *gpio = dev_get_drvdata(dev);
>   struct gpio_chip *gc= >ports[0].gc;
>   unsigned long flags;
>   int i;
> diff --git a/drivers/gpio/gpio-lynxpoint.c b/drivers/gpio/gpio-lynxpoint.c
> index 1e557b10d73e..55fa33b7209f 100644
> --- a/drivers/gpio/gpio-lynxpoint.c
> +++ b/drivers/gpio/gpio-lynxpoint.c
> @@ -408,8 +408,7 @@ static int lp_gpio_runtime_resume(struct device *dev)
>  
>  static int lp_gpio_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct lp_gpio *lg = platform_get_drvdata(pdev);
> + struct lp_gpio *lg = dev_get_drvdata(dev);
>   unsigned long reg;
>   int i;
>  
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 35971a341c40..b4f8a048a2a1 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -856,8 +856,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
>  
>  static int omap_mpuio_suspend_noirq(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct gpio_bank*bank = platform_get_drvdata(pdev);
> + struct gpio_bank*bank = dev_get_drvdata(dev);
>   void __iomem*mask_reg = bank->base +
>   OMAP_MPUIO_GPIO_MASKIT / bank->stride;
>   unsigned long   flags;
> @@ -871,8 +870,7 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
>  
>  static int omap_mpuio_resume_noirq(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct gpio_bank*bank = platform_get_drvdata(pdev);
> + struct gpio_bank*bank = dev_get_drvdata(dev);
>   void __iomem*mask_reg = bank->base +
>   OMAP_MPUIO_GPIO_MASKIT / bank->stride;
>   unsigned long   flags;
> @@ -1284,8 +1282,7 @@ static void omap_gpio_restore_context(struct gpio_bank 
> *bank);
>  
>  static int omap_gpio_runtime_suspend(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct gpio_bank *bank = platform_get_drvdata(pdev);
> + struct gpio_bank *bank = dev_get_drvdata(dev);
>   u32 l1 = 0, l2 = 0;
>   unsigned long flags;
>   u32 wake_low, wake_hi;
> @@ -1352,8 +1349,7 @@ static void omap_gpio_init_context(struct gpio_bank *p);
>  
>  static int omap_gpio_runtime_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct gpio_bank *bank = platform_get_drvdata(pdev);
> + struct gpio_bank *bank = dev_get_drvdata(dev);
>   u32 l = 0, gen, gen0, gen1;
>   unsigned long flags;
>   int c;
> diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
> index 94396caaca75..04c963f03b68 100644
> --- a/drivers/gpio/gpio-tegra.c
> +++ b/drivers/gpio/gpio-tegra.c
> @@ -403,8 +403,7 @@ static void tegra_gpio_irq_handler(struct irq_desc *desc)
>  #ifdef CONFIG_PM_SLEEP
>  static int tegra_gpio_resume(struct device *dev)
>  {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
> + struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
>   unsigned long flags;
>   unsigned int b, p;
>  
> @@ -443,8 +442,7 @@ static int tegra_gpio_resume(struct device *dev)
>  
>  static int tegra_gpio_suspend(struct device *dev)
>  {
> - struct platform_device *pdev = 

Re: [PATCH 40/61] platform: x86: simplify getting .drvdata

[Wolfram Sang]

> (I'm not sure what you mean by "Please apply individually")

Right, that is not very precise. "Individually" as "per subsystem
individually". I.e. I don't want to collect tags and push it upstream as
one huge pull-request.

Thanks!



signature.asc
Description: PGP signature

Re: [PATCH 28/61] mmc: host: simplify getting .drvdata

[Ulf Hansson]

On 19 April 2018 at 16:05, Wolfram Sang
 wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
>
> Signed-off-by: Wolfram Sang 

Thanks, applied for next!

Kind regards
Uffe

> ---
>
> Build tested only. buildbot is happy. Please apply individually.
>
>  drivers/mmc/host/davinci_mmc.c | 6 ++
>  drivers/mmc/host/sdhci-of-arasan.c | 6 ++
>  drivers/mmc/host/wmt-sdmmc.c   | 6 ++
>  3 files changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
> index 8e363174f9d6..9e68c3645e22 100644
> --- a/drivers/mmc/host/davinci_mmc.c
> +++ b/drivers/mmc/host/davinci_mmc.c
> @@ -1377,8 +1377,7 @@ static int __exit davinci_mmcsd_remove(struct 
> platform_device *pdev)
>  #ifdef CONFIG_PM
>  static int davinci_mmcsd_suspend(struct device *dev)
>  {
> -   struct platform_device *pdev = to_platform_device(dev);
> -   struct mmc_davinci_host *host = platform_get_drvdata(pdev);
> +   struct mmc_davinci_host *host = dev_get_drvdata(dev);
>
> writel(0, host->base + DAVINCI_MMCIM);
> mmc_davinci_reset_ctrl(host, 1);
> @@ -1389,8 +1388,7 @@ static int davinci_mmcsd_suspend(struct device *dev)
>
>  static int davinci_mmcsd_resume(struct device *dev)
>  {
> -   struct platform_device *pdev = to_platform_device(dev);
> -   struct mmc_davinci_host *host = platform_get_drvdata(pdev);
> +   struct mmc_davinci_host *host = dev_get_drvdata(dev);
>
> clk_enable(host->clk);
> mmc_davinci_reset_ctrl(host, 0);
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
> b/drivers/mmc/host/sdhci-of-arasan.c
> index c33a5f7393bd..bed3612247b0 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -359,8 +359,7 @@ static const struct sdhci_pltfm_data 
> sdhci_arasan_cqe_pdata = {
>   */
>  static int sdhci_arasan_suspend(struct device *dev)
>  {
> -   struct platform_device *pdev = to_platform_device(dev);
> -   struct sdhci_host *host = platform_get_drvdata(pdev);
> +   struct sdhci_host *host = dev_get_drvdata(dev);
> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
> int ret;
> @@ -403,8 +402,7 @@ static int sdhci_arasan_suspend(struct device *dev)
>   */
>  static int sdhci_arasan_resume(struct device *dev)
>  {
> -   struct platform_device *pdev = to_platform_device(dev);
> -   struct sdhci_host *host = platform_get_drvdata(pdev);
> +   struct sdhci_host *host = dev_get_drvdata(dev);
> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
> int ret;
> diff --git a/drivers/mmc/host/wmt-sdmmc.c b/drivers/mmc/host/wmt-sdmmc.c
> index fd30ac7da5e5..3ba42f508014 100644
> --- a/drivers/mmc/host/wmt-sdmmc.c
> +++ b/drivers/mmc/host/wmt-sdmmc.c
> @@ -928,8 +928,7 @@ static int wmt_mci_remove(struct platform_device *pdev)
>  static int wmt_mci_suspend(struct device *dev)
>  {
> u32 reg_tmp;
> -   struct platform_device *pdev = to_platform_device(dev);
> -   struct mmc_host *mmc = platform_get_drvdata(pdev);
> +   struct mmc_host *mmc = dev_get_drvdata(dev);
> struct wmt_mci_priv *priv;
>
> if (!mmc)
> @@ -953,8 +952,7 @@ static int wmt_mci_suspend(struct device *dev)
>  static int wmt_mci_resume(struct device *dev)
>  {
> u32 reg_tmp;
> -   struct platform_device *pdev = to_platform_device(dev);
> -   struct mmc_host *mmc = platform_get_drvdata(pdev);
> +   struct mmc_host *mmc = dev_get_drvdata(dev);
> struct wmt_mci_priv *priv;
>
> if (mmc) {
> --
> 2.11.0
>

Re: [PATCH] mmc: renesas_sdhi_internal_dmac: add R8A77980 to whitelist

[Ulf Hansson]

On 19 April 2018 at 22:09, Wolfram Sang  wrote:
> On Thu, Apr 19, 2018 at 11:07:44PM +0300, Sergei Shtylyov wrote:
>> I've successfully tested eMMC on R8A77980/Condor. R8A77980 has a single
>> SDHI core anyway, so can't be a subject of the known RX DMA errata...
>
> Lucky you ;)
>
>> Signed-off-by: Sergei Shtylyov 
>
> Reviewed-by: Wolfram Sang 
>

Seems like this one also should go for fixes/stable then?

Kind regards
Uffe

Re: [PATCH v9 1/2] dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder

[Vladimir Zapolskiy]

Hi Jacopo,

On 04/18/2018 05:40 PM, Jacopo Mondi wrote:
> Document Thine THC63LVD1024 LVDS decoder device tree bindings.
> 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Andrzej Hajda 
> Reviewed-by: Niklas Söderlund 
> Reviewed-by: Laurent Pinchart 
> Reviewed-by: Rob Herring 
> ---
>  .../bindings/display/bridge/thine,thc63lvd1024.txt | 60 
> ++
>  1 file changed, 60 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
> 

Reviewed-by: Vladimir Zapolskiy 

--
With best wishes,
Vladimir

Re: [PATCH v9 2/2] drm: bridge: Add thc63lvd1024 LVDS decoder driver

[Vladimir Zapolskiy]

Hi Jacopo,

On 04/18/2018 05:40 PM, Jacopo Mondi wrote:
> Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel
> output converter.
> 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Andrzej Hajda 
> Reviewed-by: Niklas Söderlund 
> Reviewed-by: Laurent Pinchart 
> ---
>  drivers/gpu/drm/bridge/Kconfig|   6 +
>  drivers/gpu/drm/bridge/Makefile   |   1 +
>  drivers/gpu/drm/bridge/thc63lvd1024.c | 206 
> ++
>  3 files changed, 213 insertions(+)
>  create mode 100644 drivers/gpu/drm/bridge/thc63lvd1024.c

Reviewed-by: Vladimir Zapolskiy 

--
With best wishes,
Vladimir

Re: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

[Hoan Tran]

Hi Phil,

On Thu, Apr 19, 2018 at 3:03 AM, Phil Edworthy
 wrote:
> Hi Hoan
>
> On 18 April 2018 08:03 Hoan Tran wrote:
>> On Fri, Apr 13, 2018 at 9:47 AM, Phil Edworthy wrote:
>> > On 13 April 2018 17:37 Hoan Tran wrote:
>> >> On Fri, Apr 13, 2018 at 1:51 AM, Phil Edworthy wrote:
>> >> > The DesignWare GPIO IP can be configured for either 1 interrupt or
>> >> > 1 per GPIO in port A, but the driver currently only supports 1 
>> >> > interrupt.
>> >> > See the DesignWare DW_apb_gpio Databook description of the
>> >> > 'GPIO_INTR_IO' parameter.
>> >> >
>> >> > This change allows the driver to work with up to 32 interrupts, it
>> >> > will get as many interrupts as specified in the DT 'interrupts' 
>> >> > property.
>> >> > It doesn't do anything clever with the different interrupts, it
>> >> > just calls the same handler used for single interrupt hardware.
>> >> >
>> >> > Signed-off-by: Phil Edworthy 
>> >> > ---
>> >> > One point to mention is that I have made it possible for users to
>> >> > have unconncted interrupts by specifying holes in the list of 
>> >> > interrupts.
>> >> > This is done by supporting the interrupts-extended DT prop.
>> >> > However, I have no use for this and had to hack some test case for this.
>> >> > Perhaps the driver should support 1 interrupt or all GPIOa as 
>> >> > interrupts?
>> >> >
>> >> > v3:
>> >> >  - Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid
>> >> > bisect problems
>> >> > v2:
>> >> >  - Replaced interrupt-mask DT prop with support for the interrupts-
>> >> extended
>> >> >prop. This means replacing the call to irq_of_parse_and_map() with
>> calls
>> >> >to of_irq_parse_one() and irq_create_of_mapping().
>> >> >
>> >> > Note: There are a few *code* lines over 80 chars, but this is just
>> guidance,
>> >> >right? Especially as there are already some lines over 80 chars.
>> >> > ---
>> > [snip]
>> >
>> >> > -   if (has_acpi_companion(dev) && pp->idx == 0)
>> >> > -   pp->irq = 
>> >> > platform_get_irq(to_platform_device(dev), 0);
>> >> > +   if (has_acpi_companion(dev) && pp->idx == 0) {
>> >> > +   pp->irq[0] = 
>> >> > platform_get_irq(to_platform_device(dev),
>> 0);
>> >> > +   if (pp->irq[0])
>> >> > +   pp->has_irq = true;
>> >> > +   }
>> >>
>> >> It doesn't work for ACPI. Could you do the same logic for ACPI?
>> > I don’t have access to any device that was baked (i.e. fabbed) with
>> > multiple output interrupts from the Synopsys GPIO blocks and use ACPI.
>> > I don't know if any such device exists.
>>
>> Below code is tested on X-Gene system which supports 1 interrupt per GPIO
>> on Port A. You can update it into your patch.
>>
>> -   if (has_acpi_companion(dev) && pp->idx == 0)
>> -   pp->irq = platform_get_irq(to_platform_device(dev), 
>> 0);
>> +   if (has_acpi_companion(dev) && pp->idx == 0) {
>> +   unsigned int j;
>> +   for (j = 0; j < pp->ngpio; j++) {
>> +   pp->irq[j] =
>> platform_get_irq(to_platform_device(dev), j);
>> +   if (pp->irq[j])
>> +   pp->has_irq = true;
>> +   }
>> +   }
> Since I've already got some reviewed-by and acks for v4, I'll leave it to 
> Linus
> to decide if he wants me to roll your changes into this patch or for you to
> submit a separate patch.
>

I prefer this patch works for both DTB and ACPI. Btw let Linus decide.

Thanks
Hoan

> Thanks
> Phil
>
>
>> >> > pp->irq_shared  = false;
>> >> > pp->gpio_base   = -1;
>> >> > diff --git a/drivers/mfd/intel_quark_i2c_gpio.c
>> >> > b/drivers/mfd/intel_quark_i2c_gpio.c
>> >> > index 90e35de..5bddb84 100644
>> >> > --- a/drivers/mfd/intel_quark_i2c_gpio.c
>> >> > +++ b/drivers/mfd/intel_quark_i2c_gpio.c
>> >> > @@ -233,7 +233,8 @@ static int intel_quark_gpio_setup(struct
>> >> > pci_dev
>> >> *pdev, struct mfd_cell *cell)
>> >> > pdata->properties->idx  = 0;
>> >> > pdata->properties->ngpio= INTEL_QUARK_MFD_NGPIO;
>> >> > pdata->properties->gpio_base=
>> INTEL_QUARK_MFD_GPIO_BASE;
>> >> > -   pdata->properties->irq  = pdev->irq;
>> >> > +   pdata->properties->irq[0]   = pdev->irq;
>> >> > +   pdata->properties->has_irq  = true;
>> >> > pdata->properties->irq_shared   = true;
>> >> >
>> >> > cell->platform_data = pdata; diff --git
>> >> > a/include/linux/platform_data/gpio-dwapb.h
>> >> > b/include/linux/platform_data/gpio-dwapb.h
>> >> > index 2dc7f4a..5a52d69 100644
>> >> > --- a/include/linux/platform_data/gpio-dwapb.h
>> >> > +++ b/include/linux/platform_data/gpio-dwapb.h
>> >> > @@ -19,7 +19,8 @@ struct dwapb_port_property {
>> >> > unsigned 

Re: [PATCH 06/61] crypto: simplify getting .drvdata

[Krzysztof Kozlowski]

On Thu, Apr 19, 2018 at 4:05 PM, Wolfram Sang
 wrote:
> We should get drvdata from struct device directly. Going via
> platform_device is an unneeded step back and forth.
>
> Signed-off-by: Wolfram Sang 
> ---
>
> Build tested only. buildbot is happy. Please apply individually.
>
>  drivers/crypto/exynos-rng.c   | 6 ++
>  drivers/crypto/picoxcell_crypto.c | 6 ++
>  2 files changed, 4 insertions(+), 8 deletions(-)

Reviewed-by: Krzysztof Kozlowski 

Best regards,
Krzysztof