Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Wolfram Sang]

> > +   { .compatible = "renesas,sdhi-r8a77965", .data = 
> > _rcar_gen3_compatible, },

Do we need this line...

> > { .compatible = "renesas,rcar-gen3-sdhi", .data = 
> > _rcar_gen3_compatible, },

... with this generic fallback in place?

> > @@ -276,6 +277,7 @@ static void 
> > renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
> > /* generic ones */
> > { .soc_id = "r8a7795" },
> > { .soc_id = "r8a7796" },
> > +   { .soc_id = "r8a77965", .revision = "ES1.0" },
> 
> I think we can drop .revision = "ES1.0"
> 
> to be in keeping with 349936fcdaf8 ("mmc: renesas_sdhi_internal_dmac: use
> more generic whitelisting").

Ack.



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Re: [PATCH 3/5] tty: serial: sh-sci: Hide earlycon config question

[Rob Herring]

On Sun, Apr 15, 2018 at 2:09 PM, Rich Felker  wrote:
> On Sun, Apr 15, 2018 at 08:58:42PM +0200, Geert Uytterhoeven wrote:
>> Hi Rich,
>>
>> On Sun, Apr 15, 2018 at 2:34 AM, Rich Felker  wrote:
>> > On Thu, Nov 30, 2017 at 02:12:00PM +0100, Geert Uytterhoeven wrote:
>> >> Renesas H8/300 and ARM platforms use DT and support earlycon, so most
>> >> users want earlycon support to be enabled.
>> >>
>> >> On SuperH platforms, earlycon is not yet supported.
>> >>
>> >> Hence follow the above rationale to configure the default, unless
>> >> CONFIG_EXPERT is enabled.
>> >>
>> >> Signed-off-by: Geert Uytterhoeven 
>> >> ---
>> >>  drivers/tty/serial/Kconfig | 3 ++-
>> >>  1 file changed, 2 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
>> >> index 0c75562d620feb82..952a2c6a9da08fdd 100644
>> >> --- a/drivers/tty/serial/Kconfig
>> >> +++ b/drivers/tty/serial/Kconfig
>> >> @@ -774,10 +774,11 @@ config SERIAL_SH_SCI_CONSOLE
>> >>   default y
>> >>
>> >>  config SERIAL_SH_SCI_EARLYCON
>> >> - bool "Support for early console on SuperH SCI(F)"
>> >> + bool "Support for early console on SuperH SCI(F)" if EXPERT
>> >>   depends on SERIAL_SH_SCI=y
>> >>   select SERIAL_CORE_CONSOLE
>> >>   select SERIAL_EARLYCON
>> >> + default ARCH_RENESAS || H8300
>> >>
>> >>  config SERIAL_SH_SCI_DMA
>> >>   bool "DMA support"
>> >> --
>> >
>> > Can you clarify what the claim that SuperH does not support earlycon
>> > is based on? My understanding is that users were successfully using
>> > this option on Renesas SH systems, and I'm using it on J2 with the
>> > uartlite earlycon support which I added in 7cdcc29e49. I think if you
>> > want to omit the question it should always default to enabled.
>>
>> This is a patch for a Kconfig option for the Renesas sh-sci driver, which
>> supports the SCI, SCIF, SCIFA, SCIFB, and HSCIF uarts found on various
>> Renesas SoCs.
>>
>> Earlycon is used with DT only. While you are using earlycon on J2, you do
>> use it with a different uart (uartlite). Currently there's no upstream 
>> support
>> for using DT on Renesas SuperH SoCs. If this changes, the default for
>> SERIAL_SH_SCI_EARLYCON has to be changed.
>>
>> So none of my patch applies to the current state of SuperH Linux support.
>
> OK, I was under the impression (from users) that it worked on Renesas
> SH devices without DT. If it really doesn't then it doesn't matter
> until DT support for them is added. I've got some hardware to
> experiment with now so I'll see what can be done.

Yes, it works without DT (but maybe that is UART specific). It was
originally an x86 8250 thing.

The main thing you need is either fixmap support or ioremap has to
work before paging_init when early_params are processed.

Rob

Re: igt trouble with planes shared between multiple CRTCs (Re: [PATCH v2 0/8] R-Car DU: Support CRC calculation)

[Maarten Lankhorst]

Op 01-05-18 om 10:58 schreef Maarten Lankhorst:
> Hey,
>
> Op 30-04-18 om 16:56 schreef Daniel Vetter:
>> On Mon, Apr 30, 2018 at 04:55:24PM +0200, Daniel Vetter wrote:
>>> On Sat, Apr 28, 2018 at 12:07:04AM +0300, Laurent Pinchart wrote:
 Hi Daniel,

 (Removing the linux-media mailing list from CC as it is out of scope)

 You enquired on IRC whether this patch series passes the igt CRC tests.

 # ./kms_pipe_crc_basic --run-subtest read-crc-pipe-A
 IGT-Version: 1.22-gf447f5fc531d (aarch64) (Linux: 
 4.17.0-rc1-00085-g56e849d93cc9 aarch64)
 read-crc-pipe-A: Testing connector LVDS-1 using pipe A
 (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Test assertion failure 
 function igt_pipe_crc_start, file igt_debugfs.c:764:
 (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Failed assertion: 
 pipe_crc->crc_fd != -1
 (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Last errno: 5, 
 Input/output error
 Stack trace:
 Subtest read-crc-pipe-A failed.
  DEBUG 
 (kms_pipe_crc_basic:1638) DEBUG: Test requirement passed: !(pipe >= 
 data->display.n_pipes)
 (kms_pipe_crc_basic:1638) INFO: read-crc-pipe-A: Testing connector LVDS-1 
 using pipe A
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: LVDS-1: set_pipe(A)
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: LVDS-1: Selecting pipe A
 (kms_pipe_crc_basic:1638) DEBUG: Clearing the fb with color 
 (0.00,1.00,0.00)
 (kms_pipe_crc_basic:1638) igt-fb-DEBUG: 
 igt_create_fb_with_bo_size(width=1024, height=768, format=0x34325258, 
 tiling=0x0, size=0)
 (kms_pipe_crc_basic:1638) igt-fb-DEBUG: 
 igt_create_fb_with_bo_size(handle=1, pitch=4096)
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: Test requirement passed: 
 plane_idx >= 0 && plane_idx < pipe->n_planes
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: plane_set_fb(140)
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: plane_set_size 
 (1024x768)
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: fb_set_position(0,0)
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: 
 fb_set_size(1024x768)
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: commit {
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: LVDS-1: SetCrtc pipe 
 A, fb 140, src (0, 0), mode 1024x768
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe A, 
 disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe A, 
 plane 2, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe A, 
 plane 3, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe A, 
 plane 4, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe B, 
 disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
 plane 1, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
 plane 2, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
 plane 3, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
 plane 4, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe C, 
 disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
 plane 1, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
 plane 2, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
 plane 3, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
 plane 4, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe D, 
 disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe D, 
 disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe D, 
 plane 2, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe D, 
 plane 3, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe D, 
 plane 4, disabling
 (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: }
 (kms_pipe_crc_basic:1638) igt-debugfs-DEBUG: Opening debugfs directory 
 '/sys/kernel/debug/dri/0'
 (kms_pipe_crc_basic:1638) igt-debugfs-DEBUG: Opening debugfs directory 
 '/sys/kernel/debug/dri/0'
 (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Test assertion failure 
 function igt_pipe_crc_start, file igt_debugfs.c:764:
 (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Failed assertion: 
 pipe_crc->crc_fd != -1
 (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Last errno: 5, 
 Input/output error
 (kms_pipe_crc_basic:1638) igt-core-INFO: Stack trace:
   END  
 Subtest read-crc-pipe-A: FAIL (0.061s)

 I think the 

Re: [PATCH/RFT 3/3] arm64: dts: r8a77965: Add SDHI device nodes

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:16AM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara 
> 
> Add SDHI nodes to the DT of the r8a77965 SoC.
> 
> Based on several similar patches of the R8A7796 device tree
> by Simon Horman .
> 
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

This patch needs to be rebased on top of the devel branch of the renesas
tree. Otherwise it looks good to me.

> ---
>  arch/arm64/boot/dts/renesas/r8a77965.dtsi | 68 
> ++-
>  1 file changed, 48 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
> b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> index f0871fc..6860704 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> @@ -834,26 +834,6 @@
>   };
>   };
>  
> - sdhi0: sd@ee10 {
> - reg = <0 0xee10 0 0x2000>;
> - /* placeholder */
> - };
> -
> - sdhi1: sd@ee12 {
> - reg = <0 0xee12 0 0x2000>;
> - /* placeholder */
> - };
> -
> - sdhi2: sd@ee14 {
> - reg = <0 0xee14 0 0x2000>;
> - /* placeholder */
> - };
> -
> - sdhi3: sd@ee16 {
> - reg = <0 0xee16 0 0x2000>;
> - /* placeholder */
> - };
> -
>   usb3_phy0: usb-phy@e65ee000 {
>   reg = <0 0xe65ee000 0 0x90>;
>   #phy-cells = <0>;
> @@ -874,5 +854,53 @@
>   reg = <0 0xe602 0 0x0c>;
>   /* placeholder */
>   };
> +
> + sdhi0: sd@ee10 {
> + compatible = "renesas,sdhi-r8a77965",
> +  "renesas,rcar-gen3-sdhi";
> + reg = <0 0xee10 0 0x2000>;
> + interrupts = ;
> + clocks = < CPG_MOD 314>;
> + max-frequency = <2>;
> + power-domains = < 32>;
> + resets = < 314>;
> + status = "disabled";
> + };
> +
> + sdhi1: sd@ee12 {
> + compatible = "renesas,sdhi-r8a77965",
> +  "renesas,rcar-gen3-sdhi";
> + reg = <0 0xee12 0 0x2000>;
> + interrupts = ;
> + clocks = < CPG_MOD 313>;
> + max-frequency = <2>;
> + power-domains = < 32>;
> + resets = < 313>;
> + status = "disabled";
> + };
> +
> + sdhi2: sd@ee14 {
> + compatible = "renesas,sdhi-r8a77965",
> +  "renesas,rcar-gen3-sdhi";
> + reg = <0 0xee14 0 0x2000>;
> + interrupts = ;
> + clocks = < CPG_MOD 312>;
> + max-frequency = <2>;
> + power-domains = < 32>;
> + resets = < 312>;
> + status = "disabled";
> + };
> +
> + sdhi3: sd@ee16 {
> + compatible = "renesas,sdhi-r8a77965",
> +  "renesas,rcar-gen3-sdhi";
> + reg = <0 0xee16 0 0x2000>;
> + interrupts = ;
> + clocks = < CPG_MOD 311>;
> + max-frequency = <2>;
> + power-domains = < 32>;
> + resets = < 311>;
> + status = "disabled";
> + };
>   };
>  };
> -- 
> 1.9.1
> 

Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:15AM +0900, Yoshihiro Kaneko wrote:
> From: Masaharu Hayakawa 
> 
> This patch adds r8a77965 support in SDHI.
> 
> Signed-off-by: Masaharu Hayakawa 
> Signed-off-by: Yoshihiro Kaneko 
> ---
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c  | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt 
> b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> index ba38252..ee978c9 100644
> --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> @@ -26,6 +26,7 @@ Required properties:
>   "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
>   "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
>   "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
> + "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
>   "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
>   "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
>   "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
> diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c 
> b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> index a6bf123..733ea8e 100644
> --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
> @@ -99,6 +99,7 @@
>  static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
>   { .compatible = "renesas,sdhi-r8a7795", .data = 
> _rcar_gen3_compatible, },
>   { .compatible = "renesas,sdhi-r8a7796", .data = 
> _rcar_gen3_compatible, },
> + { .compatible = "renesas,sdhi-r8a77965", .data = 
> _rcar_gen3_compatible, },
>   { .compatible = "renesas,rcar-gen3-sdhi", .data = 
> _rcar_gen3_compatible, },
>   {},
>  };
> @@ -276,6 +277,7 @@ static void 
> renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
>   /* generic ones */
>   { .soc_id = "r8a7795" },
>   { .soc_id = "r8a7796" },
> + { .soc_id = "r8a77965", .revision = "ES1.0" },

I think we can drop .revision = "ES1.0"

to be in keeping with 349936fcdaf8 ("mmc: renesas_sdhi_internal_dmac: use
more generic whitelisting").

With that fixed:

Reviewed-by: Simon Horman 


>   { .soc_id = "r8a77980" },
>   { .soc_id = "r8a77995" },
>   { /* sentinel */ }
> -- 
> 1.9.1
> 

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:14AM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara 
> 
> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
> SoC.
> 
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Reviewed-by: Simon Horman 

> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 326 
> ++
>  1 file changed, 326 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c 
> b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> index cea9d05..0350197 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> @@ -1923,6 +1923,264 @@ enum {
>   RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>  };
>  
> +/* - SDHI0 
> -- */
> +static const unsigned int sdhi0_data1_pins[] = {
> + /* D0 */
> + RCAR_GP_PIN(3, 2),
> +};
> +
> +static const unsigned int sdhi0_data1_mux[] = {
> + SD0_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi0_data4_pins[] = {
> + /* D[0:3] */
> + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
> + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
> +};
> +
> +static const unsigned int sdhi0_data4_mux[] = {
> + SD0_DAT0_MARK, SD0_DAT1_MARK,
> + SD0_DAT2_MARK, SD0_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi0_ctrl_pins[] = {
> + /* CLK, CMD */
> + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> +};
> +
> +static const unsigned int sdhi0_ctrl_mux[] = {
> + SD0_CLK_MARK, SD0_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi0_cd_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(3, 12),
> +};
> +
> +static const unsigned int sdhi0_cd_mux[] = {
> + SD0_CD_MARK,
> +};
> +
> +static const unsigned int sdhi0_wp_pins[] = {
> + /* WP */
> + RCAR_GP_PIN(3, 13),
> +};
> +
> +static const unsigned int sdhi0_wp_mux[] = {
> + SD0_WP_MARK,
> +};
> +
> +/* - SDHI1 
> -- */
> +static const unsigned int sdhi1_data1_pins[] = {
> + /* D0 */
> + RCAR_GP_PIN(3, 8),
> +};
> +
> +static const unsigned int sdhi1_data1_mux[] = {
> + SD1_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi1_data4_pins[] = {
> + /* D[0:3] */
> + RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
> + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
> +};
> +
> +static const unsigned int sdhi1_data4_mux[] = {
> + SD1_DAT0_MARK, SD1_DAT1_MARK,
> + SD1_DAT2_MARK, SD1_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi1_ctrl_pins[] = {
> + /* CLK, CMD */
> + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
> +};
> +
> +static const unsigned int sdhi1_ctrl_mux[] = {
> + SD1_CLK_MARK, SD1_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi1_cd_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(3, 14),
> +};
> +
> +static const unsigned int sdhi1_cd_mux[] = {
> + SD1_CD_MARK,
> +};
> +
> +static const unsigned int sdhi1_wp_pins[] = {
> + /* WP */
> + RCAR_GP_PIN(3, 15),
> +};
> +
> +static const unsigned int sdhi1_wp_mux[] = {
> + SD1_WP_MARK,
> +};
> +
> +/* - SDHI2 
> -- */
> +static const unsigned int sdhi2_data1_pins[] = {
> + /* D0 */
> + RCAR_GP_PIN(4, 2),
> +};
> +
> +static const unsigned int sdhi2_data1_mux[] = {
> + SD2_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi2_data4_pins[] = {
> + /* D[0:3] */
> + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
> + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
> +};
> +
> +static const unsigned int sdhi2_data4_mux[] = {
> + SD2_DAT0_MARK, SD2_DAT1_MARK,
> + SD2_DAT2_MARK, SD2_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi2_data8_pins[] = {
> + /* D[0:7] */
> + RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
> + RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
> + RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
> + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
> +};
> +
> +static const unsigned int sdhi2_data8_mux[] = {
> + SD2_DAT0_MARK, SD2_DAT1_MARK,
> + SD2_DAT2_MARK, SD2_DAT3_MARK,
> + SD2_DAT4_MARK, SD2_DAT5_MARK,
> + SD2_DAT6_MARK, SD2_DAT7_MARK,
> +};
> +
> +static const unsigned int sdhi2_ctrl_pins[] = {
> + /* CLK, CMD */
> + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
> +};
> +
> +static const unsigned int sdhi2_ctrl_mux[] = {
> + SD2_CLK_MARK, SD2_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi2_cd_a_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(4, 13),
> +};
> +
> +static const unsigned int sdhi2_cd_a_mux[] = {
> + SD2_CD_A_MARK,
> +};
> +
> +static const unsigned int sdhi2_cd_b_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(5, 10),
> +};
> +
> +static const unsigned int sdhi2_cd_b_mux[] = {
> + SD2_CD_B_MARK,
> +};
> +
> +static const unsigned int sdhi2_wp_a_pins[] = {
> + /* WP */
> + RCAR_GP_PIN(4, 14),
> +};
> +
> +static const 

Re: [PATCH/RFT 0/3] mmc: renesas_sdhi: add support for r8a77965

[Simon Horman]

On Mon, Apr 30, 2018 at 04:48:13AM +0900, Yoshihiro Kaneko wrote:
> This series adds SDHI device support for r8a77965.
> 
> This series is based on the next branch of Ulf Hansson's mmc tree.
> 
> Masaharu Hayakawa (1):
>   mmc: renesas_sdhi: Add r8a77965 support
> 
> Takeshi Kihara (2):
>   pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

Thanks,

I did some testing of these patches applied on top of a merge of:
* renesas-devel-20180430-v4.17-rc3
* mmc/next (5bec8e5878e2)

And things seem to work :)

Tested-by: Simon Horman 



# dmesg | grep mmc
[1.519354] renesas_sdhi_internal_dmac ee14.sd: mmc0 base at 0xee14 
max clock rate 200 MHz
[1.726791] mmc0: new HS200 MMC card at address 0001
[1.732769] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB 
[1.737725] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[1.744019] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[1.750462] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev 
(243:0)
[1.879912] renesas_sdhi_internal_dmac ee10.sd: mmc1 base at 0xee10 
max clock rate 200 MHz
[1.949727] renesas_sdhi_internal_dmac ee16.sd: mmc2 base at 0xee16 
max clock rate 200 MHz
[2.055805] mmc1: new ultra high speed SDR50 SDHC card at address e624
[2.064320] mmcblk1: mmc1:e624 SU08G 7.40 GiB 
[2.119395] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[2.126544] mmcblk2: mmc2:0001 0 29.8 GiB 
# dmesg | egrep '(mmc|sd)'
[1.457672] renesas_sdhi_internal_dmac ee10.sd: Got CD GPIO
[1.463699] renesas_sdhi_internal_dmac ee10.sd: Got WP GPIO
[1.519354] renesas_sdhi_internal_dmac ee14.sd: mmc0 base at 0xee14 
max clock rate 200 MHz
[1.529021] renesas_sdhi_internal_dmac ee16.sd: Got CD GPIO
[1.535111] renesas_sdhi_internal_dmac ee16.sd: Got WP GPIO
[1.726791] mmc0: new HS200 MMC card at address 0001
[1.732769] mmcblk0: mmc0:0001 BGSD3R 29.1 GiB 
[1.737725] mmcblk0boot0: mmc0:0001 BGSD3R partition 1 16.0 MiB
[1.744019] mmcblk0boot1: mmc0:0001 BGSD3R partition 2 16.0 MiB
[1.750462] mmcblk0rpmb: mmc0:0001 BGSD3R partition 3 4.00 MiB, chardev 
(243:0)
[1.818520] renesas_sdhi_internal_dmac ee10.sd: Got CD GPIO
[1.824539] renesas_sdhi_internal_dmac ee10.sd: Got WP GPIO
[1.879912] renesas_sdhi_internal_dmac ee10.sd: mmc1 base at 0xee10 
max clock rate 200 MHz
[1.889678] renesas_sdhi_internal_dmac ee16.sd: Got CD GPIO
[1.895692] renesas_sdhi_internal_dmac ee16.sd: Got WP GPIO
[1.949727] renesas_sdhi_internal_dmac ee16.sd: mmc2 base at 0xee16 
max clock rate 200 MHz
[2.055805] mmc1: new ultra high speed SDR50 SDHC card at address e624
[2.064320] mmcblk1: mmc1:e624 SU08G 7.40 GiB 
[2.119395] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[2.126544] mmcblk2: mmc2:0001 0 29.8 GiB 
# time dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2048
[   92.910712] random: crng init done
2048+0 records in
2048+0 records out
real0m 12.90s
user0m 0.00s
sys 0m 4.19s
# time dd if=/dev/mmcblk1 of=/dev/null bs=1M count=512
512+0 records in
512+0 records out
real0m 11.61s
user0m 0.00s
sys 0m 1.06s
# time dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512
512+0 records in
512+0 records out
real0m 11.67s
user0m 0.00s
sys 0m 1.06s
# time dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=512
512+0 records in
512+0 records out
real0m 21.41s
user0m 0.00s
sys 0m 2.87s
# time dd if=/dev/zero of=/dev/mmcblk1 bs=1M count=64
64+0 records in
64+0 records out
real0m 18.07s
user0m 0.00s
sys 0m 0.43s
# time dd if=/dev/zero of=/dev/mmcblk2 bs=1M count=64
64+0 records in
64+0 records out
real0m 16.58s
user0m 0.00s
sys 0m 0.44s

Re: [PATCH] rcar-vin: remove generic gen3 compatible string

[Rob Herring]

On Wed, Apr 25, 2018 at 01:43:21AM +0200, Niklas Söderlund wrote:
> The compatible string "renesas,rcar-gen3-vin" was added before the
> Gen3 driver code was added but it's not possible to use. Each SoC in the
> Gen3 series require SoC specific knowledge in the driver to function.
> Remove it before it is added to any device tree descriptions.
> 
> Signed-off-by: Niklas Söderlund 
> ---
>  Documentation/devicetree/bindings/media/rcar_vin.txt | 1 -
>  1 file changed, 1 deletion(-)

Reviewed-by: Rob Herring 

RE: [PATCH] irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer

[Phil Edworthy]

Hi Rob,

On 01 May 2018 14:29 Rob Herring wrote:
> On Mon, Apr 23, 2018 at 02:33:06PM +0100, Phil Edworthy wrote:
> > On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each
> > configured to have 32 interrupt outputs, so we have a total of 96 GPIO
> > interrupts. All of these are passed to the GPIO IRQ Muxer, which
> > selects
> > 8 of the GPIO interrupts to pass onto the GIC. The interrupt signals
> > aren't latched, so there is nothing to do in this driver when an
> > interrupt is received, other than tell the corresponding GPIO block.
> >
> > Signed-off-by: Phil Edworthy 
> > ---
> >  .../interrupt-controller/renesas,rzn1-mux.txt  |  85 ++
> 
> Please split bindings to a separate patch.
Will do.

> >  drivers/irqchip/Kconfig|  10 ++
> >  drivers/irqchip/Makefile   |   1 +
> >  drivers/irqchip/irq-rzn1-irq-mux.c | 178
> +
> >  4 files changed, 274 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-mu
> > x.txt  create mode 100644 drivers/irqchip/irq-rzn1-irq-mux.c
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-
> > mux.txt
> > b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-
> > mux.txt
> > new file mode 100644
> > index 000..f28a365
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r
> > +++ zn1-mux.txt
> > @@ -0,0 +1,85 @@
> > +* Renesas RZ/N1 GPIO Interrupt Multiplexer
> > +
> > +On Renesas RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks
> > +each configured to have 32 interrupt outputs, so we have a total of
> > +96 GPIO interrupts. All of these are passed to the GPIO IRQ Muxer,
> > +which selects
> > +8 of the GPIO interrupts to pass onto the GIC.
> > +
> > +A single node in the device tree is used to describe the GPIO IRQ Muxer.
> > +
> > +Required properties:
> > +- compatible: the SoC specific name, i.e. "renesas,r9a06g032-gpioirq"
> > +   or "renesas,r9a06g033-gpioirq" followed by the SoC family name, i.e.
> > +   "renesas,rzn1-gpioirq".
> > +- interrupt-controller: Identifies the node as an interrupt controller.
> > +- #interrupt-cells: should be <1>. The meaning of the cells is the input
> > +   interrupt index, 0 to 95.
> > +- reg: Base address and size of GPIO IRQ Muxer registers.
> > +- interrupts: The list of interrupts generated by the muxer which are then
> > +   connected to a parent interrupt controller. The format of the interrupt
> > +   specifier depends in the interrupt parent controller.
> > +- gpioirq-#N: One property for each interrupt output from the GPIO IRQ
> Muxer
> > +   that specifies the input interrupt to use, #N is from 0 to 7.
> 
> Why do you need this in DT? Can't the driver handle this dynamically?
> When you request an interrupt on a GPIO line, then connect that GPIO line
> to a free IRQ line.
On the SoC that has this block, there is another CPU that runs firmware.
It's likely that the firmware will use some of these GPIO interrupts and
so we don't want them to move around. The firmware runs before Linux is
up, and luckily setting up the registers again won't affect the interrupts.

> If you really need this in DT, then interrupt-map can be used here.
Ok

> > +
> > +Optional properties:
> > +- interrupt-parent: pHandle of the parent interrupt controller, if not
> > +   inherited from the parent node.
> > +
> > +
> > +Example:
> > +
> > +   The following is an example for the RZ/N1D SoC.
> > +
> > +   gpioirq: gpioirq@51000480 {
> > +   compatible = "renesas,r9a06g032-gpioirq",
> > +   "renesas,rzn1-gpioirq";
> > +   reg = <0x51000480 0x20>;
> > +   interrupts =
> > +   ,
> > +   ,
> > +   ,
> > +   ,
> > +   ,
> > +   ,
> > +   ,
> > +   ;
> > +   interrupt-controller;
> > +   #interrupt-cells = <1>;
> > +   status = "disabled";
> 
> Don't show status in examples.
Ok

> > +   };
> > +
> > +   gpio0: gpio@5000b000 {
> > +   compatible = "snps,dw-apb-gpio";
> > +   reg = <0x5000b000 0x80>;
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   clock-names = "bus";
> > +   clocks = <_gpio0>;
> > +   status = "disabled";
> > +
> > +   gpio0a: gpio-controller@0 {
> > +   compatible = "snps,dw-apb-gpio-port";
> > +   bank-name = "gpio0a";
> > +   gpio-controller;
> > +   #gpio-cells = <2>;
> > +   snps,nr-gpios = <32>;
> > +   reg = <0>;
> > +
> > +   interrupt-controller;
> > +   interrupt-parent = <>;
> > +   interrupts =   < 0  1  2  3  4  5  

Re: [PATCH] dt-bindings: arm: consistently name r8a77965 as M3-N

[Rob Herring]

On Tue, Apr 24, 2018 at 07:54:42AM +0200, Simon Horman wrote:
> There is an inconsistency between the use of M3N and M3-N.
> This patch resolves this by consistently using the latter.
> 
> Signed-off-by: Simon Horman 
> ---
> Based on renesas-devel-20180423-v4.17-rc2
> ---
>  Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Rob Herring 

Re: [PATCH] irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer

[Rob Herring]

On Mon, Apr 23, 2018 at 02:33:06PM +0100, Phil Edworthy wrote:
> On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each
> configured to have 32 interrupt outputs, so we have a total of 96 GPIO
> interrupts. All of these are passed to the GPIO IRQ Muxer, which selects
> 8 of the GPIO interrupts to pass onto the GIC. The interrupt signals
> aren't latched, so there is nothing to do in this driver when an interrupt
> is received, other than tell the corresponding GPIO block.
> 
> Signed-off-by: Phil Edworthy 
> ---
>  .../interrupt-controller/renesas,rzn1-mux.txt  |  85 ++

Please split bindings to a separate patch.

>  drivers/irqchip/Kconfig|  10 ++
>  drivers/irqchip/Makefile   |   1 +
>  drivers/irqchip/irq-rzn1-irq-mux.c | 178 
> +
>  4 files changed, 274 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-mux.txt
>  create mode 100644 drivers/irqchip/irq-rzn1-irq-mux.c
> 
> diff --git 
> a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-mux.txt 
> b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-mux.txt
> new file mode 100644
> index 000..f28a365
> --- /dev/null
> +++ 
> b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzn1-mux.txt
> @@ -0,0 +1,85 @@
> +* Renesas RZ/N1 GPIO Interrupt Multiplexer
> +
> +On Renesas RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each
> +configured to have 32 interrupt outputs, so we have a total of 96 GPIO
> +interrupts. All of these are passed to the GPIO IRQ Muxer, which selects
> +8 of the GPIO interrupts to pass onto the GIC.
> +
> +A single node in the device tree is used to describe the GPIO IRQ Muxer.
> +
> +Required properties:
> +- compatible: the SoC specific name, i.e. "renesas,r9a06g032-gpioirq"
> +   or "renesas,r9a06g033-gpioirq" followed by the SoC family name, i.e.
> +   "renesas,rzn1-gpioirq".
> +- interrupt-controller: Identifies the node as an interrupt controller.
> +- #interrupt-cells: should be <1>. The meaning of the cells is the input
> +   interrupt index, 0 to 95.
> +- reg: Base address and size of GPIO IRQ Muxer registers.
> +- interrupts: The list of interrupts generated by the muxer which are then
> +   connected to a parent interrupt controller. The format of the interrupt
> +   specifier depends in the interrupt parent controller.
> +- gpioirq-#N: One property for each interrupt output from the GPIO IRQ Muxer
> +   that specifies the input interrupt to use, #N is from 0 to 7.

Why do you need this in DT? Can't the driver handle this dynamically? 
When you request an interrupt on a GPIO line, then connect that GPIO 
line to a free IRQ line. 

If you really need this in DT, then interrupt-map can be used here.

> +
> +Optional properties:
> +- interrupt-parent: pHandle of the parent interrupt controller, if not
> +   inherited from the parent node.
> +
> +
> +Example:
> +
> + The following is an example for the RZ/N1D SoC.
> +
> + gpioirq: gpioirq@51000480 {
> + compatible = "renesas,r9a06g032-gpioirq",
> + "renesas,rzn1-gpioirq";
> + reg = <0x51000480 0x20>;
> + interrupts =
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + status = "disabled";

Don't show status in examples.

> + };
> +
> + gpio0: gpio@5000b000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x5000b000 0x80>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "bus";
> + clocks = <_gpio0>;
> + status = "disabled";
> +
> + gpio0a: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + bank-name = "gpio0a";
> + gpio-controller;
> + #gpio-cells = <2>;
> + snps,nr-gpios = <32>;
> + reg = <0>;
> +
> + interrupt-controller;
> + interrupt-parent = <>;
> + interrupts =   < 0  1  2  3  4  5  6  7
> +  8  9 10 11 12 13 14 15
> + 16 17 18 19 20 21 22 23
> + 24 25 26 27 28 29 30 31 >;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> +
> + The following is an example for a board using this.

Don't show the soc/board split. This is convention, but not part of the 
binding.

> +
> +  {
> + status = "okay";
> + gpioirq-0 = <24>;  

Re: [PATCH 3/3] v4l: rcar_fdp1: Fix indentation oddities

[Kieran Bingham]

Hi Laurent,

Thanks for the fixes.

On 22/04/18 11:28, Laurent Pinchart wrote:
> Indentation is odd in several places, especially when printing messages
> to the kernel log. Fix it to match the usual coding style.
> 
> Signed-off-by: Laurent Pinchart 

Reviewed-by: Kieran Bingham 

> ---
>  drivers/media/platform/rcar_fdp1.c | 28 ++--
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/media/platform/rcar_fdp1.c 
> b/drivers/media/platform/rcar_fdp1.c
> index b13dec3081e5..81e8a761b924 100644
> --- a/drivers/media/platform/rcar_fdp1.c
> +++ b/drivers/media/platform/rcar_fdp1.c
> @@ -949,7 +949,7 @@ static void fdp1_configure_wpf(struct fdp1_ctx *ctx,
>   u32 rndctl;
>  
>   pstride = q_data->format.plane_fmt[0].bytesperline
> - << FD1_WPF_PSTRIDE_Y_SHIFT;
> + << FD1_WPF_PSTRIDE_Y_SHIFT;
>  
>   if (q_data->format.num_planes > 1)
>   pstride |= q_data->format.plane_fmt[1].bytesperline
> @@ -1143,8 +1143,8 @@ static int fdp1_m2m_job_ready(void *priv)
>   int dstbufs = 1;
>  
>   dprintk(ctx->fdp1, "+ Src: %d : Dst: %d\n",
> - v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx),
> - v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx));
> + v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx),
> + v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx));
>  
>   /* One output buffer is required for each field */
>   if (V4L2_FIELD_HAS_BOTH(src_q_data->format.field))
> @@ -1282,7 +1282,7 @@ static void fdp1_m2m_device_run(void *priv)
>  
>   fdp1_queue_field(ctx, fbuf);
>   dprintk(fdp1, "Queued Buffer [%d] last_field:%d\n",
> - i, fbuf->last_field);
> + i, fbuf->last_field);
>   }
>  
>   /* Queue as many jobs as our data provides for */
> @@ -1341,7 +1341,7 @@ static void device_frame_end(struct fdp1_dev *fdp1,
>   fdp1_job_free(fdp1, job);
>  
>   dprintk(fdp1, "curr_ctx->num_processed %d curr_ctx->translen %d\n",
> - ctx->num_processed, ctx->translen);
> + ctx->num_processed, ctx->translen);
>  
>   if (ctx->num_processed == ctx->translen ||
>   ctx->aborting) {
> @@ -1366,7 +1366,7 @@ static int fdp1_vidioc_querycap(struct file *file, void 
> *priv,
>   strlcpy(cap->driver, DRIVER_NAME, sizeof(cap->driver));
>   strlcpy(cap->card, DRIVER_NAME, sizeof(cap->card));
>   snprintf(cap->bus_info, sizeof(cap->bus_info),
> - "platform:%s", DRIVER_NAME);
> +  "platform:%s", DRIVER_NAME);
>   return 0;
>  }
>  
> @@ -1997,13 +1997,13 @@ static void fdp1_stop_streaming(struct vb2_queue *q)
>   /* Free smsk_data */
>   if (ctx->smsk_cpu) {
>   dma_free_coherent(ctx->fdp1->dev, ctx->smsk_size,
> - ctx->smsk_cpu, ctx->smsk_addr[0]);
> +   ctx->smsk_cpu, ctx->smsk_addr[0]);
>   ctx->smsk_addr[0] = ctx->smsk_addr[1] = 0;
>   ctx->smsk_cpu = NULL;
>   }
>  
>   WARN(!list_empty(>fields_queue),
> - "Buffer queue not empty");
> +  "Buffer queue not empty");
>   } else {
>   /* Empty Capture queues (Jobs) */
>   struct fdp1_job *job;
> @@ -2025,10 +2025,10 @@ static void fdp1_stop_streaming(struct vb2_queue *q)
>   fdp1_field_complete(ctx, ctx->previous);
>  
>   WARN(!list_empty(>fdp1->queued_job_list),
> - "Queued Job List not empty");
> +  "Queued Job List not empty");
>  
>   WARN(!list_empty(>fdp1->hw_job_list),
> - "HW Job list not empty");
> +  "HW Job list not empty");
>   }
>  }
>  
> @@ -2114,7 +2114,7 @@ static int fdp1_open(struct file *file)
>fdp1_ctrl_deint_menu);
>  
>   ctrl = v4l2_ctrl_new_std(>hdl, _ctrl_ops,
> - V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 2, 1, 1);
> +  V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 2, 1, 1);
>   if (ctrl)
>   ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
>  
> @@ -2351,8 +2351,8 @@ static int fdp1_probe(struct platform_device *pdev)
>   goto release_m2m;
>   }
>  
> - v4l2_info(>v4l2_dev,
> - "Device registered as /dev/video%d\n", vfd->num);
> + v4l2_info(>v4l2_dev, "Device registered as /dev/video%d\n",
> +   vfd->num);
>  
>   /* Power up the cells to read HW */
>   pm_runtime_enable(>dev);
> @@ -2371,7 +2371,7 @@ static int fdp1_probe(struct platform_device *pdev)
>   break;
>   default:
>   

[PATCH v8 4/8] media: vsp1: Convert display lists to use new body pool

[Kieran Bingham]

Adapt the dl->body0 object to use an object from the body pool. This
greatly reduces the pressure on the TLB for IPMMU use cases, as all of
the lists use a single allocation for the main body.

The CLU and LUT objects pre-allocate a pool containing three bodies,
allowing a userspace update before the hardware has committed a previous
set of tables.

Bodies are no longer 'freed' in interrupt context, but instead released
back to their respective pools. This allows us to remove the garbage
collector in the DLM.

Signed-off-by: Kieran Bingham 

---
v8:
 - Don't pass dlm->pool through vsp1_dl_list_alloc()  as it's already in the 
dlm.
 - Fix up comments

v4-v7:
 - No changes (except rebases)

v3:
 - 's/fragment/body', 's/fragments/bodies/'
 - CLU/LUT now allocate 3 bodies
 - vsp1_dl_list_fragments_free -> vsp1_dl_list_bodies_put

v2:
 - Use dl->body0->max_entries to determine header offset, instead of the
   global constant VSP1_DL_NUM_ENTRIES which is incorrect.
 - squash updates for LUT, CLU, and fragment cleanup into single patch.
   (Not fully bisectable when separated)

 drivers/media/platform/vsp1/vsp1_clu.c |  27 ++-
 drivers/media/platform/vsp1/vsp1_clu.h |   1 +-
 drivers/media/platform/vsp1/vsp1_dl.c  | 219 +-
 drivers/media/platform/vsp1/vsp1_dl.h  |   3 +-
 drivers/media/platform/vsp1/vsp1_lut.c |  27 ++-
 drivers/media/platform/vsp1/vsp1_lut.h |   1 +-
 6 files changed, 99 insertions(+), 179 deletions(-)

diff --git a/drivers/media/platform/vsp1/vsp1_clu.c 
b/drivers/media/platform/vsp1/vsp1_clu.c
index ebfbb915dcdc..8efa12f5e53f 100644
--- a/drivers/media/platform/vsp1/vsp1_clu.c
+++ b/drivers/media/platform/vsp1/vsp1_clu.c
@@ -19,6 +19,8 @@
 #define CLU_MIN_SIZE   4U
 #define CLU_MAX_SIZE   8190U
 
+#define CLU_SIZE   (17 * 17 * 17)
+
 /* 
-
  * Device Access
  */
@@ -43,19 +45,19 @@ static int clu_set_table(struct vsp1_clu *clu, struct 
v4l2_ctrl *ctrl)
struct vsp1_dl_body *dlb;
unsigned int i;
 
-   dlb = vsp1_dl_body_alloc(clu->entity.vsp1, 1 + 17 * 17 * 17);
+   dlb = vsp1_dl_body_get(clu->pool);
if (!dlb)
return -ENOMEM;
 
vsp1_dl_body_write(dlb, VI6_CLU_ADDR, 0);
-   for (i = 0; i < 17 * 17 * 17; ++i)
+   for (i = 0; i < CLU_SIZE; ++i)
vsp1_dl_body_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
 
spin_lock_irq(>lock);
swap(clu->clu, dlb);
spin_unlock_irq(>lock);
 
-   vsp1_dl_body_free(dlb);
+   vsp1_dl_body_put(dlb);
return 0;
 }
 
@@ -216,8 +218,16 @@ static void clu_configure(struct vsp1_entity *entity,
}
 }
 
+static void clu_destroy(struct vsp1_entity *entity)
+{
+   struct vsp1_clu *clu = to_clu(>subdev);
+
+   vsp1_dl_body_pool_destroy(clu->pool);
+}
+
 static const struct vsp1_entity_operations clu_entity_ops = {
.configure = clu_configure,
+   .destroy = clu_destroy,
 };
 
 /* 
-
@@ -243,6 +253,17 @@ struct vsp1_clu *vsp1_clu_create(struct vsp1_device *vsp1)
if (ret < 0)
return ERR_PTR(ret);
 
+   /*
+* Pre-allocate a body pool, with 3 bodies allowing a userspace update
+* before the hardware has committed a previous set of tables, handling
+* both the queued and pending dl entries. One extra entry is added to
+* the CLU_SIZE to allow for the VI6_CLU_ADDR header.
+*/
+   clu->pool = vsp1_dl_body_pool_create(clu->entity.vsp1, 3, CLU_SIZE + 1,
+0);
+   if (!clu->pool)
+   return ERR_PTR(-ENOMEM);
+
/* Initialize the control handler. */
v4l2_ctrl_handler_init(>ctrls, 2);
v4l2_ctrl_new_custom(>ctrls, _table_control, NULL);
diff --git a/drivers/media/platform/vsp1/vsp1_clu.h 
b/drivers/media/platform/vsp1/vsp1_clu.h
index c45e6e707592..cef2f44481ba 100644
--- a/drivers/media/platform/vsp1/vsp1_clu.h
+++ b/drivers/media/platform/vsp1/vsp1_clu.h
@@ -32,6 +32,7 @@ struct vsp1_clu {
spinlock_t lock;
unsigned int mode;
struct vsp1_dl_body *clu;
+   struct vsp1_dl_body_pool *pool;
 };
 
 static inline struct vsp1_clu *to_clu(struct v4l2_subdev *subdev)
diff --git a/drivers/media/platform/vsp1/vsp1_dl.c 
b/drivers/media/platform/vsp1/vsp1_dl.c
index 41ace89a585b..5074a83c0cf4 100644
--- a/drivers/media/platform/vsp1/vsp1_dl.c
+++ b/drivers/media/platform/vsp1/vsp1_dl.c
@@ -108,7 +108,7 @@ struct vsp1_dl_list {
struct vsp1_dl_header *header;
dma_addr_t dma;
 
-   struct vsp1_dl_body body0;
+   struct vsp1_dl_body *body0;
struct list_head bodies;
 
bool has_chain;
@@ -134,8 +134,6 @@ enum vsp1_dl_mode {
  * @queued: list queued to the 

[PATCH v8 7/8] media: vsp1: Adapt entities to configure into a body

[Kieran Bingham]

Currently the entities store their configurations into a display list.
Adapt this such that the code can be configured into a body directly,
allowing greater flexibility and control of the content.

All users of vsp1_dl_list_write() are removed in this process, thus it
too is removed.

A helper, vsp1_dl_list_get_body0() is provided to access the internal body0
from the display list.

Signed-off-by: Kieran Bingham 
Reviewed-by: Laurent Pinchart 
---
v8:
 - Fixed comment style and indentation
 - Supported UIF
 - Supported new configure_partition() functionality

v7:
 - Rebase
 - s/prepare/configure_stream/
 - s/configure/configure_frame/

 drivers/media/platform/vsp1/vsp1_brx.c| 22 ++--
 drivers/media/platform/vsp1/vsp1_clu.c| 23 ++---
 drivers/media/platform/vsp1/vsp1_dl.c | 12 ++-
 drivers/media/platform/vsp1/vsp1_dl.h |  2 +-
 drivers/media/platform/vsp1/vsp1_drm.c| 12 ---
 drivers/media/platform/vsp1/vsp1_entity.c | 21 ++--
 drivers/media/platform/vsp1/vsp1_entity.h | 16 +
 drivers/media/platform/vsp1/vsp1_hgo.c| 16 -
 drivers/media/platform/vsp1/vsp1_hgt.c| 18 +-
 drivers/media/platform/vsp1/vsp1_hsit.c   | 10 +++---
 drivers/media/platform/vsp1/vsp1_lif.c| 15 
 drivers/media/platform/vsp1/vsp1_lut.c| 23 ++---
 drivers/media/platform/vsp1/vsp1_pipe.c   |  4 +-
 drivers/media/platform/vsp1/vsp1_pipe.h   |  3 +-
 drivers/media/platform/vsp1/vsp1_rpf.c| 43 
 drivers/media/platform/vsp1/vsp1_sru.c| 14 
 drivers/media/platform/vsp1/vsp1_uds.c| 24 ++---
 drivers/media/platform/vsp1/vsp1_uds.h|  2 +-
 drivers/media/platform/vsp1/vsp1_uif.c| 21 ++--
 drivers/media/platform/vsp1/vsp1_video.c  | 16 ++---
 drivers/media/platform/vsp1/vsp1_wpf.c| 41 +++
 21 files changed, 188 insertions(+), 170 deletions(-)

diff --git a/drivers/media/platform/vsp1/vsp1_brx.c 
b/drivers/media/platform/vsp1/vsp1_brx.c
index 011edac5ebc1..359917b5d842 100644
--- a/drivers/media/platform/vsp1/vsp1_brx.c
+++ b/drivers/media/platform/vsp1/vsp1_brx.c
@@ -26,10 +26,10 @@
  * Device Access
  */
 
-static inline void vsp1_brx_write(struct vsp1_brx *brx, struct vsp1_dl_list 
*dl,
- u32 reg, u32 data)
+static inline void vsp1_brx_write(struct vsp1_brx *brx,
+ struct vsp1_dl_body *dlb, u32 reg, u32 data)
 {
-   vsp1_dl_list_write(dl, brx->base + reg, data);
+   vsp1_dl_body_write(dlb, brx->base + reg, data);
 }
 
 /* 
-
@@ -283,7 +283,7 @@ static const struct v4l2_subdev_ops brx_ops = {
 
 static void brx_configure_stream(struct vsp1_entity *entity,
 struct vsp1_pipeline *pipe,
-struct vsp1_dl_list *dl)
+struct vsp1_dl_body *dlb)
 {
struct vsp1_brx *brx = to_brx(>subdev);
struct v4l2_mbus_framefmt *format;
@@ -305,7 +305,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,
 * format at the pipeline output is premultiplied.
 */
flags = pipe->output ? pipe->output->format.flags : 0;
-   vsp1_brx_write(brx, dl, VI6_BRU_INCTRL,
+   vsp1_brx_write(brx, dlb, VI6_BRU_INCTRL,
   flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
   0 : VI6_BRU_INCTRL_NRM);
 
@@ -313,12 +313,12 @@ static void brx_configure_stream(struct vsp1_entity 
*entity,
 * Set the background position to cover the whole output image and
 * configure its color.
 */
-   vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_SIZE,
+   vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_SIZE,
   (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
   (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
-   vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_LOC, 0);
+   vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_LOC, 0);
 
-   vsp1_brx_write(brx, dl, VI6_BRU_VIRRPF_COL, brx->bgcolor |
+   vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_COL, brx->bgcolor |
   (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
 
/*
@@ -328,7 +328,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,
 * unit.
 */
if (entity->type == VSP1_ENTITY_BRU)
-   vsp1_brx_write(brx, dl, VI6_BRU_ROP,
+   vsp1_brx_write(brx, dlb, VI6_BRU_ROP,
   VI6_BRU_ROP_DSTSEL_BRUIN(1) |
   VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
   VI6_BRU_ROP_AROP(VI6_ROP_NOP));
@@ -370,7 +370,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,
if (!(entity->type == VSP1_ENTITY_BRU && i == 1))

[PATCH v8 0/8] vsp1: TLB optimisation and DL caching

[Kieran Bingham]

Each display list currently allocates an area of DMA memory to store register
settings for the VSP1 to process. Each of these allocations adds pressure to
the IPMMU TLB entries.

We can reduce the pressure by pre-allocating larger areas and dividing the area
across multiple bodies represented as a pool.

With this reconfiguration of bodies, we can adapt the configuration code to
separate out constant hardware configuration and cache it for re-use.

The patches provided in this series can be found at:
  git://git.kernel.org/pub/scm/linux/kernel/git/kbingham/rcar.git  
tags/vsp1/tlb-optimise/v8

Changelog:
--
v8:
 - Fix formatting and white space
 - Reword vsp1_dl_list_add_body() documentation
 - Update commit message on "Provide a body pool"
 - No longer pass unnecessary dlm->pool through vsp1_dl_list_alloc()
 - Add support for the new UIF entity
 - Fix comment location for clu_configure_stream()
 - Implement configure_partition separation
 - Rename video->pipe_config to video->stream_config

v7:
 - Rebased on to linux-media/master (v4.16-rc4)
 - Clean up the formatting of the vsp1_dl_list_add_body()
 - Fix formatting and white space
 -  s/prepare/configure_stream/
 -  s/configure/configure_frame/

v6:
 - Rebased on to linux-media/master (v4.16-rc1)
 - Removed DRM/UIF (DISCOM/ColorKey) updates

v5:
 - Rebased on to renesas-drivers-2018-01-09-v4.15-rc7 to fix conflicts
   with DRM and UIF updates on VSP1 driver

v4:
 - Rebased to v4.14
 * v4l: vsp1: Use reference counting for bodies
   - Fix up reference handling comments

 * v4l: vsp1: Provide a body pool
   - Provide comment explaining extra allocation on body pool
 highlighting area for optimisation later.

 * v4l: vsp1: Refactor display list configure operations
   - Fix up comment to describe yuv_mode caching rather than format

 * vsp1: Adapt entities to configure into a body
   - Rename vsp1_dl_list_get_body() to vsp1_dl_list_get_body0()

 * v4l: vsp1: Move video configuration to a cached dlb
   - Adjust pipe configured flag to be reset on resume rather than suspend
   - rename dl_child, dl_next

Testing:

The VSP unit tests have been run on this patch set with the following results:

--- Test loop 1 ---
- vsp-unit-test-.sh
Test Conditions:
  Platform  Renesas Salvator-X 2nd version board based on r8a7795 ES2.0+
  Kernel release4.17.0-rc1-arm64-renesas
  convert   /usr/bin/convert
  compare   /usr/bin/compare
  killall   /usr/bin/killall
  raw2rgbpnm/usr/bin/raw2rgbpnm
  stress/usr/bin/stress
  yavta /usr/bin/yavta
- vsp-unit-test-0001.sh
Testing WPF packing in RGB332: pass
Testing WPF packing in ARGB555: pass
Testing WPF packing in XRGB555: pass
Testing WPF packing in RGB565: pass
Testing WPF packing in BGR24: pass
Testing WPF packing in RGB24: pass
Testing WPF packing in ABGR32: pass
Testing WPF packing in ARGB32: pass
Testing WPF packing in XBGR32: pass
Testing WPF packing in XRGB32: pass
- vsp-unit-test-0002.sh
Testing WPF packing in NV12M: pass
Testing WPF packing in NV16M: pass
Testing WPF packing in NV21M: pass
Testing WPF packing in NV61M: pass
Testing WPF packing in UYVY: pass
Testing WPF packing in VYUY: skip
Testing WPF packing in YUV420M: pass
Testing WPF packing in YUV422M: pass
Testing WPF packing in YUV444M: pass
Testing WPF packing in YVU420M: pass
Testing WPF packing in YVU422M: pass
Testing WPF packing in YVU444M: pass
Testing WPF packing in YUYV: pass
Testing WPF packing in YVYU: pass
- vsp-unit-test-0003.sh
Testing scaling from 640x640 to 640x480 in RGB24: pass
Testing scaling from 1024x768 to 640x480 in RGB24: pass
Testing scaling from 640x480 to 1024x768 in RGB24: pass
Testing scaling from 640x640 to 640x480 in YUV444M: pass
Testing scaling from 1024x768 to 640x480 in YUV444M: pass
Testing scaling from 640x480 to 1024x768 in YUV444M: pass
- vsp-unit-test-0004.sh
Testing histogram in RGB24: pass
Testing histogram in YUV444M: pass
- vsp-unit-test-0005.sh
Testing RPF.0: pass
Testing RPF.1: pass
Testing RPF.2: pass
Testing RPF.3: pass
Testing RPF.4: pass
- vsp-unit-test-0006.sh
Testing invalid pipeline with no RPF: pass
Testing invalid pipeline with no WPF: pass
- vsp-unit-test-0007.sh
Testing BRU in RGB24 with 1 inputs: pass
Testing BRU in RGB24 with 2 inputs: pass
Testing BRU in RGB24 with 3 inputs: pass
Testing BRU in RGB24 with 4 inputs: pass
Testing BRU in RGB24 with 5 inputs: pass
Testing BRU in YUV444M with 1 inputs: pass
Testing BRU in YUV444M with 2 inputs: pass
Testing BRU in YUV444M with 3 inputs: pass
Testing BRU in YUV444M with 4 inputs: pass
Testing BRU in YUV444M with 5 inputs: pass
- vsp-unit-test-0008.sh
Test requires unavailable feature set `bru rpf.0 uds wpf.0': skipped
- vsp-unit-test-0009.sh
Test requires unavailable feature set `rpf.0 wpf.0 wpf.1': skipped
- vsp-unit-test-0010.sh
Testing CLU in RGB24 with zero configuration: pass
Testing CLU in RGB24 with identity configuration: pass
Testing CLU in RGB24 with wave 

[PATCH v8 3/8] media: vsp1: Provide a body pool

[Kieran Bingham]

Each display list allocates a body to store register values in a dma
accessible buffer from a dma_alloc_wc() allocation. Each of these
results in an entry in the IOMMU TLB, and a large number of display list
allocations adds pressure to this resource.

Reduce TLB pressure on the IPMMUs by allocating multiple display list
bodies in a single allocation, and providing these to the display list
through a 'body pool'. A pool can be allocated by the display list
manager or entities which require their own body allocations.

Signed-off-by: Kieran Bingham 

---
v8:
 - Update commit message
 - Fix comments and descriptions

v4:
 - Provide comment explaining extra allocation on body pool
   highlighting area for optimisation later.

v3:
 - s/fragment/body/, s/fragments/bodies/
 - qty -> num_bodies
 - indentation fix
 - s/vsp1_dl_body_pool_{alloc,free}/vsp1_dl_body_pool_{create,destroy}/'
 - Add kerneldoc to non-static functions

v2:
 - assign dlb->dma correctly

 drivers/media/platform/vsp1/vsp1_dl.c | 163 +++-
 drivers/media/platform/vsp1/vsp1_dl.h |   8 +-
 2 files changed, 171 insertions(+)

diff --git a/drivers/media/platform/vsp1/vsp1_dl.c 
b/drivers/media/platform/vsp1/vsp1_dl.c
index 51965c30dec2..41ace89a585b 100644
--- a/drivers/media/platform/vsp1/vsp1_dl.c
+++ b/drivers/media/platform/vsp1/vsp1_dl.c
@@ -41,6 +41,8 @@ struct vsp1_dl_entry {
 /**
  * struct vsp1_dl_body - Display list body
  * @list: entry in the display list list of bodies
+ * @free: entry in the pool free body list
+ * @pool: pool to which this body belongs
  * @vsp1: the VSP1 device
  * @entries: array of entries
  * @dma: DMA address of the entries
@@ -50,6 +52,9 @@ struct vsp1_dl_entry {
  */
 struct vsp1_dl_body {
struct list_head list;
+   struct list_head free;
+
+   struct vsp1_dl_body_pool *pool;
struct vsp1_device *vsp1;
 
struct vsp1_dl_entry *entries;
@@ -61,6 +66,30 @@ struct vsp1_dl_body {
 };
 
 /**
+ * struct vsp1_dl_body_pool - display list body pool
+ * @dma: DMA address of the entries
+ * @size: size of the full DMA memory pool in bytes
+ * @mem: CPU memory pointer for the pool
+ * @bodies: Array of DLB structures for the pool
+ * @free: List of free DLB entries
+ * @lock: Protects the free list
+ * @vsp1: the VSP1 device
+ */
+struct vsp1_dl_body_pool {
+   /* DMA allocation */
+   dma_addr_t dma;
+   size_t size;
+   void *mem;
+
+   /* Body management */
+   struct vsp1_dl_body *bodies;
+   struct list_head free;
+   spinlock_t lock;
+
+   struct vsp1_device *vsp1;
+};
+
+/**
  * struct vsp1_dl_list - Display list
  * @list: entry in the display list manager lists
  * @dlm: the display list manager
@@ -104,6 +133,7 @@ enum vsp1_dl_mode {
  * @active: list currently being processed (loaded) by hardware
  * @queued: list queued to the hardware (written to the DL registers)
  * @pending: list waiting to be queued to the hardware
+ * @pool: body pool for the display list bodies
  * @gc_work: bodies garbage collector work struct
  * @gc_bodies: array of display list bodies waiting to be freed
  */
@@ -119,6 +149,8 @@ struct vsp1_dl_manager {
struct vsp1_dl_list *queued;
struct vsp1_dl_list *pending;
 
+   struct vsp1_dl_body_pool *pool;
+
struct work_struct gc_work;
struct list_head gc_bodies;
 };
@@ -127,6 +159,137 @@ struct vsp1_dl_manager {
  * Display List Body Management
  */
 
+/**
+ * vsp1_dl_body_pool_create - Create a pool of bodies from a single allocation
+ * @vsp1: The VSP1 device
+ * @num_bodies: The number of bodies to allocate
+ * @num_entries: The maximum number of entries that a body can contain
+ * @extra_size: Extra allocation provided for the bodies
+ *
+ * Allocate a pool of display list bodies each with enough memory to contain 
the
+ * requested number of entries plus the @extra_size.
+ *
+ * Return a pointer to a pool on success or NULL if memory can't be allocated.
+ */
+struct vsp1_dl_body_pool *
+vsp1_dl_body_pool_create(struct vsp1_device *vsp1, unsigned int num_bodies,
+unsigned int num_entries, size_t extra_size)
+{
+   struct vsp1_dl_body_pool *pool;
+   size_t dlb_size;
+   unsigned int i;
+
+   pool = kzalloc(sizeof(*pool), GFP_KERNEL);
+   if (!pool)
+   return NULL;
+
+   pool->vsp1 = vsp1;
+
+   /*
+* TODO: 'extra_size' is only used by vsp1_dlm_create(), to allocate
+* extra memory for the display list header. We need only one header per
+* display list, not per display list body, thus this allocation is
+* extraneous and should be reworked in the future.
+*/
+   dlb_size = num_entries * sizeof(struct vsp1_dl_entry) + extra_size;
+   pool->size = dlb_size * num_bodies;
+
+   pool->bodies = kcalloc(num_bodies, sizeof(*pool->bodies), GFP_KERNEL);
+   if (!pool->bodies) {
+   kfree(pool);
+ 

[PATCH v8 2/8] media: vsp1: Protect bodies against overflow

[Kieran Bingham]

The body write function relies on the code never asking it to write more
than the entries available in the list.

Currently with each list body containing 256 entries, this is fine, but
we can reduce this number greatly saving memory. In preparation of this
add a level of protection to catch any buffer overflows.

Signed-off-by: Kieran Bingham 
Reviewed-by: Laurent Pinchart 

---

v3:
 - adapt for new 'body' terminology
 - simplify WARN_ON macro usage

 drivers/media/platform/vsp1/vsp1_dl.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/media/platform/vsp1/vsp1_dl.c 
b/drivers/media/platform/vsp1/vsp1_dl.c
index 083da4f05c20..51965c30dec2 100644
--- a/drivers/media/platform/vsp1/vsp1_dl.c
+++ b/drivers/media/platform/vsp1/vsp1_dl.c
@@ -46,6 +46,7 @@ struct vsp1_dl_entry {
  * @dma: DMA address of the entries
  * @size: size of the DMA memory in bytes
  * @num_entries: number of stored entries
+ * @max_entries: number of entries available
  */
 struct vsp1_dl_body {
struct list_head list;
@@ -56,6 +57,7 @@ struct vsp1_dl_body {
size_t size;
 
unsigned int num_entries;
+   unsigned int max_entries;
 };
 
 /**
@@ -138,6 +140,7 @@ static int vsp1_dl_body_init(struct vsp1_device *vsp1,
 
dlb->vsp1 = vsp1;
dlb->size = size;
+   dlb->max_entries = num_entries;
 
dlb->entries = dma_alloc_wc(vsp1->bus_master, dlb->size, >dma,
GFP_KERNEL);
@@ -219,6 +222,10 @@ void vsp1_dl_body_free(struct vsp1_dl_body *dlb)
  */
 void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data)
 {
+   if (WARN_ONCE(dlb->num_entries >= dlb->max_entries,
+ "DLB size exceeded (max %u)", dlb->max_entries))
+   return;
+
dlb->entries[dlb->num_entries].addr = reg;
dlb->entries[dlb->num_entries].data = data;
dlb->num_entries++;
-- 
git-series 0.9.1

[PATCH v8 1/8] media: vsp1: Reword uses of 'fragment' as 'body'

[Kieran Bingham]

Throughout the codebase, the term 'fragment' is used to represent a
display list body. This term duplicates the 'body' which is already in
use.

The datasheet references these objects as a body, therefore replace all
mentions of a fragment with a body, along with the corresponding
pluralised terms.

Signed-off-by: Kieran Bingham 
Reviewed-by: Laurent Pinchart 
---
Changes since v7:

- Fix indentation
- Reword vsp1_dl_list_add_body() documentation

Changes since v6:

- Clean up the formatting of the vsp1_dl_list_add_body()

 drivers/media/platform/vsp1/vsp1_clu.c |  10 +-
 drivers/media/platform/vsp1/vsp1_dl.c  | 111 --
 drivers/media/platform/vsp1/vsp1_dl.h  |  13 +--
 drivers/media/platform/vsp1/vsp1_lut.c |   8 +-
 4 files changed, 70 insertions(+), 72 deletions(-)

diff --git a/drivers/media/platform/vsp1/vsp1_clu.c 
b/drivers/media/platform/vsp1/vsp1_clu.c
index 96a448e1504c..ebfbb915dcdc 100644
--- a/drivers/media/platform/vsp1/vsp1_clu.c
+++ b/drivers/media/platform/vsp1/vsp1_clu.c
@@ -43,19 +43,19 @@ static int clu_set_table(struct vsp1_clu *clu, struct 
v4l2_ctrl *ctrl)
struct vsp1_dl_body *dlb;
unsigned int i;
 
-   dlb = vsp1_dl_fragment_alloc(clu->entity.vsp1, 1 + 17 * 17 * 17);
+   dlb = vsp1_dl_body_alloc(clu->entity.vsp1, 1 + 17 * 17 * 17);
if (!dlb)
return -ENOMEM;
 
-   vsp1_dl_fragment_write(dlb, VI6_CLU_ADDR, 0);
+   vsp1_dl_body_write(dlb, VI6_CLU_ADDR, 0);
for (i = 0; i < 17 * 17 * 17; ++i)
-   vsp1_dl_fragment_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
+   vsp1_dl_body_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
 
spin_lock_irq(>lock);
swap(clu->clu, dlb);
spin_unlock_irq(>lock);
 
-   vsp1_dl_fragment_free(dlb);
+   vsp1_dl_body_free(dlb);
return 0;
 }
 
@@ -211,7 +211,7 @@ static void clu_configure(struct vsp1_entity *entity,
spin_unlock_irqrestore(>lock, flags);
 
if (dlb)
-   vsp1_dl_list_add_fragment(dl, dlb);
+   vsp1_dl_list_add_body(dl, dlb);
break;
}
 }
diff --git a/drivers/media/platform/vsp1/vsp1_dl.c 
b/drivers/media/platform/vsp1/vsp1_dl.c
index 801dea475740..083da4f05c20 100644
--- a/drivers/media/platform/vsp1/vsp1_dl.c
+++ b/drivers/media/platform/vsp1/vsp1_dl.c
@@ -65,7 +65,7 @@ struct vsp1_dl_body {
  * @header: display list header, NULL for headerless lists
  * @dma: DMA address for the header
  * @body0: first display list body
- * @fragments: list of extra display list bodies
+ * @bodies: list of extra display list bodies
  * @has_chain: if true, indicates that there's a partition chain
  * @chain: entry in the display list partition chain
  * @internal: whether the display list is used for internal purpose
@@ -78,7 +78,7 @@ struct vsp1_dl_list {
dma_addr_t dma;
 
struct vsp1_dl_body body0;
-   struct list_head fragments;
+   struct list_head bodies;
 
bool has_chain;
struct list_head chain;
@@ -97,13 +97,13 @@ enum vsp1_dl_mode {
  * @mode: display list operation mode (header or headerless)
  * @singleshot: execute the display list in single-shot mode
  * @vsp1: the VSP1 device
- * @lock: protects the free, active, queued, pending and gc_fragments lists
+ * @lock: protects the free, active, queued, pending and gc_bodies lists
  * @free: array of all free display lists
  * @active: list currently being processed (loaded) by hardware
  * @queued: list queued to the hardware (written to the DL registers)
  * @pending: list waiting to be queued to the hardware
- * @gc_work: fragments garbage collector work struct
- * @gc_fragments: array of display list fragments waiting to be freed
+ * @gc_work: bodies garbage collector work struct
+ * @gc_bodies: array of display list bodies waiting to be freed
  */
 struct vsp1_dl_manager {
unsigned int index;
@@ -118,7 +118,7 @@ struct vsp1_dl_manager {
struct vsp1_dl_list *pending;
 
struct work_struct gc_work;
-   struct list_head gc_fragments;
+   struct list_head gc_bodies;
 };
 
 /* 
-
@@ -156,18 +156,17 @@ static void vsp1_dl_body_cleanup(struct vsp1_dl_body *dlb)
 }
 
 /**
- * vsp1_dl_fragment_alloc - Allocate a display list fragment
+ * vsp1_dl_body_alloc - Allocate a display list body
  * @vsp1: The VSP1 device
- * @num_entries: The maximum number of entries that the fragment can contain
+ * @num_entries: The maximum number of entries that the body can contain
  *
- * Allocate a display list fragment with enough memory to contain the requested
+ * Allocate a display list body with enough memory to contain the requested
  * number of entries.
  *
- * Return a pointer to a fragment on success or NULL if memory can't be
- * allocated.
+ * 

[PATCH v8 8/8] media: vsp1: Move video configuration to a cached dlb

[Kieran Bingham]

We are now able to configure a pipeline directly into a local display
list body. Take advantage of this fact, and create a cacheable body to
store the configuration of the pipeline in the video object.

vsp1_video_pipeline_run() is now the last user of the pipe->dl object.
Convert this function to use the cached video->config body and obtain a
local display list reference.

Attach the video->config body to the display list when needed before
committing to hardware.

The pipe object is marked as un-configured when resuming from a suspend.
This ensures that when the hardware is reset - our cached configuration
will be re-attached to the next committed DL.

Our video DL usage now looks like the below output:

dl->body0 contains our disposable runtime configuration. Max 41.
dl_child->body0 is our partition specific configuration. Max 12.
dl->bodies shows our constant configuration and LUTs.

  These two are LUT/CLU:
 * dl->bodies[x]->num_entries 256 / max 256
 * dl->bodies[x]->num_entries 4914 / max 4914

Which shows that our 'constant' configuration cache is currently
utilised to a maximum of 64 entries.

trace-cmd report | \
grep max | sed 's/.*vsp1_dl_list_commit://g' | sort | uniq;

  dl->body0->num_entries 13 / max 128
  dl->body0->num_entries 14 / max 128
  dl->body0->num_entries 16 / max 128
  dl->body0->num_entries 20 / max 128
  dl->body0->num_entries 27 / max 128
  dl->body0->num_entries 34 / max 128
  dl->body0->num_entries 41 / max 128
  dl_child->body0->num_entries 10 / max 128
  dl_child->body0->num_entries 12 / max 128
  dl->bodies[x]->num_entries 15 / max 128
  dl->bodies[x]->num_entries 16 / max 128
  dl->bodies[x]->num_entries 17 / max 128
  dl->bodies[x]->num_entries 18 / max 128
  dl->bodies[x]->num_entries 20 / max 128
  dl->bodies[x]->num_entries 21 / max 128
  dl->bodies[x]->num_entries 256 / max 256
  dl->bodies[x]->num_entries 31 / max 128
  dl->bodies[x]->num_entries 32 / max 128
  dl->bodies[x]->num_entries 39 / max 128
  dl->bodies[x]->num_entries 40 / max 128
  dl->bodies[x]->num_entries 47 / max 128
  dl->bodies[x]->num_entries 48 / max 128
  dl->bodies[x]->num_entries 4914 / max 4914
  dl->bodies[x]->num_entries 55 / max 128
  dl->bodies[x]->num_entries 56 / max 128
  dl->bodies[x]->num_entries 63 / max 128
  dl->bodies[x]->num_entries 64 / max 128

Signed-off-by: Kieran Bingham 
---
v8:
 - Fix comments
 - Rename video->pipe_config -> video->stream_config

v3:
 - 's/fragment/body/', 's/fragments/bodies/'
 - video dlb cache allocation increased from 2 to 3 dlbs

v4:
 - Adjust pipe configured flag to be reset on resume rather than suspend
 - rename dl_child, dl_next

 drivers/media/platform/vsp1/vsp1_pipe.c  |  9 +++-
 drivers/media/platform/vsp1/vsp1_pipe.h  |  5 +--
 drivers/media/platform/vsp1/vsp1_video.c | 72 +++--
 drivers/media/platform/vsp1/vsp1_video.h |  2 +-
 4 files changed, 59 insertions(+), 29 deletions(-)

diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c 
b/drivers/media/platform/vsp1/vsp1_pipe.c
index d06ffa01027c..70af6c9fc97f 100644
--- a/drivers/media/platform/vsp1/vsp1_pipe.c
+++ b/drivers/media/platform/vsp1/vsp1_pipe.c
@@ -230,6 +230,7 @@ void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
   VI6_CMD_STRCMD);
pipe->state = VSP1_PIPELINE_RUNNING;
+   pipe->configured = true;
}
 
pipe->buffers_ready = 0;
@@ -295,6 +296,8 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
 
v4l2_subdev_call(>output->entity.subdev, video, s_stream, 0);
 
+   pipe->configured = false;
+
return ret;
 }
 
@@ -451,6 +454,12 @@ void vsp1_pipelines_resume(struct vsp1_device *vsp1)
continue;
 
spin_lock_irqsave(>irqlock, flags);
+   /*
+* The hardware may have been reset during a suspend and will
+* need a full reconfiguration.
+*/
+   pipe->configured = false;
+
if (vsp1_pipeline_ready(pipe))
vsp1_pipeline_run(pipe);
spin_unlock_irqrestore(>irqlock, flags);
diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h 
b/drivers/media/platform/vsp1/vsp1_pipe.h
index e00010693eef..7c8b30018aac 100644
--- a/drivers/media/platform/vsp1/vsp1_pipe.h
+++ b/drivers/media/platform/vsp1/vsp1_pipe.h
@@ -86,6 +86,7 @@ struct vsp1_partition {
  * @irqlock: protects the pipeline state
  * @state: current state
  * @wq: wait queue to wait for state change completion
+ * @configured: flag determining if the hardware has run since reset
  * @frame_end: frame end interrupt handler
  * @lock: protects the pipeline use count and stream count
  * @kref: pipeline reference count
@@ -102,7 +103,6 @@ struct vsp1_partition {
  * @uds: UDS entity, if present
  * @uds_input: entity at the input of the UDS, if the UDS is 

[PATCH v8 6/8] media: vsp1: Refactor display list configure operations

[Kieran Bingham]

The entities provide a single .configure operation which configures the
object into the target display list, based on the vsp1_entity_params
selection.

Split the configure function into three parts, '.configure_stream()',
'.configure_frame()', and '.configure_partition()' to facilitate
splitting the configuration of each parameter class into separate
display list bodies.

Signed-off-by: Kieran Bingham 

---
The checkpatch warning:

WARNING: function definition argument 'struct vsp1_dl_list *' should
also have an identifier name

has been ignored to match the existing code style.

v8:
 - Add support for the UIF
 - Remove unrelated whitespace change
 - Fix comment location for clu_configure_stream()
 - Update configure documentations
 - Implement configure_partition separation.

v7
 - Fix formatting and white space
 - s/prepare/configure_stream/
 - s/configure/configure_frame/

 drivers/media/platform/vsp1/vsp1_brx.c|  12 +-
 drivers/media/platform/vsp1/vsp1_clu.c|  77 ++
 drivers/media/platform/vsp1/vsp1_drm.c|  12 +-
 drivers/media/platform/vsp1/vsp1_entity.c |  24 ++-
 drivers/media/platform/vsp1/vsp1_entity.h |  39 +--
 drivers/media/platform/vsp1/vsp1_hgo.c|  12 +-
 drivers/media/platform/vsp1/vsp1_hgt.c|  12 +-
 drivers/media/platform/vsp1/vsp1_hsit.c   |  12 +-
 drivers/media/platform/vsp1/vsp1_lif.c|  12 +-
 drivers/media/platform/vsp1/vsp1_lut.c|  47 +---
 drivers/media/platform/vsp1/vsp1_rpf.c| 168 ++---
 drivers/media/platform/vsp1/vsp1_sru.c|  12 +-
 drivers/media/platform/vsp1/vsp1_uds.c|  56 ++--
 drivers/media/platform/vsp1/vsp1_uif.c|  16 +-
 drivers/media/platform/vsp1/vsp1_video.c  |  28 +--
 drivers/media/platform/vsp1/vsp1_wpf.c| 303 ---
 16 files changed, 422 insertions(+), 420 deletions(-)

diff --git a/drivers/media/platform/vsp1/vsp1_brx.c 
b/drivers/media/platform/vsp1/vsp1_brx.c
index 3beec18fd863..011edac5ebc1 100644
--- a/drivers/media/platform/vsp1/vsp1_brx.c
+++ b/drivers/media/platform/vsp1/vsp1_brx.c
@@ -281,19 +281,15 @@ static const struct v4l2_subdev_ops brx_ops = {
  * VSP1 Entity Operations
  */
 
-static void brx_configure(struct vsp1_entity *entity,
- struct vsp1_pipeline *pipe,
- struct vsp1_dl_list *dl,
- enum vsp1_entity_params params)
+static void brx_configure_stream(struct vsp1_entity *entity,
+struct vsp1_pipeline *pipe,
+struct vsp1_dl_list *dl)
 {
struct vsp1_brx *brx = to_brx(>subdev);
struct v4l2_mbus_framefmt *format;
unsigned int flags;
unsigned int i;
 
-   if (params != VSP1_ENTITY_PARAMS_INIT)
-   return;
-
format = vsp1_entity_get_pad_format(>entity, brx->entity.config,
brx->entity.source_pad);
 
@@ -400,7 +396,7 @@ static void brx_configure(struct vsp1_entity *entity,
 }
 
 static const struct vsp1_entity_operations brx_entity_ops = {
-   .configure = brx_configure,
+   .configure_stream = brx_configure_stream,
 };
 
 /* 
-
diff --git a/drivers/media/platform/vsp1/vsp1_clu.c 
b/drivers/media/platform/vsp1/vsp1_clu.c
index ea83f1b7d125..0a978980d447 100644
--- a/drivers/media/platform/vsp1/vsp1_clu.c
+++ b/drivers/media/platform/vsp1/vsp1_clu.c
@@ -168,58 +168,50 @@ static const struct v4l2_subdev_ops clu_ops = {
 /* 
-
  * VSP1 Entity Operations
  */
+static void clu_configure_stream(struct vsp1_entity *entity,
+struct vsp1_pipeline *pipe,
+struct vsp1_dl_list *dl)
+{
+   struct vsp1_clu *clu = to_clu(>subdev);
+   struct v4l2_mbus_framefmt *format;
 
-static void clu_configure(struct vsp1_entity *entity,
- struct vsp1_pipeline *pipe,
- struct vsp1_dl_list *dl,
- enum vsp1_entity_params params)
+   /*
+* The yuv_mode can't be changed during streaming. Cache it internally
+* for future runtime configuration calls.
+*/
+   format = vsp1_entity_get_pad_format(>entity,
+   clu->entity.config,
+   CLU_PAD_SINK);
+   clu->yuv_mode = format->code == MEDIA_BUS_FMT_AYUV8_1X32;
+}
+
+static void clu_configure_frame(struct vsp1_entity *entity,
+   struct vsp1_pipeline *pipe,
+   struct vsp1_dl_list *dl)
 {
struct vsp1_clu *clu = to_clu(>subdev);
struct vsp1_dl_body *dlb;
unsigned long flags;
u32 ctrl = VI6_CLU_CTRL_AAI | VI6_CLU_CTRL_MVS | VI6_CLU_CTRL_EN;
 
-   switch (params) {
-   case 

[PATCH v8 5/8] media: vsp1: Use reference counting for bodies

[Kieran Bingham]

Extend the display list body with a reference count, allowing bodies to
be kept as long as a reference is maintained. This provides the ability
to keep a cached copy of bodies which will not change, so that they can
be re-applied to multiple display lists.

Signed-off-by: Kieran Bingham 
Reviewed-by: Laurent Pinchart 
---
This could be squashed into the body update code, but it's not a
straightforward squash as the refcounts will affect both:
  v4l: vsp1: Provide a body pool
and
  v4l: vsp1: Convert display lists to use new body pool
therefore, I have kept this separate to prevent breaking bisectability
of the vsp-tests.

v3:
 - 's/fragment/body/'

v4:
 - Fix up reference handling comments.

Changes since v7:

- Fix comment style

 drivers/media/platform/vsp1/vsp1_clu.c |  7 ++-
 drivers/media/platform/vsp1/vsp1_dl.c  | 16 ++--
 drivers/media/platform/vsp1/vsp1_lut.c |  7 ++-
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/vsp1/vsp1_clu.c 
b/drivers/media/platform/vsp1/vsp1_clu.c
index 8efa12f5e53f..ea83f1b7d125 100644
--- a/drivers/media/platform/vsp1/vsp1_clu.c
+++ b/drivers/media/platform/vsp1/vsp1_clu.c
@@ -212,8 +212,13 @@ static void clu_configure(struct vsp1_entity *entity,
clu->clu = NULL;
spin_unlock_irqrestore(>lock, flags);
 
-   if (dlb)
+   if (dlb) {
vsp1_dl_list_add_body(dl, dlb);
+
+   /* Release our local reference. */
+   vsp1_dl_body_put(dlb);
+   }
+
break;
}
 }
diff --git a/drivers/media/platform/vsp1/vsp1_dl.c 
b/drivers/media/platform/vsp1/vsp1_dl.c
index 5074a83c0cf4..e07ed3a2acda 100644
--- a/drivers/media/platform/vsp1/vsp1_dl.c
+++ b/drivers/media/platform/vsp1/vsp1_dl.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -54,6 +55,8 @@ struct vsp1_dl_body {
struct list_head list;
struct list_head free;
 
+   refcount_t refcnt;
+
struct vsp1_dl_body_pool *pool;
struct vsp1_device *vsp1;
 
@@ -258,6 +261,7 @@ struct vsp1_dl_body *vsp1_dl_body_get(struct 
vsp1_dl_body_pool *pool)
if (!list_empty(>free)) {
dlb = list_first_entry(>free, struct vsp1_dl_body, free);
list_del(>free);
+   refcount_set(>refcnt, 1);
}
 
spin_unlock_irqrestore(>lock, flags);
@@ -278,6 +282,9 @@ void vsp1_dl_body_put(struct vsp1_dl_body *dlb)
if (!dlb)
return;
 
+   if (!refcount_dec_and_test(>refcnt))
+   return;
+
dlb->num_entries = 0;
 
spin_lock_irqsave(>pool->lock, flags);
@@ -463,8 +470,11 @@ void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, 
u32 data)
  * which bodies are added.
  *
  * Adding a body to a display list passes ownership of the body to the list. 
The
- * caller must not touch the body after this call, and must not release it
- * explicitly with vsp1_dl_body_put().
+ * caller retains its reference to the fragment when adding it to the display
+ * list, but is not allowed to add new entries to the body.
+ *
+ * The reference must be explicitly released by a call to vsp1_dl_body_put()
+ * when the body isn't needed anymore.
  *
  * Additional bodies are only usable for display lists in header mode.
  * Attempting to add a body to a header-less display list will return an error.
@@ -475,6 +485,8 @@ int vsp1_dl_list_add_body(struct vsp1_dl_list *dl, struct 
vsp1_dl_body *dlb)
if (dl->dlm->mode != VSP1_DL_MODE_HEADER)
return -EINVAL;
 
+   refcount_inc(>refcnt);
+
list_add_tail(>list, >bodies);
 
return 0;
diff --git a/drivers/media/platform/vsp1/vsp1_lut.c 
b/drivers/media/platform/vsp1/vsp1_lut.c
index 6b358617ce15..b3ea90172439 100644
--- a/drivers/media/platform/vsp1/vsp1_lut.c
+++ b/drivers/media/platform/vsp1/vsp1_lut.c
@@ -168,8 +168,13 @@ static void lut_configure(struct vsp1_entity *entity,
lut->lut = NULL;
spin_unlock_irqrestore(>lock, flags);
 
-   if (dlb)
+   if (dlb) {
vsp1_dl_list_add_body(dl, dlb);
+
+   /* Release our local reference. */
+   vsp1_dl_body_put(dlb);
+   }
+
break;
}
 }
-- 
git-series 0.9.1

[PATCH v8 01/12] ARM: Allow this header to be included by assembly files

[Mylène Josserand]

From: Doug Berger 

The constants defined in this file are equally useful in assembly and C
source files. The arm64 architecture version of this file allows
inclusion in both assembly and C source files, so this this commit adds
that capability to the arm architecture version so that the constants
don't need to be defined in multiple places.

Signed-off-by: Doug Berger 
Signed-off-by: Florian Fainelli 
Signed-off-by: Mylène Josserand 
---
 arch/arm/include/asm/cputype.h | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb546425da8a..e7632f536633 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,9 +2,6 @@
 #ifndef __ASM_ARM_CPUTYPE_H
 #define __ASM_ARM_CPUTYPE_H
 
-#include 
-#include 
-
 #define CPUID_ID   0
 #define CPUID_CACHETYPE1
 #define CPUID_TCM  2
@@ -98,6 +95,11 @@
 /* Qualcomm implemented cores */
 #define ARM_CPU_PART_SCORPION  0x510002d0
 
+#ifndef __ASSEMBLY__
+
+#include 
+#include 
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -326,4 +328,6 @@ static inline int __attribute_const__ 
cpuid_feature_extract_field(u32 features,
 #define cpuid_feature_extract(reg, field) \
cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 
+#endif /* __ASSEMBLY__ */
+
 #endif
-- 
2.11.0

[PATCH v8 03/12] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

[Mylène Josserand]

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 379981389eea..a50ccb475de8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
};
};
 
+   cpucfg@170 {
+   compatible = "allwinner,sun8i-a83t-cpucfg";
+   reg = <0x0170 0x400>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v8 04/12] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Mylène Josserand]

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a50ccb475de8..53ace066b7dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -938,6 +938,11 @@
#reset-cells = <1>;
};
 
+   r_cpucfg@1f01c00 {
+   compatible = "allwinner,sun8i-a83t-r-cpucfg";
+   reg = <0x1f01c00 0x400>;
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

[PATCH v8 02/12] ARM: sunxi: smp: Move assembly code into a file

[Mylène Josserand]

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/Makefile  |  2 +-
 arch/arm/mach-sunxi/headsmp.S | 80 +
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++
 3 files changed, 85 insertions(+), 79 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..71429aa85143 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,5 @@
 CFLAGS_mc_smp.o+= -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index ..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai 
+ * Mylène Josserand 
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+   .arch   armv7-a
+   /*
+* Enable cluster-level coherency, in preparation for turning on the 
MMU.
+*
+* Also enable regional clock gating and L2 data latency settings for
+* Cortex-A15. These settings are from the vendor kernel.
+*/
+   mrc p15, 0, r1, c0, c0, 0
+   movwr2, #(ARM_CPU_PART_MASK & 0x)
+   movtr2, #(ARM_CPU_PART_MASK >> 16)
+   and r1, r1, r2
+   movwr2, #(ARM_CPU_PART_CORTEX_A15 & 0x)
+   movtr2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+   cmp r1, r2
+   bne not_a15
+
+   /* The following is Cortex-A15 specific */
+
+   /* ACTLR2: Enable CPU regional clock gates */
+   mrc p15, 1, r1, c15, c0, 4
+   orr r1, r1, #(0x1 << 31)
+   mcr p15, 1, r1, c15, c0, 4
+
+   /* L2ACTLR */
+   mrc p15, 1, r1, c15, c0, 0
+   /* Enable L2, GIC, and Timer regional clock gates */
+   orr r1, r1, #(0x1 << 26)
+   /* Disable clean/evict from being pushed to external */
+   orr r1, r1, #(0x1<<3)
+   mcr p15, 1, r1, c15, c0, 0
+
+   /* L2CTRL: L2 data RAM latency */
+   mrc p15, 1, r1, c9, c0, 2
+   bic r1, r1, #(0x7 << 0)
+   orr r1, r1, #(0x3 << 0)
+   mcr p15, 1, r1, c9, c0, 2
+
+   /* End of Cortex-A15 specific setup */
+   not_a15:
+
+   /* Get value of sunxi_mc_smp_first_comer */
+   adr r1, first
+   ldr r0, [r1]
+   ldr r0, [r1, r0]
+
+   /* Skip cci_enable_port_for_self if not first comer */
+   cmp r0, #0
+   bxeqlr
+   b   cci_enable_port_for_self
+
+   .align 2
+   first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-   asm volatile (
-   "mrcp15, 0, r1, c0, c0, 0\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0x) "\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-   "andr1, r1, r2\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0x) 
"\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
- 

[PATCH v8 06/12] ARM: smp: Add initialization of CNTVOFF

[Mylène Josserand]

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---
 arch/arm/common/Makefile  |  1 +
 arch/arm/common/secure_cntvoff.S  | 31 +++
 arch/arm/include/asm/secure_cntvoff.h |  8 
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)   += dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
 obj-$(CONFIG_SHARP_PARAM)  += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)  += scoop.o
+obj-$(CONFIG_SMP)  += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o 
vlock.o
 CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index ..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include 
+#include 
+
+ENTRY(secure_cntvoff_init)
+   .arch   armv7-a
+   /*
+* CNTVOFF has to be initialized either from non-secure Hypervisor
+* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+* then it should be handled by the secure code
+*/
+   cps #MON_MODE
+   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
+   orr r0, r1, #1
+   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
+   isb
+   mov r0, #0
+   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+   isb
+   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
+   isb
+   cps #SVC_MODE
+   ret lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h 
b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index ..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

[PATCH v8 05/12] ARM: dts: sun8i: a83t: Add CCI-400 node

[Mylène Josserand]

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53ace066b7dc..0669b8dc499d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <0>;
};
 
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <1>;
};
 
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <2>;
};
 
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <3>;
};
 
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x100>;
};
 
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x101>;
};
 
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x102>;
};
 
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x0170 0x400>;
};
 
+   cci@179 {
+   compatible = "arm,cci-400";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0179 0x1>;
+   ranges = <0x0 0x0179 0x1>;
+
+   cci_control0: slave-if@4000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x4000 0x1000>;
+   };
+
+   cci_control1: slave-if@5000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x5000 0x1000>;
+   };
+
+   pmu@9000 {
+   compatible = "arm,cci-400-pmu,r1";
+   reg = <0x9000 0x5000>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v8 07/12] ARM: sunxi: Add initialization of CNTVOFF

[Mylène Josserand]

Add the initialization of CNTVOFF for sun8i-a83t.

For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because of that, this function can't be called in SMP's early_initcall
function which is called after timer's init.

For secondary CPUs, add this function into secondary_startup
assembly entry.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/headsmp.S |  1 +
 arch/arm/mach-sunxi/sunxi.c   | 20 +++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
index 37dc772701f3..32d76be98541 100644
--- a/arch/arm/mach-sunxi/headsmp.S
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
 
 ENTRY(sunxi_mc_smp_secondary_startup)
bl  sunxi_mc_smp_cluster_cache_enable
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(sunxi_mc_smp_secondary_startup)
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..2770a31a9278 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 
 static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
-   "allwinner,sun8i-a83t",
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.dt_compat  = sun8i_board_dt_compat,
 MACHINE_END
 
+void __init sun8i_a83t_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+   secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+   "allwinner,sun8i-a83t",
+   NULL,
+};
+
+DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")
+   .init_early = sun8i_a83t_cntvoff_init,
+   .init_time  = sun6i_timer_init,
+   .dt_compat  = sun8i_a83t_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
"allwinner,sun9i-a80",
NULL,
-- 
2.11.0

[PATCH v8 08/12] ARM: sun9i: smp: Rename clusters's power-off

[Mylène Josserand]

To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
/* clear cluster power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
/* gate cluster power */
pr_debug("%s: gate cluster power\n", __func__);
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
-- 
2.11.0

[PATCH v8 12/12] ARM: shmobile: Convert file to use cntvoff

[Mylène Josserand]

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---
 arch/arm/mach-shmobile/common.h  |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 43c1ac696274..2109f123bdfb 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S 
b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include 
 #include 
 
-ENTRY(shmobile_init_cntvoff)
-   /*
-* CNTVOFF has to be initialized either from non-secure Hypervisor
-* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-* then it should be handled by the secure code
-*/
-   cps #MON_MODE
-   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
-   orr r0, r1, #1
-   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
-   instr_sync
-   mov r0, #0
-   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
-   instr_sync
-   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
-   instr_sync
-   cps #SVC_MODE
-   ret lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-   bl  shmobile_init_cntvoff
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
 
-   shmobile_init_cntvoff();
+   secure_cntvoff_init();
 
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

[PATCH v8 09/12] ARM: sun9i: smp: Add is_a83t field

[Mylène Josserand]

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/mc_smp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..fc10e3a3268f 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static bool is_a83t;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
const char *enable_method;
int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+   bool is_a83t;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -697,6 +699,8 @@ static int __init sunxi_mc_smp_init(void)
break;
}
 
+   is_a83t = sunxi_mc_smp_data[i].is_a83t;
+
of_node_put(node);
if (ret)
return -ENODEV;
-- 
2.11.0

[PATCH v8 10/12] ARM: sun8i: smp: Add support for A83T

[Mylène Josserand]

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/Kconfig  |   2 +-
 arch/arm/mach-sunxi/mc_smp.c | 151 ++-
 2 files changed, 137 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
bool
depends on SMP
-   default MACH_SUN9I
+   default MACH_SUN9I || MACH_SUN8I
select ARM_CCI400_PORT_CTRL
select ARM_CPU_SUSPEND
 
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index fc10e3a3268f..b4037b603897 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST  BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)   BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I   BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)   BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC00xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC10x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   /* assert cpu power-on reset */
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 0)
+   cpu = 4;
+   }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
+   /* Handle A83T bit swap */
+   if (is_a83t) {
+   if (cpu == 4)
+   cpu = 0;
+   }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_a83t) {
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if (cluster >= SUNXI_NR_CLUSTERS)
return -EINVAL;
 
+   /* For 

[PATCH v8 11/12] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

[Mylène Josserand]

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 0669b8dc499d..2be23d600957 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
 
@@ -75,6 +76,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
 
@@ -83,6 +85,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
 
@@ -91,6 +94,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
 
@@ -101,6 +105,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
 
@@ -109,6 +114,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
 
@@ -117,6 +123,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
 
@@ -125,6 +132,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
-- 
2.11.0

[PATCH v8 00/12] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V8 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files that I included in my series (patch 01).

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes from v7:
- Add the patch of Doug Berger in my series.
- Rename the machine name to start secure_cntvoff into "sun8i-a83t",
according to Maxime's review.
- Change the type of is_a83t field from integer into boolean.

Changes from v6:
- Correct the commit log on patch 07 according to Sergei Shtylyov's
review.
- Rename the field "is_sun8i" into "is_a83t".
- Add all Tested-by and Reviewed-by from previous version.

Changes from v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes from v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.

Changes from v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes from v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes from v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
patch 05).

Doug Berger (1):
  ARM: Allow this header to be included by assembly files

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: sun9i: smp: Add is_a83t field
  ARM: sun8i: smp: Add support for A83T
  

Re: [PATCH v2 0/5] Add R8A77980 PCIe support & some driver cleanups

[Lorenzo Pieralisi]

On Tue, May 01, 2018 at 07:55:53AM +0200, Simon Horman wrote:
> On Sun, Apr 08, 2018 at 08:57:13PM +0300, Sergei Shtylyov wrote:
> > Hello!
> > 
> > Here's a set of 5 patches against the 'pci/rcar' branch of Lorenzo 
> > Pieralisi's
> > 'pci.git' repo. These are the changes needed for better R-Car gen3 support
> > (namely for R8A77980 support) plus some PCIe driver re-factoring done in
> > the process...
> > 
> > [1/5] pcie-rcar: poll PHYRDY in rcar_pcie_hw_init()
> > [2/5] pcie-rcar: remove PHYRDY polling from rcar_pcie_hw_init_h1()
> > [3/5] pcie-rcar: add R-Car gen3 PHY support
> > [4/5] pcie-rcar: factor out rcar_pcie_hw_init() call
> > [5/5] DT: pci: rcar-pci: document R8A77980 bindings
> 
> Reviewed-by: Simon Horman 

Sergei, would you mind rebasing this series against my pci/rcar
branch please ? I will apply it then.

Thanks,
Lorenzo

Re: [PATCH V5] PCI: rcar: Use runtime PM to control controller clock

[Lorenzo Pieralisi]

On Fri, Apr 13, 2018 at 02:48:19PM +0200, Simon Horman wrote:
> On Tue, Apr 10, 2018 at 06:17:04PM +0200, Marek Vasut wrote:
> > On 04/10/2018 05:28 PM, Geert Uytterhoeven wrote:
> 
> ...
> 
> > >>> rcar_pcie_get_resources() is called while the device is
> > >>> runtime-enabled/resumed,
> > >>> pci_free_resource_list() is called while the device is runtime-disabled.
> > 
> > rcar_pcie_get_resources() is NOT a pair function for
> > pci_free_resource_list() . rcar_pcie_parse_request_of_pci_ranges() is a
> > pair function for pci_free_resource_list().
> > 
> > rcar_pcie_parse_request_of_pci_ranges() calls
> > of_pci_get_host_bridge_resources() internally, so every single function
> > called after successful call of rcar_pcie_parse_request_of_pci_ranges()
> > must call pci_free_resource_list().
> > 
> > Both of_pci_get_host_bridge_resources() and pci_free_resource_list() are
> > called with runtime PM disabled.
> > 
> > The naming of the functions is confusing though.
> 
> Hi,
> 
> thanks everyone for their efforts in preparing/reviewing this patch.
> 
> It seems there are some differences of opinion on how best to handle the
> error paths but unlike earlier versions this one seems correct to me. If
> that turns out to be false we can address it. But I don't think its likely
> things will be enhanced by continuing this review.
> 
> Lorenzo, please consider taking this patch in its current form.
> 
> Reviewed-by: Simon Horman 

Applied to pci/rcar for v4.18, thanks.

Lorenzo

Re: [PATCH V3] PCI: rcar: Clean up the macros

[Lorenzo Pieralisi]

On Tue, May 01, 2018 at 07:53:19AM +0200, Simon Horman wrote:
> On Sun, Apr 08, 2018 at 08:04:31PM +0200, Marek Vasut wrote:
> > This patch replaces the (1 << n) with BIT(n) and cleans up whitespace,
> > no functional change.
> > 
> > Signed-off-by: Marek Vasut 
> > Cc: Geert Uytterhoeven 
> > Cc: Phil Edworthy 
> > Cc: Simon Horman 
> > Cc: Wolfram Sang 
> > Cc: linux-renesas-soc@vger.kernel.org
> > Reviewed-by: Niklas S??derlund 
> 
> Marek, thanks for your patch.
> 
> Lorenzo, this seems pretty well baked.
> Could you consider applying it?
> 
> Reviewed-by: Simon Horman 

Applied to pci/rcar for v4.18, thanks.

Lorenzo

Re: igt trouble with planes shared between multiple CRTCs (Re: [PATCH v2 0/8] R-Car DU: Support CRC calculation)

[Maarten Lankhorst]

Hey,

Op 30-04-18 om 16:56 schreef Daniel Vetter:
> On Mon, Apr 30, 2018 at 04:55:24PM +0200, Daniel Vetter wrote:
>> On Sat, Apr 28, 2018 at 12:07:04AM +0300, Laurent Pinchart wrote:
>>> Hi Daniel,
>>>
>>> (Removing the linux-media mailing list from CC as it is out of scope)
>>>
>>> You enquired on IRC whether this patch series passes the igt CRC tests.
>>>
>>> # ./kms_pipe_crc_basic --run-subtest read-crc-pipe-A
>>> IGT-Version: 1.22-gf447f5fc531d (aarch64) (Linux: 
>>> 4.17.0-rc1-00085-g56e849d93cc9 aarch64)
>>> read-crc-pipe-A: Testing connector LVDS-1 using pipe A
>>> (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Test assertion failure 
>>> function igt_pipe_crc_start, file igt_debugfs.c:764:
>>> (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Failed assertion: 
>>> pipe_crc->crc_fd != -1
>>> (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Last errno: 5, Input/output 
>>> error
>>> Stack trace:
>>> Subtest read-crc-pipe-A failed.
>>>  DEBUG 
>>> (kms_pipe_crc_basic:1638) DEBUG: Test requirement passed: !(pipe >= 
>>> data->display.n_pipes)
>>> (kms_pipe_crc_basic:1638) INFO: read-crc-pipe-A: Testing connector LVDS-1 
>>> using pipe A
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: LVDS-1: set_pipe(A)
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: LVDS-1: Selecting pipe A
>>> (kms_pipe_crc_basic:1638) DEBUG: Clearing the fb with color (0.00,1.00,0.00)
>>> (kms_pipe_crc_basic:1638) igt-fb-DEBUG: 
>>> igt_create_fb_with_bo_size(width=1024, height=768, format=0x34325258, 
>>> tiling=0x0, size=0)
>>> (kms_pipe_crc_basic:1638) igt-fb-DEBUG: 
>>> igt_create_fb_with_bo_size(handle=1, pitch=4096)
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: Test requirement passed: plane_idx 
>>> >= 0 && plane_idx < pipe->n_planes
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: plane_set_fb(140)
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: plane_set_size 
>>> (1024x768)
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: fb_set_position(0,0)
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: A.0: fb_set_size(1024x768)
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: commit {
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: LVDS-1: SetCrtc pipe 
>>> A, fb 140, src (0, 0), mode 1024x768
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe A, 
>>> disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe A, 
>>> plane 2, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe A, 
>>> plane 3, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe A, 
>>> plane 4, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe B, 
>>> disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
>>> plane 1, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
>>> plane 2, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
>>> plane 3, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe B, 
>>> plane 4, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe C, 
>>> disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
>>> plane 1, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
>>> plane 2, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
>>> plane 3, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe C, 
>>> plane 4, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe D, 
>>> disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetCrtc pipe D, 
>>> disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe D, 
>>> plane 2, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe D, 
>>> plane 3, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: SetPlane pipe D, 
>>> plane 4, disabling
>>> (kms_pipe_crc_basic:1638) igt-kms-DEBUG: display: }
>>> (kms_pipe_crc_basic:1638) igt-debugfs-DEBUG: Opening debugfs directory 
>>> '/sys/kernel/debug/dri/0'
>>> (kms_pipe_crc_basic:1638) igt-debugfs-DEBUG: Opening debugfs directory 
>>> '/sys/kernel/debug/dri/0'
>>> (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Test assertion failure 
>>> function igt_pipe_crc_start, file igt_debugfs.c:764:
>>> (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Failed assertion: 
>>> pipe_crc->crc_fd != -1
>>> (kms_pipe_crc_basic:1638) igt-debugfs-CRITICAL: Last errno: 5, Input/output 
>>> error
>>> (kms_pipe_crc_basic:1638) igt-core-INFO: Stack trace:
>>>   END  
>>> Subtest read-crc-pipe-A: FAIL (0.061s)
>>>
>>> I think the answer is no, but I don't think it's the fault of this patch
>>> series. Opening the CRC data file returns -EIO because the CRTC is not 
>>> active,
>>> and I'm 

Re: [PATCH v7 8/8] media: vsp1: Move video configuration to a cached dlb

[Kieran Bingham]

Hi Laurent,

New plan ... (from the .. why didn't I think of this earlier department)



On 30/04/18 18:48, Kieran Bingham wrote:
> Hi Laurent,
> 
> On 07/04/18 01:23, Laurent Pinchart wrote:
>> Hi Kieran,
>>
>> Thank you for the patch.
>>
>> On Thursday, 8 March 2018 02:05:31 EEST Kieran Bingham wrote:
>>> We are now able to configure a pipeline directly into a local display
>>> list body. Take advantage of this fact, and create a cacheable body to
>>> store the configuration of the pipeline in the video object.
>>>
>>> vsp1_video_pipeline_run() is now the last user of the pipe->dl object.
>>> Convert this function to use the cached video->config body and obtain a
>>> local display list reference.
>>>
>>> Attach the video->config body to the display list when needed before
>>> committing to hardware.
>>>
>>> The pipe object is marked as un-configured when resuming from a suspend.
>>> This ensures that when the hardware is reset - our cached configuration
>>> will be re-attached to the next committed DL.
>>>
>>> Signed-off-by: Kieran Bingham 
>>> ---
>>>
>>> v3:
>>>  - 's/fragment/body/', 's/fragments/bodies/'
>>>  - video dlb cache allocation increased from 2 to 3 dlbs
>>>
>>> Our video DL usage now looks like the below output:
>>>
>>> dl->body0 contains our disposable runtime configuration. Max 41.
>>> dl_child->body0 is our partition specific configuration. Max 12.
>>> dl->bodies shows our constant configuration and LUTs.
>>>
>>>   These two are LUT/CLU:
>>>  * dl->bodies[x]->num_entries 256 / max 256
>>>  * dl->bodies[x]->num_entries 4914 / max 4914
>>>
>>> Which shows that our 'constant' configuration cache is currently
>>> utilised to a maximum of 64 entries.
>>>
>>> trace-cmd report | \
>>> grep max | sed 's/.*vsp1_dl_list_commit://g' | sort | uniq;
>>>
>>>   dl->body0->num_entries 13 / max 128
>>>   dl->body0->num_entries 14 / max 128
>>>   dl->body0->num_entries 16 / max 128
>>>   dl->body0->num_entries 20 / max 128
>>>   dl->body0->num_entries 27 / max 128
>>>   dl->body0->num_entries 34 / max 128
>>>   dl->body0->num_entries 41 / max 128
>>>   dl_child->body0->num_entries 10 / max 128
>>>   dl_child->body0->num_entries 12 / max 128
>>>   dl->bodies[x]->num_entries 15 / max 128
>>>   dl->bodies[x]->num_entries 16 / max 128
>>>   dl->bodies[x]->num_entries 17 / max 128
>>>   dl->bodies[x]->num_entries 18 / max 128
>>>   dl->bodies[x]->num_entries 20 / max 128
>>>   dl->bodies[x]->num_entries 21 / max 128
>>>   dl->bodies[x]->num_entries 256 / max 256
>>>   dl->bodies[x]->num_entries 31 / max 128
>>>   dl->bodies[x]->num_entries 32 / max 128
>>>   dl->bodies[x]->num_entries 39 / max 128
>>>   dl->bodies[x]->num_entries 40 / max 128
>>>   dl->bodies[x]->num_entries 47 / max 128
>>>   dl->bodies[x]->num_entries 48 / max 128
>>>   dl->bodies[x]->num_entries 4914 / max 4914
>>>   dl->bodies[x]->num_entries 55 / max 128
>>>   dl->bodies[x]->num_entries 56 / max 128
>>>   dl->bodies[x]->num_entries 63 / max 128
>>>   dl->bodies[x]->num_entries 64 / max 128
>>
>> This might be useful to capture in the main part of the commit message.
>>
>>> v4:
>>>  - Adjust pipe configured flag to be reset on resume rather than suspend
>>>  - rename dl_child, dl_next
>>>
>>>  drivers/media/platform/vsp1/vsp1_pipe.c  |  7 +++-
>>>  drivers/media/platform/vsp1/vsp1_pipe.h  |  4 +-
>>>  drivers/media/platform/vsp1/vsp1_video.c | 67 -
>>>  drivers/media/platform/vsp1/vsp1_video.h |  2 +-
>>>  4 files changed, 54 insertions(+), 26 deletions(-)
>>>
>>> diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c
>>> b/drivers/media/platform/vsp1/vsp1_pipe.c index 5012643583b6..fa445b1a2e38
>>> 100644
>>> --- a/drivers/media/platform/vsp1/vsp1_pipe.c
>>> +++ b/drivers/media/platform/vsp1/vsp1_pipe.c
>>> @@ -249,6 +249,7 @@ void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
>>> vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
>>>VI6_CMD_STRCMD);
>>> pipe->state = VSP1_PIPELINE_RUNNING;
>>> +   pipe->configured = true;

Look at that lovely pipe->state flag update right above the pipe->configured
update...

>>> }
>>>
>>> pipe->buffers_ready = 0;
>>> @@ -470,6 +471,12 @@ void vsp1_pipelines_resume(struct vsp1_device *vsp1)
>>> continue;
>>>
>>> spin_lock_irqsave(>irqlock, flags);
>>> +   /*
>>> +* The hardware may have been reset during a suspend and will
>>> +* need a full reconfiguration
>>> +*/
>>
>> s/reconfiguration/reconfiguration./
>>
>>> +   pipe->configured = false;

If we have 'suspended' then pipe->state == STOPPED


>>> +
>>
>> Where does that full reconfiguration occur, given that the 
>> vsp1_pipeline_run() 
>> right below sets pipe->configured to true without performing reconfiguration 
>> ?
> 
> It's magic isn't it :D
> 
> If the pipe->configured flag gets set to false, the next execution of
> 

Re: [PATCH v3] arm64: dts: renesas: v3msk: add DU/LVDS/HDMI support

[Simon Horman]

On Mon, Apr 23, 2018 at 11:45:49PM +0300, Sergei Shtylyov wrote:
> Define the V3M Starter Kit board dependent part of the DU and LVDS device
> nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
> Analog Devices ADV7511W HDMI transmitter...
> 
> Based on the original (and large) patch by Vladimir Barinov.
> 
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> This patch is against the 'renesas-devel-20180423-v4.17-rc2' tag of Simon
> Horman's 'renesas.git' repo. It requires the Thine THC63LVD1024 driver in
> order to work (the same as the Eagle HDMI patch by Jacopo/Niklas).
> 
> Changes in version 3:
> - added  Thine THC63LVD1024 device node, updating the respected endpoints;
> - merged the I2C pins subnode to the main PFC device node;
> - renamed the regulators;

Thanks, applied.