Define the generic R8A77970 part of the MMC0 (SDHI2) device node.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 12
1 file changed, 12 insertions(+)
Add the eMMC chip support for the V3M Started Kit board.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 26 +
1 file changed, 26
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180810-v4.18-rc7' tag. We're adding the R8A77970 MMC0
(SDHI2) device nodes and then enable eMMC support on the V3M Starter Kit
board. The SDHI (w/internal DMA) driver patch white-listing the R8A77970
On Tue, Jul 31, 2018 at 6:08 PM Geert Uytterhoeven
wrote:
> SH-Mobile AG5 and R-Car H1 SoCs are based on the Cortex-A9 MPCore, which
> includes a global timer.
>
> Enable the ARM global timer on these SoCs, which will be used for:
> - the scheduler clock, improving scheduler accuracy from 10 ms
Document the R-Car V3M (R8A77970) SoC in the R-Car SDHI bindings -- it's
the usual R-Car gen3 compatible controller with the internal DMA engine.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'next' branch of Ulf Hansson's 'mmc.git' repo.
Successfully tested on H3 ES1.0 and ES2.0, M3-W ES1.0, and M3-N ES1.0.
Even previously stubborn cards work fine. Transfer rates were >60MB/s.
Signed-off-by: Wolfram Sang
---
The problems I reported last week were simply me booting the wrong kernel on H3
ES1.0 :(
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
We'll also need to support the SoC specific clock types, thus we're adding
Hi Geert,
On 21/08/18 16:45, Geert Uytterhoeven wrote:
Hi Robin,
CC Lee (mfd), Wolfram (i2c), Marek (bd9571wmv + recent da9063 hacking)
On Fri, Jul 27, 2018 at 6:28 PM Robin Murphy wrote:
On 27/07/18 17:17, Stefan Wahren wrote:
i was noticed that recent linux-next on Raspberry Pi 3 (32
On Tue, Aug 21, 2018 at 05:45:43PM +0200, Geert Uytterhoeven wrote:
> Hi Robin,
>
> CC Lee (mfd), Wolfram (i2c), Marek (bd9571wmv + recent da9063 hacking)
>
> On Fri, Jul 27, 2018 at 6:28 PM Robin Murphy wrote:
> > On 27/07/18 17:17, Stefan Wahren wrote:
> > > i was noticed that recent
I have pushed renesas-drivers-2018-08-21-v4.18 to
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git
This tree is meant to ease development of platform support and drivers
for Renesas ARM SoCs. It is created by merging (a) the for-next branches
of various subsystem trees and
Hi Robin,
CC Lee (mfd), Wolfram (i2c), Marek (bd9571wmv + recent da9063 hacking)
On Fri, Jul 27, 2018 at 6:28 PM Robin Murphy wrote:
> On 27/07/18 17:17, Stefan Wahren wrote:
> > i was noticed that recent linux-next on Raspberry Pi 3 (32 bit) doesn't
> > boot anymore. So i tested todays
On Tue, Aug 21, 2018 at 08:58:38AM +, Phil Edworthy wrote:
> Hi Lorenzo,
>
> On 20 August 2018 15:48 Lorenzo Pieralisi wrote:
> > On Mon, Aug 20, 2018 at 01:44:48PM +, Phil Edworthy wrote:
> >
> > [...]
> >
> > > However, both before and after this patch, the RP does not transition
> >
On Fri, Aug 17, 2018 at 11:19:02PM +0300, Sergei Shtylyov wrote:
> Fix a stray underscore in the DM_CM_DTRAN_MODE.BUS_WIDTH register field
> name.
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Simon Horman
On Fri, Aug 17, 2018 at 11:20:23PM +0300, Sergei Shtylyov wrote:
> Fix the typo in the comment to #define DTRAN_MODE_CH_NUM_CH1.
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Simon Horman
On Sun, Aug 12, 2018 at 03:31:45PM +0200, Eugeniu Rosca wrote:
> According to R-Car Gen3 HW manual Rev.1.00 Apr 2018, M3-N SoC implements
> five (0..4) HSCIF channels, similar to H3, M3-W and E3.
>
> The story behind this patch is tackling below dmesg warnings, which pop
> up when booting M3NULCB
On Fri, Aug 17, 2018 at 03:53:03PM +0100, Fabrizio Castro wrote:
> Add r8a774a1 specific compatible string.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Simon Horman
On Fri, Aug 17, 2018 at 03:58:34PM +0100, Fabrizio Castro wrote:
> Document RZ/G2M (R8A774A1) SoC bindings.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Simon Horman
> > +/* MD12 (SW12-7) must be set 'Off' which is not the default! */
>
> Upon reading this again, I think this comment is confusing: the 'Off' refers
> to the switch position, not to the MD12 logic value, while the parentheses
> suggest otherwise.
>
> What about the following?
>
> SW12-7
Hi Wolfram, Simon,
On Mon, Jul 30, 2018 at 9:34 AM Wolfram Sang
wrote:
> Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
> off for that to work.
>
> Signed-off-by: Wolfram Sang
> Reviewed-by: Geert Uytterhoeven
> ---
>
> Changes since v1:
> * fixed indentation
Hi Lorenzo,
On 20 August 2018 15:48 Lorenzo Pieralisi wrote:
> On Mon, Aug 20, 2018 at 01:44:48PM +, Phil Edworthy wrote:
>
> [...]
>
> > However, both before and after this patch, the RP does not transition
> > L1 when the endpoints change to L1.
> > This patch only transitions the RP to
Hello Jacopo,
Thank you for the patch.
On Wednesday, 1 August 2018 17:26:36 EEST Jacopo Mondi wrote:
> The processor manual prescribes to clear reset of LVDS interface in CPG/MSSR
> module before display on, and to assert the same reset line at display off
> time, to have the module resuming in
Hi Sato-san
> > > Given the above clause I wonder if the SPDX identifier should be:
> > >
> > > SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
> >
> > Ahh, indeed.
> > I will post v2 patch.
> > Sato-san, can I post [13/13 v2] only ? or should post all patches ?
> >
>
> Please sent
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