atch!
Reviewed-by: Geert Uytterhoeven
> --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
> +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
Perhaps you want to add an "ethernet0" alias, so U-Boot can find the
device-node and add an appropriate "local-mac-address" property?
Gr{oe
On Tue, Apr 30, 2019 at 3:33 PM Chris Brandt wrote:
> Add SDHI support for the R7S9210 (RZ/A2) SoC.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32
On Tue, Apr 30, 2019 at 3:36 PM Chris Brandt wrote:
> Document support for the R7S9210 (RZ/A2) SoC. Also explicitly document
> bindings for the R7S72100 (RZ/A1) SoC.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geer
On Tue, Apr 30, 2019 at 3:42 PM Chris Brandt wrote:
> Add I2C support for the R7S9210 (RZ/A2) SoC.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32
On Tue, Apr 30, 2019 at 3:33 PM Chris Brandt wrote:
> Add Ethernet support for the RZ/A2 SoC.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@
On Tue, Apr 30, 2019 at 3:34 PM Chris Brandt wrote:
> Add RSPI support for RZ/A2 SoC.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linu
On Fri, Apr 5, 2019 at 7:44 AM Cao Van Dong wrote:
> Document SoC specific bindings for R-Car H3/M3-N/E3 SoCs.
>
> Signed-off-by: Cao Van Dong
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux bey
On Fri, Apr 5, 2019 at 7:44 AM Cao Van Dong wrote:
> This patch adds CMT{0|1|2|3} device nodes for r8a77990 SoC.
>
> Signed-off-by: Cao Van Dong
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux bey
On Fri, Apr 5, 2019 at 7:44 AM Cao Van Dong wrote:
> This patch adds CMT{0|1|2|3} device nodes for r8a77965 SoC.
>
> Tested-by: Cao Van Dong
> Signed-off-by: Cao Van Dong
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven --
On Fri, Apr 5, 2019 at 7:44 AM Cao Van Dong wrote:
> This patch adds CMT{0|1|2|3} device nodes for r8a7795 SoC.
>
> Tested-by: Cao Van Dong
> Signed-off-by: Cao Van Dong
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven --
<&cpg 626>;
> +
> + renesas,fcp = <&fcpvb0>;
> + };
Apart from that:
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m
On Tue, Apr 16, 2019 at 5:38 PM Biju Das wrote:
> The r8a774a1 has a single FDP1 instance similar to r8a7796.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux bey
On Tue, Apr 16, 2019 at 5:38 PM Biju Das wrote:
> Hook up r8a774a1 Audio-DMAC nodes to the IPMMU-MP.
>
> Based on work for the r8a7795 by Magnus Damm.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Gee
On Tue, Apr 16, 2019 at 5:38 PM Biju Das wrote:
> Add IPMMU-DS0 to the Ethernet-AVB device node.
>
> Based on work by Magnus Damm for the r8a7795.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterho
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say &q
On Tue, Apr 9, 2019 at 10:52 AM Cao Van Dong wrote:
> Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC.
>
> Signed-off-by: Cao Van Dong
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's
On Fri, Apr 19, 2019 at 4:41 PM Simon Horman wrote:
> From: Cao Van Dong
>
> Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the
> RZ/G1C (r8a77470) SoC.
>
> Signed-off-by: Cao Van Dong
> Signed-off-by: Simon Horman
Reviewed-by: Geert Uytterhoeve
On Thu, Apr 11, 2019 at 9:54 AM Cao Van Dong wrote:
> Add hscif{0|1|2} nodes to dtsi for HSCIF support on the RZ/G1C (r8a77470) SoC.
>
> Signed-off-by: Cao Van Dong
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There&
On Wed, Apr 10, 2019 at 4:55 PM Biju Das wrote:
> Define the r8a77470 generic part of the USB PHY device node.
>
> Signed-off-by: Biju Das
> Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- The
> Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm ta
qchip tree,
- Patches 3-5 are meant for the Renesas tree.
This has been tested on RSK+RZA1 with evtest and s2ram wake-up.
I have verified proper operation of low-level and rising/falling sense
select, too.
Thanks!
Geert Uytterhoeven (5):
dt-bindings: interrupt-controller: Add Renesas RZ/A1
Add support for input switches SW1-3 on the Renesas RZ/A1 RSK+RZA1
development board.
Note that this uses the IRQ interrupts, as the RZ/A1 GPIO controller
does not include interrupt support.
Signed-off-by: Geert Uytterhoeven
---
v3:
- No changes,
v2:
- Use rza1-irqc instead of gic
Enable support for the IRQC on RZ/A1H, which is a small front-end to the
GIC. This allows to use up to 8 external interrupts with configurable
sense select.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by,
- Add "renesas,gic-spi-base".
---
Add a driver for the Renesas RZ/A1 Interrupt Controller.
This supports using up to 8 external interrupts on RZ/A1, with
configurable sense select.
NMI edge select is not yet supported.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Use u16 for register values,
- Use relaxed I/O accessors
Auto-enable support for the RZ/A1 Interrupt Controller when configuring
a kernel which supports RZ/A1H or RZ/A2M SoCs.
Keep selects sorted while at it.
This is similar to how interrupt controllers for other Renesas SoCs are
enabled.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Add "renesas,gic-spi-base",
- Document RZ/A2M.
---
.../renesas,rza1-irqc.txt | 30 +++
1 file changed, 30 insertions(+)
create m
Hi Sergei,
On Tue, Apr 30, 2019 at 10:12 AM Sergei Shtylyov
wrote:
> On 29.04.2019 18:20, Geert Uytterhoeven wrote:
> > There is no need to print a message if devm_kzalloc() or
>
> Just kzalloc() in this case.
Thanks, silly copy-and-paste error.
> > --- a/drivers/irqch
commits
having been accepted in an upstream integration tree.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talkin
newer versions of some commits
having been accepted in an upstream integration tree.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. B
tree.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
e,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programme
l Comet Lake
+ bee5c20b7323a7af027d1b4ba538137b518ad232 dt-bindings: spi:
spi-mt65xx: add support for MT8516
+ 4b490710d4d24f95e95a07baac6f3f98bb94cf3b spi: expand mode support
+ ad1ac1fa0b24b40281eeccdc1d7b085e77639357 spi/spi-bcm2835: Split
transfers that exceed DLEN
Thanks!
Gr{oetje,eeting}s,
Geert
--
devm_iio_device_alloc() can only fail due to a memory or IDA allocation
failure. Hence there is no need to print a message, as the memory
allocation or IIO core code already takes care of that.
Signed-off-by: Geert Uytterhoeven
---
drivers/iio/adc/rcar-gyroadc.c | 4 +---
1 file changed, 1
ata_host_alloc() can only fail due to memory allocation failures.
Hence there is no need to print a message, as the memory allocation core
code already takes care of that.
Signed-off-by: Geert Uytterhoeven
---
drivers/ata/sata_rcar.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers
Simplify error handling by converting the driver to use managed
allocations and initializations.
Note that platform_get_resource() and ioremap_nocache() are combined in
devm_platform_ioremap_resource().
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-irqc.c | 54
Hi all,
This is a set of miscellaneous cleanups and improvements for the Renesas
R-Mobile APE6 and R-Car IRQC driver.
Thanks!
Geert Uytterhoeven (5):
irqchip/renesas-irqc: Remove unneeded inclusion of
irqchip/renesas-irqc: Remove devm_kzalloc()/ioremap_nocache() error
printing
Nothing really uses irqc_priv.pdev, all users need irqc_priv.pdev->dev.
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-irqc.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-irqc.c
b/drivers/irqchip/irq-renesas-irq
There is no need to print a message if devm_kzalloc() or
ioremap_nocache() fails, as the memory allocation core already takes
care of that.
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-irqc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/irqchip/irq-renesas
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-irqc.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-irqc.c
b/drivers/irqchip/irq-renesas-irqc.c
index 0955ffe12b32eb36..3cc428ba495c3793 100644
--- a
The driver never used spinlocks, and thus does not need to include
.
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-irqc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/irqchip/irq-renesas-irqc.c
b/drivers/irqchip/irq-renesas-irqc.c
index a449a7c839b3ec08
There is no need to print a message if devm_kzalloc() fails, as the
memory allocation core already takes care of that.
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/irq-renesas-intc-irqpin.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq
Hi Chris,
On Mon, Apr 29, 2019 at 2:21 PM Chris Brandt wrote:
> I've been hacking this support into the standard GIC driver in our BSPs
> for years now. :o
Yeah, and having that patch in your tree breaks all other GICs, as
I found out the hard way ;-)
> On Mon, Apr 29, 2019, Geer
Hi Marc,
On Mon, Apr 29, 2019 at 12:07 PM Marc Zyngier wrote:
> On 29/04/2019 10:36, Geert Uytterhoeven wrote:
> > Add a driver for the Renesas RZ/A1 Interrupt Controller.
> >
> > This supports using up to 8 external interrupts on RZ/A1, with
> > configurable sen
Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
Signed-off-by: Geert Uytterhoeven
---
.../renesas,rza1-irqc.txt | 27 +++
1 file changed, 27 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,rza1
n accepted,
- Patch 5 depends on patch 4.
This has been tested on RSK+RZA1 with evtest and s2ram wake-up.
I have verified proper operation of low-level and rising/falling sense
select, too.
Thanks for your comments!
Geert Uytterhoeven (5):
dt-bindings: interrupt-controller: Add Renesas RZ/A1
Add support for input switches SW1-3 on the Renesas RZ/A1 RSK+RZA1
development board.
Note that this uses the IRQ interrupts, as the RZ/A1 GPIO controller
does not include interrupt support.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Use rza1-irqc instead of gic.
---
arch/arm/boot/dts
Add a driver for the Renesas RZ/A1 Interrupt Controller.
This supports using up to 8 external interrupts on RZ/A1, with
configurable sense select.
NMI edge select is not yet supported.
Signed-off-by: Geert Uytterhoeven
---
drivers/irqchip/Kconfig| 4 +
drivers/irqchip/Makefile
Auto-enable the RZ/A1 Interrupt Controller when configuring a kernel
with support for RZ/A1H SoCs.
This is similar to how interrupt controllers for other Renesas SoCs are
enabled.
Signed-off-by: Geert Uytterhoeven
---
drivers/soc/renesas/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
Enable support for the IRQC on RZ/A1H, which is a small front-end to the
GIC. This allows to use up to 8 external interrupts with configurable
sense select.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r7s72100.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch
Hi Simon,
On Fri, Apr 26, 2019 at 11:21 AM Simon Horman wrote:
> On Thu, Apr 25, 2019 at 11:55:39AM +0200, Geert Uytterhoeven wrote:
> > Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at
> > runtime when debugging")
> > Signed-off-by: Geert Uy
Hi Simon,
On Fri, Apr 26, 2019 at 11:35 AM Simon Horman wrote:
> On Thu, Apr 25, 2019 at 11:55:41AM +0200, Geert Uytterhoeven wrote:
> > The pinmux groups and functions arrays may contain two parts, to ease
> > supporting SoCs that expose pin subsets of other related SoCs. Both
On Thu, Apr 25, 2019 at 3:25 AM Cao Van Dong wrote:
> This patch adds TPU clock to R-car r8a7795/r8a7796/r8a77965 Socs.
>
> Signed-off-by: Cao Van Dong
Reviewed-by: Geert Uytterhoeven
i.e. will queue in clk-renesas-for-v5.3.
Gr{oetje,eeting}s,
Geert
Hi Linus,
This patch series contains miscellaneous improvements to the Renesas pin
control source code base. None of these have any impact on the
resulting binary.
I intend to queue this in sh-pfc-for-v5.3.
Thanks for your comments!
Geert Uytterhoeven (3):
pinctrl: sh-pfc: Rename 2
Several drivers have identical definitions for PIN_NONE.
Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h,
and convert all drivers over to use it.
Signed-off-by: Geert Uytterhoeven
---
drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 76 ++--
drivers/pinctrl/sh
2-parameter variant to CPU_ALL_GP(), to avoid confusion, and
to increase naming consistency.
Signed-off-by: Geert Uytterhoeven
---
drivers/pinctrl/sh-pfc/pfc-r8a77470.c| 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +-
drivers/pinctrl/
: Geert Uytterhoeven
---
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 12 +---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 12 +---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 12
Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime
when debugging")
Signed-off-by: Geert Uytterhoeven
---
drivers/pinctrl/sh-pfc/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-
Extend the run-time debug code with checks to ensure there are no
conflicting pin names, numbers, or enumeration values.
This helps catching bugs early.
Signed-off-by: Geert Uytterhoeven
---
drivers/pinctrl/sh-pfc/core.c | 29 +
1 file changed, 29 insertions
Hi Linus,
This patch series contains several fixes and enhancements for the
debug code to validate pinctrl tables at run-time.
I intend to queue this in sh-pfc-for-v5.3.
Thanks for your comments!
Geert Uytterhoeven (4):
pinctrl: sh-pfc: Correct printk level of group referral warning
time debug code (for
pin groups).
Extend the run-time debug code with checks to detect this, to help
catching bugs early.
Signed-off-by: Geert Uytterhoeven
---
drivers/pinctrl/sh-pfc/core.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/core
All run-time debug code is called from sh_pfc_init(), which is __init.
Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime
when debugging")
Signed-off-by: Geert Uytterhoeven
---
drivers/pinctrl/sh-pfc/core.c | 14 +++---
1 file changed, 7 insert
resume.
Signed-off-by: Geert Uytterhoeven
---
This patch takes a different approach than the BSP, which implements a
bulk save/restore of all registers during system suspend/resume.
v3:
- No changes,
v2:
- Drop PSCI checks.
---
drivers/iommu/ipmmu-vmsa.c | 47
On R-Car Gen3, the faulting virtual address is a 40-bit address, and
comprised of two registers. Read the upper address part, and combine
both parts, when running on a 64-bit system.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
Apart from this, the driver doesn't suppo
Make the IPMMU_CTX_MAX constant unsigned, to match the type of
ipmmu_features.number_of_contexts.
This allows to use plain min() instead of type-casting min_t().
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
Reviewed-by: Simon Horman
---
v3:
- Add Reviewed-by,
v2:
- Add
r H3 ES2.0, with IPMMU
suport for SATA enabled. To play safe, the resume operation has also
been tested on R-Car M2-W.
Thanks!
Geert Uytterhoeven (6):
iommu/ipmmu-vmsa: Link IOMMUs and devices in sysfs
iommu/ipmmu-vmsa: Prepare to handle 40-bit error addresses
iommu/ipmmu-vmsa: Make IPM
ipmmu_domain_init_context() takes care of (1) initializing the software
domain, and (2) initializing the hardware context for the domain.
Extract the code to initialize the hardware context into a new subroutine
ipmmu_domain_setup_context(), to prepare for later reuse.
Signed-off-by: Geert
all links are created, on both arm32 and arm64.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
---
v3:
- Fix sysfs path typo in patch description,
v2:
- Add Reviewed-by.
---
drivers/iommu/ipmmu-vmsa.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(
The maximum number of micro-TLBs per IPMMU instance is not fixed, but
depends on the SoC type. Hence move it from struct ipmmu_vmsa_device to
struct ipmmu_features, and set up the correct value for both R-Car Gen2
and Gen3 SoCs.
Note that currently no code uses this value.
Signed-off-by: Geert
nfig?
Shimoda-san: can you please enlighten us?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking
now, but
from Marek's report, Porter has DA9063L CA.
Marek: which variant does your Stout (R-Car H2) have?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
->identity;
struct watchdog_info {
...
__u8 identity[32]; /* Identity of the board */
};
Is identity[] guaranteed to be NUL-terminated?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge..
into separate patches, as DTS and
clock driver changes go in through different subsystem/maintainer paths.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I
power-coefficient = <854>;
> > > + cooling-min-level = <0>;
> > > + cooling-max-level = <2>;
> >
> > I can't find any documentation or code which makes use of the
> > cooling-min-level and cooling-max-level
n shmobile_defconfig").
>
> Signed-off-by: Biju Das
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myse
((priv->ctemp * 5) - 60);
> } else {
> tmp = MCELSIUS((priv->ctemp * 5) - 65);
> }
_Iff_ we decide on going for the rename, I'd still write it as:
if (!priv->chip->gen3)
tmp = MCELSIUS((priv->ctemp * 5) - 65);
else if (priv->c
Hi Simon,
On Thu, Apr 11, 2019 at 10:39 AM Simon Horman wrote:
> On Wed, Apr 03, 2019 at 08:21:48PM +0200, Geert Uytterhoeven wrote:
> > During PSCI system suspend, R-Car Gen3 SoCs are powered down, and all
> > IPMMU state is lost. Hence after s2ram, devices wired behind an
Hi Simon,
On Thu, Apr 11, 2019 at 10:12 AM Simon Horman wrote:
> On Thu, Apr 11, 2019 at 10:10:28AM +0200, Simon Horman wrote:
> > On Wed, Apr 03, 2019 at 08:21:43PM +0200, Geert Uytterhoeven wrote:
> > > As of commit 7af9a5fdb9e0ca33 ("iommu/ipmmu-vmsa: Use
> > >
t.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker
r.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -70,7 +70,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct
> device_node *np,
> unsigned long flags, unsigned int mult, unsigned int div)
> {
> struct clk_fixed_factor *fix;
> - str
emoved from shmobile_defconfig.
> # CONFIG_DNOTIFY is not set
> CONFIG_MSDOS_FS=y
> CONFIG_VFAT_FS=y
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical p
Hi Stephen,
On Thu, Apr 11, 2019 at 7:36 PM Stephen Boyd wrote:
> Quoting Geert Uytterhoeven (2019-04-04 04:37:22)
> > The following changes since commit 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b:
> >
> > Linux 5.1-rc1 (2019-03-17 14:22:26 -0700)
> >
> > are a
gt; zt 00 4
> 0 0
> ztr 00 2
> 0 0
> .sdsrc 11 8
> 0 0
> sd0
Geert Uytterhoeven (16):
pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
pinctrl: sh-pfc: r8a77980: Rename IOCTRLx registers
pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging
pinctrl: sh-pfc
h64.h | 13 ++
13 files changed, 137 insertions(+), 118 deletions(-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I cal
e placeholder pin data.
Thanks for the update!
Reviewed-by: Geert Uytterhoeven
i.e. queuing in sh-pfc-for-v5.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people,
On Wed, Apr 3, 2019 at 4:45 PM Ulrich Hecht wrote:
> Pin data for I2C controllers 0, 3 and 5 is properly defined already.
>
> Signed-off-by: Ulrich Hecht
Reviewed-by: Geert Uytterhoeven
i.e. queuing in sh-pfc-for-v5.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uyt
Hi Hoan,
On Thu, Apr 4, 2019 at 2:48 AM Hoan wrote:
> On 2019/04/03 18:24, Geert Uytterhoeven wrote:
> > On Wed, Apr 3, 2019 at 11:17 AM Nguyen An Hoan wrote:
> >> From: Hoan Nguyen An
> >>
> >> We can use each word (data length) of 32bits (4 bytes),
> &
,
- sh_msiof_get_cs_gpios() must release all GPIOs, else
spi_get_gpio_descs() cannot claim them during SPI controller
registration.
Signed-off-by: Geert Uytterhoeven
---
sh_msiof_get_cs_gpios() still duplicates some logic from
spi_get_gpio_descs(). Reusing spi_controller.cs_gpiods[] is not
trivial, as
siof_transfer_one(struct spi_controller
> *ctlr,
> return 0;
> }
>
> - if (bits <= 8 && len > 15) {
> + if (bits <= 8 && len > 3) {
Likewise.
> bits = 32;
> swab = true;
he check is different: the write sets the bit, the check
must wait until
the hardware has cleared the bit again.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people,
Improve maintainability by converting the register bit, bitmask, and
bitfield definitions from hexadecimal constants to constructs using
BIT(), GENMASK(), or "val << shift".
Suggested-by: Simon Horman
Signed-off-by: Geert Uytterhoeven
---
All definitions keep their original v
Replace the open-coded loop in sh_msiof_modify_ctr_wait() by a call to
the readl_poll_timeout_atomic() helper macro.
Suggested-by: Wolfram Sang
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
drivers/spi/spi-sh-msiof.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions
n out to be suitable
for calling by sh_msiof_spi_reset_regs()),
- Use BIT(),
- Use readl_poll_timeout_atomic().
Thanks!
Geert Uytterhoeven (3):
spi: sh-msiof: Use BIT() and GENMASK()
spi: sh-msiof: Use readl_poll_timeout_atomic() instead of open-coding
spi: sh-msiof: Add res
In accordance with hardware specification Ver 1.0, reset register
transmission / reception setting before transfer.
Signed-off-by: Hiromitsu Yamasaki
[geert: Use readl_poll_timeout_atomic()]
Signed-off-by: Geert Uytterhoeven
---
v2:
- Use BIT(),
- Use readl_poll_timeout_atomic
US to
256"), the default value of NR_CPUS was increased to 256, increasing the
waste by another 78 KiB.
Reduce NR_CPUS to 8, reducing kernel size by ca. 94 KiB.
Signed-off-by: Geert Uytterhoeven
---
arch/arm64/configs/renesas_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/
el/git/lee/mfd.git#for-mfd-next
- git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with t
t;)
Signed-off-by: Geert Uytterhoeven
---
v2:
- Use "<" instead of "<=" to use first match (doesn't matter, though,
but is more aligned with the behavior of cpg_sd_clock_calc_div()),
- Keep best_div instead of best_rate, to avoid extra
DIV_ROUND_CLOSEST().
Enable the config options needed to access the CFI NOR FLASH on the
APE6EVM board.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/configs/multi_v7_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index
Enable the config options needed to access the CFI NOR FLASH on the
APE6EVM board.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/configs/shmobile_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/shmobile_defconfig
b/arch/arm/configs/shmobile_defconfig
index
kernel size.
Thanks!
Geert Uytterhoeven (2):
ARM: shmobile: defconfig: Enable support for CFI NOR FLASH
ARM: multi_v7_defconfig: Enable support for CFI NOR FLASH
arch/arm/configs/multi_v7_defconfig | 4
arch/arm/configs/shmobile_defconfig | 4
2 files changed, 8 insertions
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