RE: [PATCH] PCI: rcar, rcar-gen2: Use ARCH_RENESAS

Hi Geert, On 25 February 2016 08:05, Geert Uytterhoeven wrote: > On Thu, Feb 25, 2016 at 1:45 AM, Simon Horman > wrote: > > Make use of ARCH_RENESAS in place of ARCH_SHMOBILE. > > > > This is part of an ongoing process to migrate from ARCH_SHMOBILE to > > ARCH_RENESAS

RE: [PATCH] ARM: dts: r8a7791: Don't disable referenced optional clocks

>>> +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts > >>> @@ -660,6 +660,7 @@ > >>>}; > >>> > >>>_bus_clk { > >>> + clock-frequency = <1>; > > >> Hmmm, looking at the Koelsch schematics, I don't see t

[PATCH 1/2] arm64: renesas: r8a7795: Add PCIe nodes

Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 58 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 868c10e..6

[PATCH v2 2/2] arm64: dts: r8a7795: enable PCIe on Salvator-X

Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- v2: no changes --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-sa

[PATCH v2 1/2] arm64: renesas: r8a7795: Add PCIe nodes

Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- v2: Dropped the "_clk" suffix from the PCIe bus device node's name. Removed "clock-output-names" property from the PCIe bus node. Use GIC_SPI for all interrupts. --- arch/arm64/boot/dts

[PATCH v2 0/2] Add PCIe to r8a7795 & Salvator-X

With these two patches PCIe works on the Salvator-X board. v2: Fixes for Geert's comments. Phil Edworthy (2): arm64: renesas: r8a7795: Add PCIe nodes arm64: dts: r8a7795: enable PCIe on Salvator-X arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 + arch/arm64/boot/dts/renesas

[PATCH v3 2/2] arm64: dts: r8a7795: enable PCIe on Salvator-X

Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- v3: no changes v2: no changes --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/r

[PATCH v3 1/2] arm64: renesas: r8a7795: Add PCIe nodes

Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- v3: Really use GIC_SPI for all interrupts. v2: Dropped the "_clk" suffix from the PCIe bus device node's name. Removed "clock-output-names" property from the PCIe bus node. Use GIC_SPI for all interrupts

Question about dma-ranges property for PCI host controllers

Hi, A few PCI host controllers use the "dma-ranges" property to specify the mapping from PCI bus addresses to physical addresses. In the case of R-Car PCIe Host controllers, the intention was to set this property as a 1 to 1 mapping for all DDR that could be addressed by the device. However,

RE: Question about dma-ranges property for PCI host controllers

Hi Arnd, On 11 August 2016 16:09 Arnd Bergmann wrote: > On Thursday, August 11, 2016 3:00:42 PM CEST Phil Edworthy wrote: > > Hi, > > > > A few PCI host controllers use the "dma-ranges" property to specify the > > mapping from PCI bus addresses to physical ad

[RFC] pci: Provide a domain limited version of pdev_fixup_irq

ate. This happens because dev->irq has been overwritten with 0, and irq_get_msi_desc(dev->irq) returns NULL. This patch introduces a new function, pci_fixup_irqs_local(), that performs the same operation as pdev_fixup_irq(), but only changes the dev->irq of device on the same domain. Signed-

RE: [RFC] pci: Provide a domain limited version of pdev_fixup_irq

Note that kbuild test failed because domain_nr is only available when we have CONFIG_PCI_DOMAINS_GENERIC defined, so the patch will definitely have to change. Phil On 08 July 2016 12:50, Phil Edworthy wrote: > Hi Bjorn, > > I've marked this as RFC as I guess there might be a better

RE: [RFC] pci: Provide a domain limited version of pdev_fixup_irq

Hi Lorenzo, Thanks for the link, I'll wait to see how this pans out. Thanks Phil > -Original Message- > From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci- > ow...@vger.kernel.org] On Behalf Of Lorenzo Pieralisi > Sent: 21 July 2016 10:35 > To: Phil Edwor

RE: [PATCH/RFC] PCI: rcar: Restrict pci_fixup_irqs to the same PCI domain

Hi Simon, On 07 November 2016 12:01, Simon Horman wrote: > From: Phil Edworthy <phil.edwor...@renesas.com> > > Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> > Signed-off-by: Simon Horman <horms+rene...@verge.net.au> > --- > > Phil, this is

RE: [PATCH/RFC 0/4] sh: sh7722/sh7757i/sh7264/sh7269: Fix pinctrl registration

Hi Geert, Thanks for the patches, sorry I can't test these either... It's been quite a few years since I had an sh7264 or sh7269 board! Thanks Phil -Original Message- On: 09 May 2017 16:44, Laurent Pinchart wrote: Subject: Re: [PATCH/RFC 0/4] sh: sh7722/sh7757i/sh7264/sh7269: Fix

RE: [PATCH v5] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Andy, On 05 May 2018 11:49 Andy Shevchenko wrote: > On Thu, Apr 26, 2018 at 7:19 PM, Phil Edworthy wrote: > > Sotty fo a late response. Consider follow up fixes for below. > > > if (!pp->irq_shared) { > > + int i; > > + > > +

[PATCH v6] gpio: dwapb: Add support for 1 interrupt per port A GPIO

, it will get as many interrupts as specified in the DT 'interrupts' property. It doesn't do anything clever with the different interrupts, it just calls the same handler used for single interrupt hardware. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> Reviewed-by: Rob Herring <r...@k

RE: [PATCH v6] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Linus, On 23 May 2018 09:29, Linus Walleij wrote: > On Fri, May 11, 2018 at 10:31 AM, Phil Edworthy wrote: > > > The DesignWare GPIO IP can be configured for either 1 interrupt or 1 > > per GPIO in port A, but the driver currently only supports 1 interrupt. > > See th

[PATCH] gpio: dwapb: Rework support for 1 interrupt per port A GPIO

(). Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- drivers/gpio/gpio-dwapb.c | 53 --- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c index 7dcd06b..15b4154 100644 --- a/d

RE: [PATCH] gpio: dwapb: Rework support for 1 interrupt per port A GPIO

Hi Simon, On 23 May 2018 10:12 Simon Horman wrote: > On Wed, May 23, 2018 at 09:52:44AM +0100, Phil Edworthy wrote: > > Treat DT and ACPI the same as much as possible. Note that we can't use > > platform_get_irq() to get the DT interrupts as they are in the port > > sub-node

[PATCH] gpio: dwapb: Fix rework support for 1 interrupt per port A GPIO

r feedback came afterwards. However, in my haste I managed to drop the changes made to dwapb_port_property struct. This patch includes those missing changes. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- include/linux/platform_data/gpio-dwapb.h | 2 +- 1 file changed, 1

[PATCH v5] gpio: dwapb: Add support for 1 interrupt per port A GPIO

y Hoan. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> Reviewed-by: Rob Herring <r...@kernel.org> Acked-by: Lee Jones <lee.jo...@linaro.org> --- One point to mention is that I have made it possible for users to have unconncted interrupts by specifying holes in the list of

RE: [PATCH] irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer

Hi Rob, On 01 May 2018 14:29 Rob Herring wrote: > On Mon, Apr 23, 2018 at 02:33:06PM +0100, Phil Edworthy wrote: > > On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each > > configured to have 32 interrupt outputs, so we have a total of 96 GPIO >

RE: [PATCH V2 4/5] PCI: rcar: Support runtime PM, link state L1 handling

Hi Lorenzo, On 20 August 2018 15:48 Lorenzo Pieralisi wrote: > On Mon, Aug 20, 2018 at 01:44:48PM +0000, Phil Edworthy wrote: > > [...] > > > However, both before and after this patch, the RP does not transition > > L1 when the endpoints change to L1. > > This

RE: [PATCH V2 4/5] PCI: rcar: Support runtime PM, link state L1 handling

Hi Lorenzo, On 21 August 2018 16:32, Lorenzo Pieralisi wrote: > On Tue, Aug 21, 2018 at 08:58:38AM +0000, Phil Edworthy wrote: > > On 20 August 2018 15:48 Lorenzo Pieralisi wrote: > > > On Mon, Aug 20, 2018 at 01:44:48PM +0000, Phil Edworthy wrote: > > > > > &g

RE: [PATCH V2 4/5] PCI: rcar: Support runtime PM, link state L1 handling

;>>>>> On 11/17/2017 06:49 PM, Lorenzo Pieralisi wrote: > >>>>>>>> On Fri, Nov 10, 2017 at 10:58:42PM +0100, Marek Vasut wrote: > >>>>>>>>> From: Phil Edworthy > >>>>>>>>> > >>>&g

RE: [PATCH] ARM: dts: r9a06g032: Correct UART and add all other UARTs

Hi Geert, On 06 September 2018 15:38 Geert Uytterhoeven wrote: > On Thu, Aug 30, 2018 at 11:52 AM Phil Edworthy wrote: > > - UART0 was missing the bus clock ("apb_pclk"). > > - Now that the relevant rzn1 bindings have been added, replace the > Synopsys > > c

[PATCH v2] ARM: dts: r9a06g032: Correct UART and add all other UARTs

- UART0 was missing the bus clock ("apb_pclk"). - Now that the relevant rzn1 bindings have been added, replace the Synopsys compat string with the rzn1 strings. - Add all the other UARTs. Signed-off-by: Phil Edworthy --- v2: - Keep the "snps,dw-apb-uart" fal

RE: [PATCH] ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions

Hi Geert, On 28 August 2018 16:13, Geert Uytterhoeven wrote: > Replace the hardcoded clock indices by R9A06G032_CLK_* symbols. > > Signed-off-by: Geert Uytterhoeven Reviewed-by: Phil Edworthy Thanks! Phil

[PATCH] ARM: dts: r9a06g032: Correct UART and add all other UARTs

- UART0 was missing the bus clock ("apb_pclk"). - Now that the relevant rzn1 bindings have been added, replace the Synopsys compat string with the rzn1 strings. - Add all the other UARTs. Signed-off-by: Phil Edworthy --- arch/arm/boot/dts/r9a06g032

RE: [PATCH 2/2] serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART

Hi Geert, On 11 July 2018 13:42, Geert Uytterhoeven wrote: > On Wed, Jul 11, 2018 at 2:30 PM Phil Edworthy wrote: > > The Renesas RZ/N1 UART is based on the Synopsys DW UART, but has > > additional registers for DMA. This patch does not address the changes > > required for D

[PATCH 1/2] dt: serial: Add Renesas RZ/N1 binding documentation

The RZ/N1 UART is a modified Synopsys DesignWare UART. The modifications only relate to DMA so you could actually use the controller with the Synopsys compatible string if you are not using DMA, but you should not do so. Signed-off-by: Phil Edworthy --- Documentation/devicetree/bindings/serial

[PATCH 0/2] dt: serial: Add Renesas RZ/N1 binding documentation

Just a new compatible string for the Synopsys UART to allow us to add DMA at some point in the future. Phil Edworthy (2): dt: serial: Add Renesas RZ/N1 binding documentation serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART Documentation/devicetree/bindings/serial/renesas,rzn1

[PATCH 2/2] serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART

The Renesas RZ/N1 UART is based on the Synopsys DW UART, but has additional registers for DMA. This patch does not address the changes required for DMA support, it simply adds the compatible string. Signed-off-by: Phil Edworthy --- drivers/tty/serial/8250/8250_dw.c | 1 + 1 file changed, 1

[PATCH v2 2/2] serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART

The Renesas RZ/N1 UART is based on the Synopsys DW UART, but has additional registers for DMA. This patch does not address the changes required for DMA support, it simply adds the compatible string. Signed-off-by: Phil Edworthy --- v2: - Change "renesas,-" to "renesas,-&qu

[PATCH v2 1/2] dt: serial: Add Renesas RZ/N1 binding documentation

The RZ/N1 UART is a modified Synopsys DesignWare UART. The modifications only relate to DMA so you could actually use the controller with the Synopsys compatible string if you are not using DMA, but you should not do so. Signed-off-by: Phil Edworthy --- v2: - Change "renesas,-" to

[PATCH v2 0/2] dt: serial: Add Renesas RZ/N1 binding documentation

Just a new compatible string for the Synopsys UART to allow us to add DMA at some point in the future. v2: - Change "renesas,-" to "renesas,-" Phil Edworthy (2): dt: serial: Add Renesas RZ/N1 binding documentation serial: 8250_dw: Add compatible string fo

RE: [PATCH 1/2] dt: serial: Add Renesas RZ/N1 binding documentation

Hi Geert, On 11 July 2018 13:39, Geert Uytterhoeven wrote: > On Wed, Jul 11, 2018 at 2:30 PM Phil Edworthy wrote: > > The RZ/N1 UART is a modified Synopsys DesignWare UART. > > The modifications only relate to DMA so you could actually use the > > controller with the Synop

RE: [PATCH 2/2] serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART

Hi Geert, On 11 July 2018 16:02, Phil Edworthy wrote: > On 11 July 2018 13:42, Geert Uytterhoeven wrote: > > On Wed, Jul 11, 2018 at 2:30 PM Phil Edworthy wrote: > > > The Renesas RZ/N1 UART is based on the Synopsys DW UART, but has > > > additional registers for DMA.

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi Geert, On 06 April 2018 10:57 Geert Uytterhoeven wrote: > On Thu, Apr 5, 2018 at 11:42 AM, Phil Edworthy wrote: > > On 30 March 2018 22:26 Andy Shevchenko wrote: > >> On Wed, Mar 28, 2018 at 5:22 PM, Phil Edworthy wrote: > >> > The DesignWare GPIO IP can be

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi Rob, On 10 April 2018 07:24 Phil Edworthy wrote: > On 09 April 2018 20:20 Rob Herring wrote: > > On Wed, Mar 28, 2018 at 03:22:30PM +0100, Phil Edworthy wrote: [...] > > > +- interrupt-mask : a 32-bit bit mask that specifies which interrupts > > > +in the list >

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi Geert, On 10 April 2018 15:29 Geert Uytterhoeven wrote: > On Tue, Apr 10, 2018 at 4:23 PM, Phil Edworthy wrote: > > On 10 April 2018 07:24 Phil Edworthy wrote: > >> On 09 April 2018 20:20 Rob Herring wrote: > >> > On Wed, Mar 28, 2018 at 03:22:3

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi Andy, On 30 March 2018 22:26 Andy Shevchenko wrote: > On Wed, Mar 28, 2018 at 5:22 PM, Phil Edworthy wrote: > > The DesignWare GPIO IP can be configured for either 1 or 32 > > interrupts, > > 1 to 32, or just a choice between two? Just a choice of 1 or 32. Note that

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi Andy, On 05 April 2018 10:43, Phil Edworthy wrote: > On 30 March 2018 22:26 Andy Shevchenko wrote: > > On Wed, Mar 28, 2018 at 5:22 PM, Phil Edworthy wrote: > > > The DesignWare GPIO IP can be configured for either 1 or 32 > > > interrupts, > > > > 1 to 3

RE: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Hoan, On 13 April 2018 17:37 Hoan Tran wrote: > On Fri, Apr 13, 2018 at 1:51 AM, Phil Edworthy wrote: > > The DesignWare GPIO IP can be configured for either 1 interrupt or 1 > > per GPIO in port A, but the driver currently only supports 1 interrupt. > > See the DesignWare

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi Rob, On 09 April 2018 20:20 Rob Herring wrote: > On Wed, Mar 28, 2018 at 03:22:30PM +0100, Phil Edworthy wrote: > > The DesignWare GPIO IP can be configured for either 1 or 32 > > interrupts, but the driver currently only supports 1 interrupt. See > > the DesignWare

RE: [PATCH v2 2/2] mfd: intel_quark_i2c_gpio: Update Synopsys GPIO interrupts

Hi Geert, On 13 April 2018 09:20 Geert Uytterhoeven wrote: > On Fri, Apr 13, 2018 at 10:08 AM, Phil Edworthy wrote: > > Since the way the Synopsys GPIO interrupts are stored has changed, > > this driver needs to be updated in line with the changes. > > > > Signed-off-by

[PATCH v2 0/2] gpio: dwapb: Add support for 1 interrupt per port A GPIO

-extended DT prop. However, I have no use for this and had to hack some test case for this. Perhaps the driver should support 1 interrupt or all GPIOa as interrupts? Phil Edworthy (2): gpio: dwapb: Add support for 1 interrupt per port A GPIO mfd: intel_quark_i2c_gpio: Update Synopsys GPIO

[PATCH v2 1/2] gpio: dwapb: Add support for 1 interrupt per port A GPIO

, it will get as many interrupts as specified in the DT 'interrupts' property. It doesn't do anything clever with the different interrupts, it just calls the same handler used for single interrupt hardware. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- v2: - Replaced interrupt-mask D

[PATCH v2 2/2] mfd: intel_quark_i2c_gpio: Update Synopsys GPIO interrupts

Since the way the Synopsys GPIO interrupts are stored has changed, this driver needs to be updated in line with the changes. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- v2: - New patch in v2 to fix the only other user of struct dwapb_port_property. --- drive

[PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

, it will get as many interrupts as specified in the DT 'interrupts' property. It doesn't do anything clever with the different interrupts, it just calls the same handler used for single interrupt hardware. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- One point to mention is that I hav

[PATCH v4] gpio: dwapb: Add support for 1 interrupt per port A GPIO

, it will get as many interrupts as specified in the DT 'interrupts' property. It doesn't do anything clever with the different interrupts, it just calls the same handler used for single interrupt hardware. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- One point to mention is that I hav

RE: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Rob, On 16 April 2018 21:03 Rob Herring wrote: > On Fri, Apr 13, 2018 at 09:51:12AM +0100, Phil Edworthy wrote: > > The DesignWare GPIO IP can be configured for either 1 interrupt or 1 > > per GPIO in port A, but the driver currently only supports 1 interrupt. > &g

RE: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

Hi Hoan On 18 April 2018 08:03 Hoan Tran wrote: > On Fri, Apr 13, 2018 at 9:47 AM, Phil Edworthy wrote: > > On 13 April 2018 17:37 Hoan Tran wrote: > >> On Fri, Apr 13, 2018 at 1:51 AM, Phil Edworthy wrote: > >> > The DesignWare GPIO IP can be configured for eith

[PATCH] irqchip: Add support for Renesas RZ/N1 GPIO interrupt multiplexer

there is nothing to do in this driver when an interrupt is received, other than tell the corresponding GPIO block. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- .../interrupt-controller/renesas,rzn1-mux.txt | 85 ++ drivers/irqchip/K

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

Hi, On 28 March 2018 15:23, Phil Edworthy wrote: > The DesignWare GPIO IP can be configured for either 1 or 32 interrupts, > but the driver currently only supports 1 interrupt. See the DesignWare > DW_apb_gpio Databook description of the 'GPIO_INTR_IO' parameter. > > Thi

[PATCH] gpio: dwapb: Add support for 32 interrupts

interrupts as specified in the DT 'interrupts' property. It doesn't do anything clever with the different interrupts, it just calls the same handler used for single interrupt hardware. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- Note: There are a few lines over 80

RE: [PATCH] mmc: sdhci-of-arasan: Add quirk to avoid erroneous msg

Hi Shawn, On 28 February 2018 01:53, Shawn Lin wrote: > On 2018/2/27 23:05, Phil Edworthy wrote: > > On 27 February 2018 14:42, Shawn Lin wrote: > >> On 2018/2/27 22:31, Phil Edworthy wrote: > >>> On 27 February 2018 14:28, Shawn Lin wrote: > >>

RE: [PATCH 0/2] arm: Support for Renesas RZ/N1D (R9A06G032)

Hi Simon, On 26 February 2018, Michel Pollet wrote: > > This series adds the plain basic support for booting a bare > kernel on the RZ/N1D-DB Board. It's been trimmed to the strict > minimum as a 'base', further patches that will add the > rest of the support, pinctrl, clock architecture and

[PATCH] mmc: sdhci-of-arasan: Add quirk to avoid erroneous msg

an IP. See https://patchwork.kernel.org/patch/8062871/ This has been tested on the Renesas RZ/ND-DB board with the RZ/N1 SoC. Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> --- drivers/mmc/host/sdhci-of-arasan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --g

RE: [PATCH] mmc: sdhci-of-arasan: Add quirk to avoid erroneous msg

Hi Adrian, On 27 February 2018 14:08, Adrian Hunter wrote: > On 27/02/18 15:55, Phil Edworthy wrote: > > Since the controller does not support the end-of-busy IRQ, don't use it. > > Otherwise, on older SD cards you will get lots of these messages: > > "mmc0: Got data

RE: [PATCH] mmc: sdhci-of-arasan: Add quirk to avoid erroneous msg

Hi Shawn, On 27 February 2018 14:42, Shawn Lin wrote: > On 2018/2/27 22:31, Phil Edworthy wrote: > > Hi Shawn, > > > > On 27 February 2018 14:28, Shawn Lin wrote: > >> 在 2018/2/27 21:55, Phil Edworthy 写道: > >>> Since the controller does

RE: [PATCH] pinctrl: rzn1: Fix check for used MDIO bus

HI Jacopo, On 15 October 2018 08:54 jacopo mondi wrote: > On Fri, Oct 12, 2018 at 11:40:36AM +0100, Phil Edworthy wrote: > > This fixes the check for unused mdio bus setting and the following > > static checker warning: > > drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_md

[PATCH v2] pinctrl: rzn1: Fix check for used MDIO bus

_child_count() Reported-by: Dan Carpenter Signed-off-by: Phil Edworthy --- v2: - Don't use implicit type conversion. - Fix type of return var when calling of_get_child_count(). --- drivers/pinctrl/pinctrl-rzn1.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/dri

RE: [PATCH v2] pinctrl: rzn1: Fix check for used MDIO bus

Hi Jacopo, On 15 October 2018 16:12 jacopo mondi wrote: > On Mon, Oct 15, 2018 at 04:01:47PM +0100, Phil Edworthy wrote: > > This fixes the check for unused mdio bus setting and the following > > static checker warning: > > drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_md

[PATCH] pinctrl: rzn1: Fix check for used MDIO bus

This fixes the check for unused mdio bus setting and the following static checker warning: drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select() warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter Signed-off-by: P

RE: [PATCH] pinctrl: renesas: fix platform_no_drv_owner.cocci warnings

r.cocci > > Fixes: 4e53b5004745 ("pinctrl: renesas: Renesas RZ/N1 pinctrl driver") > CC: Phil Edworthy > Signed-off-by: kbuild test robot Reviewed-by: Phil Edworthy > --- > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/gee

[PATCH v6 0/3] Renesas R9A06G032 PINCTRL Driver

the way the functions are defined so it is easy to check against the hardware numbering. v2: - Change to generic rzn1 family driver, instead of device specific. - Review comments fixed. - Fix error handling during probe Phil Edworthy (3): dt-bindings: pinctrl: renesas,rzn1-pinctrl

[PATCH v6 1/3] dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentation

The Renesas RZ/N1 device family PINCTRL node description. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy Reviewed-by: Jacopo Mondi --- v6: - Instead of combining the pin nr and func into a single element, use a pair of 8-bit elements. v5

[PATCH v6 2/3] pinctrl: renesas: Renesas RZ/N1 pinctrl driver

This provides a pinctrl driver for the Renesas RZ/N1 device family. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy Reviewed-by: Jacopo Mondi --- v6: - Instead of combining the pin nr and func into a single element, use a pair of 8-bit elements

[PATCH v6 3/3] ARM: dts: r9a06g032: Add pinctrl node

This provides a pinctrl driver for the Renesas R9A06G032 SoC Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy --- v6: - No changes. v5: - No changes. v4: - No changes. v3: - No changes. v2: - Add "renesas,rzn1-pinctrl" compatibl

RE: [PATCH v3 1/2] dt-bindings/interrupt-controller: rzn1: Add RZ/N1 gpio irq mux binding

Hi Rob, On 17 November 2018 14:33 Rob Herring wrote: > On Tue, Nov 13, 2018 at 01:09:09PM +0000, Phil Edworthy wrote: > > Add device binding documentation for the Renesas RZ/N1 GPIO interrupt > > multiplexer. > > > > Signed-off-by: Phil Edworthy > > --- >

RE: [PATCH v6 1/6] clk: Add of_clk_get_by_name_optional() function

Hi Uwe, On 16 November 2018 16:11 Uwe Kleine-König wrote: > On Fri, Nov 16, 2018 at 05:01:28PM +0100, Uwe Kleine-König wrote: > > Other than that I think the patch is fine > > Thinking again, I wonder why not just do: > > static inline struct clk *clk_get_optional(struct device *dev, const char

RE: [PATCH v6 1/6] clk: Add of_clk_get_by_name_optional() function

Hi Uwe, On 19 November 2018 10:46 Uwe Kleine-König wrote: > On Mon, Nov 19, 2018 at 10:41:42AM +0000, Phil Edworthy wrote: > > On 16 November 2018 16:11 Uwe Kleine-König wrote: > > > On Fri, Nov 16, 2018 at 05:01:28PM +0100, Uwe Kleine-König wrote: > > > > Oth

RE: [PATCH v6 1/6] clk: Add of_clk_get_by_name_optional() function

Hi Uwe, On 19 November 2018 12:58 Uwe Kleine-König wrote: > On Mon, Nov 19, 2018 at 12:53:46PM +0000, Phil Edworthy wrote: > > On 19 November 2018 10:46 Uwe Kleine-König wrote: > > > On Mon, Nov 19, 2018 at 10:41:42AM +0000, Phil Edworthy wrote: > > &g

[PATCH] clk: Add (devm_)clk_get_optional() functions

clk_prepare_enable, etc to be called on the returned reference without additional checks. Signed-off-by: Phil Edworthy --- v7: - Instead of messing with the core functions, simply wrap them for the _optional() versions. By putting clk_get_optional() inline in the header file, we can get rid

[PATCH] pinctrl: rzn1: Fix check for used MDIO bus

_child_count() Reported-by: Dan Carpenter Signed-off-by: Phil Edworthy --- v2: - Don't rely on rely on the implicit typecast from -1 to uint --- drivers/pinctrl/pinctrl-rzn1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rzn1.c b/drivers/pinctrl/