Re: [PATCH 3/6] pinctrl: sh-pfc: r8a77990: Add bias pinconf support

2018-05-15 Thread Geert Uytterhoeven 
On Mon, May 14, 2018 at 10:13 PM, Geert Uytterhoeven
 wrote:
> On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
>  wrote:
>> From: Takeshi Kihara 
>>
>> This patch implements control of pull-up and pull-down. On this SoC there
>> is no simple mapping of GP pins to bias register bits, so we need a table.
>>
>> Signed-off-by: Takeshi Kihara 
>> Signed-off-by: Yoshihiro Shimoda 
>
> Thanks for your patch!
>
>> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>
>> @@ -1227,10 +1248,55 @@ enum {
>>
>> PINMUX_IPSR_GPSR(IP15_31_28,USB30_OVC),
>> PINMUX_IPSR_MSEL(IP15_31_28,USB0_OVC_A, 
>> SEL_USB_20_CH0_0),
>> +
>> +/*
>> + * Static pins can not be muxed between different functions but
>> + * still needs a mark entry in the pinmux list. Add each static
>
> need mark entries
>
>> + * pin to the list without an associated function. The sh-pfc
>> + * core will do the right thing and skip trying to mux then pin
>
> mux the pin
>
>> + * while still applying configuration to it
>
> period
>
> I have just sent a patch to fix the other copies, in the hope these grammar
> atrocities will stop spreading ;-)
>
>> @@ -1708,8 +1774,263 @@ enum {
>> { },
>>  };
>>
>> +static const struct pinmux_bias_reg pinmux_bias_regs[] = {
>
> The register definitions look OK to me.
> I'll review the actual pin mappings later.

Reviewed-by: Geert Uytterhoeven 
i.e. will queue in sh-pfc-for-v4.18 with the comments fixed.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 3/6] pinctrl: sh-pfc: r8a77990: Add bias pinconf support

2018-05-14 Thread Geert Uytterhoeven 
Hi Shimoda-san,

On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
 wrote:
> From: Takeshi Kihara 
>
> This patch implements control of pull-up and pull-down. On this SoC there
> is no simple mapping of GP pins to bias register bits, so we need a table.
>
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Shimoda 

Thanks for your patch!

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c

> @@ -1227,10 +1248,55 @@ enum {
>
> PINMUX_IPSR_GPSR(IP15_31_28,USB30_OVC),
> PINMUX_IPSR_MSEL(IP15_31_28,USB0_OVC_A, 
> SEL_USB_20_CH0_0),
> +
> +/*
> + * Static pins can not be muxed between different functions but
> + * still needs a mark entry in the pinmux list. Add each static

need mark entries

> + * pin to the list without an associated function. The sh-pfc
> + * core will do the right thing and skip trying to mux then pin

mux the pin

> + * while still applying configuration to it

period

I have just sent a patch to fix the other copies, in the hope these grammar
atrocities will stop spreading ;-)

> @@ -1708,8 +1774,263 @@ enum {
> { },
>  };
>
> +static const struct pinmux_bias_reg pinmux_bias_regs[] = {

The register definitions look OK to me.
I'll review the actual pin mappings later.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 3/6] pinctrl: sh-pfc: r8a77990: Add bias pinconf support

2018-05-10 Thread Yoshihiro Shimoda 
From: Takeshi Kihara 

This patch implements control of pull-up and pull-down. On this SoC there
is no simple mapping of GP pins to bias register bits, so we need a table.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 340 +-
 1 file changed, 331 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 0af2fef..1fe8aee 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -16,15 +16,17 @@
 #include "core.h"
 #include "sh_pfc.h"
 
-#define CPU_ALL_PORT(fn, sfx)  \
-   PORT_GP_18(0, fn, sfx), \
-   PORT_GP_23(1, fn, sfx), \
-   PORT_GP_26(2, fn, sfx), \
-   PORT_GP_16(3, fn, sfx), \
-   PORT_GP_11(4, fn, sfx), \
-   PORT_GP_20(5, fn, sfx), \
-   PORT_GP_18(6, fn, sfx)
-
+#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
+  SH_PFC_PIN_CFG_PULL_DOWN)
+
+#define CPU_ALL_PORT(fn, sfx) \
+   PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
 /*
  * F_() : just information
  * FM() : macro for FN_xxx / xxx_MARK
@@ -461,6 +463,17 @@
 MOD_SEL0_2 \
 MOD_SEL0_1_0
 
+/*
+ * These pins are not able to be muxed but have other properties
+ * that can be set, such as pull-up/pull-down enable.
+ */
+#define PINMUX_STATIC \
+   FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
+   FM(AVB_TD3) \
+   FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
+   FM(ASEBRK) \
+   FM(MLB_REF)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -485,6 +498,7 @@ enum {
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
+   PINMUX_STATIC
PINMUX_MARK_END,
 #undef F_
 #undef FM
@@ -493,6 +507,13 @@ enum {
 static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
 
+   PINMUX_SINGLE(CLKOUT),
+   PINMUX_SINGLE(AVB_PHY_INT),
+   PINMUX_SINGLE(AVB_RD3),
+   PINMUX_SINGLE(AVB_RXC),
+   PINMUX_SINGLE(AVB_RX_CTL),
+   PINMUX_SINGLE(QSPI0_SSL),
+
/* IPSR0 */
PINMUX_IPSR_GPSR(IP0_3_0,   QSPI0_SPCLK),
PINMUX_IPSR_MSEL(IP0_3_0,   HSCK4_A,SEL_HSCIF4_0),
@@ -1227,10 +1248,55 @@ enum {
 
PINMUX_IPSR_GPSR(IP15_31_28,USB30_OVC),
PINMUX_IPSR_MSEL(IP15_31_28,USB0_OVC_A, 
SEL_USB_20_CH0_0),
+
+/*
+ * Static pins can not be muxed between different functions but
+ * still needs a mark entry in the pinmux list. Add each static
+ * pin to the list without an associated function. The sh-pfc
+ * core will do the right thing and skip trying to mux then pin
+ * while still applying configuration to it
+ */
+#define FM(x)   PINMUX_DATA(x##_MARK, 0),
+   PINMUX_STATIC
+#undef FM
 };
 
+/*
+ * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
+ * Physical layout rows: A - AE, cols: 1 - 25.
+ */
+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+#define PIN_NONE U16_MAX
+
 static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+
+   /*
+* Pins not associated with a GPIO port.
+*
+* The pin positions are different between different R8A77990
+* packages, all that is needed for the pfc driver is a unique
+* number for each pin. To this end use the pin layout from
+* R8A77990 to calculate a unique number for each pin.
+*/
+   SH_PFC_PIN_NAMED_CFG('F',  1, TRST_N,   CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('F',  3, TMS,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('F',  4, TCK,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('G',  2, TDI,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('G',  3, FSCLKST_N,CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('H',  1, ASEBRK,   CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  1, AVB_TXC,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  2, AVB_TD0,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  3, AVB_TD1,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  5, AVB_TD2,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  6, AVB_TD3,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('P',  3, AVB_TX_CTL,   CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('P',  4, AVB_MDIO, CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('P',  5, AVB_MDC,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF,  CFG_FLAGS),
+