A. Hi Geert,
Am Freitag, den 21.10.2016, 15:17 +0200 schrieb Geert Uytterhoeven:
> Hi Philipp, Mike, Stephen, Simon, Magnus,
> (see questions *** below!)
>
> Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
> state of the mode pins either by a call from the
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
.
Signed-off-by: Sergei Shtylyov
Hi Magnus,
On 20/10/16 00:36, Magnus Damm wrote:
> From: Magnus Damm
>
> Not all architectures have an iommu member in their archdata, so
> use #ifdefs support build wit COMPILE_TEST on any architecture.
As an alternative to this we could now use iommu_fwspec in
On 20/10/16 00:36, Magnus Damm wrote:
> From: Magnus Damm
>
> Introduce an alternative set of iommu_ops suitable for 64-bit ARM
> as well as 32-bit ARM when CONFIG_IOMMU_DMA=y. Also adjust the
> Kconfig to depend on ARM or IOMMU_DMA.
>
> Signed-off-by: Magnus Damm
Add the initial device tree for the R8A7743 SoC based SK-RZG1M board.
The board has one debug serial port (SCIF0); include support for it, so
that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
.
Signed-off-by: Sergei
> For the VERSION register, the low byte is the version of the IP, but
> the upper byte is a number that the design group that made the part
I know. It is just that I haven't seen this one "in the wild" so far.
> > This SWAP register exists on R-Car as well. Out of curiosity, what is the
> >
The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, CPG,
and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
.
Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert
Describe SYS-DMAC0/1 in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
.
Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
---
Changes in version 4:
Describe [H]SCIF{|A|B} ports in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin
.
Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
---
Changes in
Define the generic R8A7743 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
.
Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
---
Changes in
Define the SK-RZG1M board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin
.
Signed-off-by: Sergei Shtylyov
Reviewed-by:
Describe the IRQC interrupt controller in the R8A7743 device tree.
Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
---
Changes in version 4:
- refreshed the patch;
- added Geert's tag.
Changes in version 3:
- updated
On Friday, October 21, 2016 8:01:49 PM CEST Geert Uytterhoeven wrote:
> > diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
> > index 90dd0db7d9c6..762d122eddec 100644
> > --- a/drivers/clk/renesas/Makefile
> > +++ b/drivers/clk/renesas/Makefile
> > @@ -4,11 +4,7 @@
On Friday, October 21, 2016 8:16:00 PM CEST Geert Uytterhoeven wrote:
> On Wed, Oct 19, 2016 at 12:59 PM, Arnd Bergmann wrote:
> > On Wednesday, October 19, 2016 10:02:57 AM CEST Geert Uytterhoeven wrote:
> >> On Mon, Oct 10, 2016 at 4:23 PM, Arnd Bergmann wrote:
>
As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property,
but no unit name
Signed-off-by: Geert
As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi
as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property,
but no unit name
Signed-off-by: Geert
Hi Geert,
Thank you for the review comments.
> On Wed, Oct 12, 2016 at 4:10 PM, Ramesh Shanmugasundaram
> wrote:
> > This patch adds Digital Radio Interface (DRIF) support to R-Car Gen3
> SoCs.
> > The driver exposes each instance of DRIF as a V4L2 SDR
The R-Car H1 board code no longer calls r8a7779_clocks_init().
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- New.
---
drivers/clk/renesas/clk-r8a7779.c | 9 -
include/linux/clk/renesas.h
e "renesas,-rst" instead of "renesas,rst-",
- Drop "syscon" compatible value and "renesas,modemr" property, use a
real driver instead,
- Add support for R-Car M1A, H1, and M3-W.
Changes compared to v1:
- Add support for R-Car H3.
This patch serie
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- New.
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5
The R-Car M1A board code no longer calls r8a7778_clocks_init().
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- New.
---
drivers/clk/renesas/clk-r8a7778.c | 13 -
include/linux/clk/renesas.h
On 04/10/16 15:31, Laurent Pinchart wrote:
> The node pointer passed to the display timing functions is never
> modified, make it const.
>
> Signed-off-by: Laurent Pinchart
> ---
> drivers/video/of_display_timing.c | 6 +++---
>
> > > * Does it have a version register (CTL_VERSION)? If so, what does it
> > > say?
> >
> > 0x820B
>
> Okay, this is a version I have not seen before.
The SDHI IP came from the SH7269 (SH-2A device).
For the VERSION register, the low byte is the version of the IP, but the upper
byte is a
Hi Laurent,
Thank you for the review comments.
> On Tuesday 18 Oct 2016 16:29:24 Geert Uytterhoeven wrote:
> > On Wed, Oct 12, 2016 at 4:10 PM, Ramesh Shanmugasundaram wrote:
> > > This patch adds Digital Radio Interface (DRIF) support to R-Car Gen3
> SoCs.
> > > The driver exposes each instance
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- Use "renesas,-rst" instead of "renesas,rst-",
- Drop
Add a driver for the Renesas R-Car Gen1 RESET/WDT and R-Car Gen2/Gen3
and RZ/G RST module.
For now this driver just provides an API to obtain the state of the mode
pins, as latched at reset time. As this is typically called from the
probe function of a clock driver, which can run much earlier
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- Use "renesas,-rst" instead of "renesas,rst-",
- Drop
Add a device node for the RESET/WDT module, which provides a.o. reset
control, mode pin monitoring, and watchdog control.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- New.
---
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
Reviewed-by: Laurent Pinchart
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- New.
---
Now the R-Car M1A CPG clock driver obtains the state of the mode pins
from the R-Car RST driver, there's no longer a need to pass this state
explicitly. Hence we can just remove the .init_time() callback, the
generic ARM code will take care of calling of_clk_init().
Signed-off-by: Geert
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
Reviewed-by: Laurent Pinchart
All R-Car Gen3 clock drivers now obtain the values of the mode pins from
the R-Car RST driver.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
Reviewed-by: Laurent Pinchart
---
v4:
- Add Acked-by,
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven
---
v4:
- New.
---
arch/arm/boot/dts/r8a7792.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- Use "renesas,-rst" instead of "renesas,rst-",
- Drop
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RESET/WDT module.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- New.
---
Now the R-Car H1 CPG clock driver obtains the state of the mode pins
from the R-Car RST driver, there's no longer a need to pass this state
explicitly. Hence we can just remove the .init_time() callback, the
generic ARM code will take care of calling of_clk_init() and
clocksource_probe().
Now the R-Car Gen2 CPG clock driver obtains the state of the mode pins
from the R-Car RST driver, there's no longer a need to pass this state
explicitly. Hence we can just call of_clk_init() instead.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
The R-Car Gen2 board code no longer calls rcar_gen2_clocks_init().
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- Rebased,
v2:
- No changes.
---
drivers/clk/renesas/clk-rcar-gen2.c | 7 ---
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Fall back to our own private copy of rcar_gen2_read_mode_pins() for
backward-compatibility with old DTs.
Signed-off-by: Geert Uytterhoeven
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven
Acked-by: Dirk Behme
---
v4:
- Add Acked-by,
v3:
- Use "renesas,-rst" instead of "renesas,rst-",
- Drop
DU0 uses an externally provided clock, but the corresponding pin isn't
correctly muxed. Fix it.
Signed-off-by: Laurent Pinchart
---
arch/arm/boot/dts/r8a7779-marzen.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Along with the DU reg fix
On 09/08/16 00:25, Laurent Pinchart wrote:
The menu control selects the operation mode of a video deinterlacer. The
menu entries are driver specific.
Signed-off-by: Laurent Pinchart
---
Documentation/media/uapi/v4l/extended-controls.rst | 4
Hi Laurent,
Thank you for the review comments.
> On Wednesday 12 Oct 2016 15:10:25 Ramesh Shanmugasundaram wrote:
> > This patch adds driver support for MAX2175 chip. This is Maxim
> > Integrated's RF to Bits tuner front end chip designed for
> > software-defined radio solutions. This driver
On 10/21/2016 03:52 PM, Laurent Pinchart wrote:
Hi Archit,
On Friday 21 Oct 2016 10:43:34 Archit Taneja wrote:
On 10/19/2016 07:55 PM, Laurent Pinchart wrote:
The ADV7123 is a transparent VGA DAC. Unlike dumb VGA DACs it can be
controlled through a power save pin, and requires a power
On 19.10.2016 11:50, Yoshihiro Shimoda wrote:
This patch set is based on the latest Greg's usb.git / usb-next branch.
(commit id = 1001354ca34179f3db924eb66672442a173147dc)
Changes from v1:
- Revise the comment in patch 1.
- Don't add a new macro because the macro will be not used in the
Hi Archit,
On Friday 21 Oct 2016 10:43:34 Archit Taneja wrote:
> On 10/19/2016 07:55 PM, Laurent Pinchart wrote:
> > The ADV7123 is a transparent VGA DAC. Unlike dumb VGA DACs it can be
> > controlled through a power save pin, and requires a power supply.
> > However, on most boards where the
Hi Archit,
On Friday 21 Oct 2016 10:51:59 Archit Taneja wrote:
> On 10/19/2016 07:55 PM, Laurent Pinchart wrote:
> > The LVDS encoder driver is a DRM bridge driver that supports the
> > parallel to LVDS encoders that don't require any configuration. The
> > driver thus doesn't interact with the
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