On 18 January 2017 at 18:25, Chris Brandt wrote:
> In the case of a single clock source, you don't need names. However,
> if the controller has 2 clock sources, you need to name them correctly
> so the driver can find the 2nd one.
>
> Signed-off-by: Chris Brandt
Since the driver is now merged into next, we can add the DTS snipplets as well.
Changes from V6:
* rebased to latest renesas/arm64-dt-for-v4.11
* changed critical temp from 90° to 120° which is the state in the latest BSP
Wolfram Sang (2):
arm64: dts: r8a7795: Add R-Car Gen3 thermal support
Signed-off-by: Hien Dang
Signed-off-by: Thao Nguyen
Signed-off-by: Khiem Nguyen
Signed-off-by: Niklas Söderlund
Acked-by: Eduardo Valentin
Signed-off-by: Hien Dang
Signed-off-by: Thao Nguyen
Signed-off-by: Khiem Nguyen
Signed-off-by: Niklas Söderlund
Acked-by: Eduardo Valentin
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that all resets added
Hi all,
This patch series adds reset control support to the Renesas Clock Pulse
Generator / Module Standby and Software Reset module, on the R-Car H3
and M3-W, RZ/G1M, and RZ/G1E SoCs.
- Patch 1 amends the Renesas CPG/MSSR DT bindings for reset control,
- Patches 2-4 add reset
Document properties needed to use the Reset Control feature of the
Renesas Clock Pulse Generator / Module Standby and Software Reset
module.
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 6 ++
1 file changed, 6
Add optional support for the Reset Control feature of the Renesas Clock
Pulse Generator / Module Standby and Software Reset module on R-Car
Gen2, R-Car Gen3, and RZ/G1 SoCs.
This allows to reset SoC devices using the Reset Controller API.
Signed-off-by: Geert Uytterhoeven
Hi Geert,
On Friday, January 20, 2017, Geert Uytterhoeven wrote:
> It takes longer to boot, though. I guess due to more kernel output?
You can see there is a jump in the time when the system clocksource changes
from mtu2 to ostm.
[0.079591] clocksource: Switched to clocksource ostm
[
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that all resets added
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that all resets added
The spinlock is used to protect Read-Modify-Write register accesses,
which won't be limited to SMSTPCR register accesses.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/renesas-cpg-mssr.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
The Renesas CPG/MSSR driver is already in active use for RZ/G1 since
commits c0b2d75d2a4bf6a3 ("clk: renesas: cpg-mssr: Add R8A7743 support")
and 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support").
Signed-off-by: Geert Uytterhoeven
---
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.
Signed-off-by:
Some controllers have 2 clock sources instead of 1. The 2nd clock
is for the internal card detect logic and must be enabled/disabled
along with the main core clock for proper operation.
Signed-off-by: Chris Brandt
---
v3:
* add more clarification to the commit log
v2:
*
In the case of a single clock source, you don't need names. However,
if the controller has 2 clock sources, you need to name them correctly
so the driver can find the 2nd one. The 2nd clock is for the internal
card detect logic and must be enabled/disabled along with the main
core clock.
At first this started out as a simple typo fix, until I realized
that the SDHI in the RZ/A1 has 2 clocks per channel and both need
to be turned on/off.
This patch series adds the ability to specify 2 clocks instead of
just 1, and does so for the RZ/A1 r7s72100.
This patch has been tested on an
On 01/17, Geert Uytterhoeven wrote:
> INTC-SYS is the module clock for the GIC. Accessing the GIC while it is
> disabled causes:
>
> Unhandled fault: asynchronous external abort (0x1211) at 0x
>
> Currently, the GIC-400 driver cannot enable its module clock for several
> reasons:
>
On 01/13, Geert Uytterhoeven wrote:
> Hi Mike, Stephen,
>
> The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
>
> Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
>
> are available in the git repository at:
>
>
On 01/21/2017 01:12 AM, Stephen Boyd wrote:
> On 01/12, Marek Vasut wrote:
>> Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
>> chips have two clock inputs, XTAL or CLK, which are muxed into single
>> PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
>>
On 01/10, Kuninori Morimoto wrote:
> From: Khiem Nguyen
>
> CS2000 needs re-setup when redume, otherwise, it can't
> handle correct clock rate.
>
> Signed-off-by: Khiem Nguyen
> [Kuninori: cleanup original patch]
>
On 01/12, Marek Vasut wrote:
> Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
> chips have two clock inputs, XTAL or CLK, which are muxed into single
> PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
> while the 5P49V5923 requires external XTAL.
>
> The
At first this started out as a simple typo fix, until I realized
that the SDHI in the RZ/A1 has 2 clocks per channel and both need
to be turned on/off.
This patch series adds the ability to specify 2 clocks instead of
just 1, and does so for the RZ/A1 r7s72100.
This patch has been tested on an
In the case of a single clock source, you don't need names. However,
if the controller has 2 clock sources, you need to name them correctly
so the driver can find the 2nd one. The 2nd clock is for the internal
card detect logic.
Signed-off-by: Chris Brandt
---
v4:
*
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.
Signed-off-by:
> It sounds like your suggestion is to just put the HW description in
> the DT bindings, but move the dirty details into the driver.
>
> Keep in DT:
>
> +- clocks: Most controllers only have 1 clock source per channel. However, on
> + some variations of this controller, the internal card
> > Is this clock solely about card detection? So in cases when you have a
> > GPIO card detect, the clock isn't needed?
> >
> > Just trying to understand things a bit better...
>
> According to the hardware manual, enabling the "core" clock but not the
> "cd" clock is not a valid setting. So
Signed-off-by: Chris Brandt
---
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/timer/renesas,ostm.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644
This patch set adds a new clocksource driver that uses the OS Timer
(OSTM) that exists in the R7S72100 (RZ/A1) SoC.
The operation of the driver was tested with a simple user application
that does multiple calls to nanosleep() and gettimeofday().
The purpose of adding this driver is to get better
This patch adds a OSTM driver for the Renesas architecture.
Signed-off-by: Chris Brandt
---
v2:
* changed implementation to be independent channel nodes
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig| 12 ++
On 01/17, Geert Uytterhoeven wrote:
> When the Renesas CPG/MSSR driver was introduced, it was anticipated that
> critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag
> soon. However, CLK_ENABLE_HAND_OFF never made it upstream.
>
> Instead, commit 32b9b10961860860 ("clk: Allow
On 01/17, Geert Uytterhoeven wrote:
> Hi Mike, Stephen,
>
> This patch series adds support for the CLK_IS_CRITICAL flag to drivers
> for module clocks on Renesas ARM SoCs. For now, this is used to prevent
> disabling of the ARM GIC module clock, which would lead to a system
> lock-up when
Signed-off-by: Chris Brandt
---
v2:
* remove part that was supposed to go in dsti
* now there is a node for each channel
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r7s72100.dtsi| 9 +
include/dt-bindings/clock/r7s72100-clock.h | 4
2 files changed, 13 insertions(+)
diff --git
Signed-off-by: Chris Brandt
---
v2:
* wrap clock lines to avoid 80 char max
* split into 2 separate channel nodes
---
arch/arm/boot/dts/r7s72100.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi
This patch set enables the use of the newly created driver
renesas-ostm.c for the r7s72100 SoC.
v2:
* The biggest change was now the channels are independent of each
other and have separate nodes in the DT. The first probed will
be set up as a clock source, and any additional channels probed
On 01/20, Geert Uytterhoeven wrote:
> Document properties needed to use the Reset Control feature of the
> Renesas Clock Pulse Generator / Module Standby and Software Reset
> module.
>
> Signed-off-by: Geert Uytterhoeven
Subject should be "dt-bindings: clock:" ?
--
On 01/20, Geert Uytterhoeven wrote:
> The Renesas CPG/MSSR driver is already in active use for RZ/G1 since
> commits c0b2d75d2a4bf6a3 ("clk: renesas: cpg-mssr: Add R8A7743 support")
> and 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support").
>
> Signed-off-by: Geert Uytterhoeven
On 01/20, Geert Uytterhoeven wrote:
> The spinlock is used to protect Read-Modify-Write register accesses,
> which won't be limited to SMSTPCR register accesses.
>
> Signed-off-by: Geert Uytterhoeven
> ---
Acked-by: Stephen Boyd
--
Qualcomm
On 01/20, Geert Uytterhoeven wrote:
> Add optional support for the Reset Control feature of the Renesas Clock
> Pulse Generator / Module Standby and Software Reset module on R-Car
> Gen2, R-Car Gen3, and RZ/G1 SoCs.
>
> This allows to reset SoC devices using the Reset Controller API.
>
>
Hello Ulf,
On Friday, January 20, 2017, Ulf Hansson wrote:
> On 18 January 2017 at 18:25, Chris Brandt
> wrote:
> > Some controllers have 2 clock sources instead of 1, so they both need
> > to be turned on/off.
>
> This doesn't tell me enough. Please elaborate.
>
>
> Add this to my tree and to my linux-next branch. However, as usual, I am
Thanks!
> taking the driver+docs, the dt binding must go through your arch tree,
Yes, sure. I do the same in the I2C subsystem.
> Acked-by: Eduardo Valentin
Done. Will resend the DTS patches in a
Dear Dong,
On Friday 20 Jan 2017 12:11:50 DongCV wrote:
> Dear Mr Laurent,
>
> Thank you for your quick reply.
> This is the log file contains information about the command "modetest -M
> rcar-du" (with the HDMI cable plugged).
Thank you. I think I know what's wrong. The default mode picked by
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +--
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c
b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index
On 20 January 2017 at 17:05, Chris Brandt wrote:
> Hello Ulf,
>
> Friday, January 20, 2017, Ulf Hansson wrote:
>> > +- clocks: Most controllers only have 1 clock source per channel.
>> However, some
>> > + have a second clock dedicated to card detection. If 2
Hello Ulf,
Friday, January 20, 2017, Ulf Hansson wrote:
> > +- clocks: Most controllers only have 1 clock source per channel.
> However, some
> > + have a second clock dedicated to card detection. If 2 clocks
> are
> > + specified, you must name them as "core" and "cd". If the
>
Hi Geert,
On Fri, 2017-01-20 at 15:08 +0100, Geert Uytterhoeven wrote:
> Add optional support for the Reset Control feature of the Renesas Clock
> Pulse Generator / Module Standby and Software Reset module on R-Car
> Gen2, R-Car Gen3, and RZ/G1 SoCs.
Is there a reason to make this optional?
>
On 01/20/2017 04:04 PM, Geert Uytterhoeven wrote:
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +--
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git
Hi Philipp,
On Fri, Jan 20, 2017 at 4:57 PM, Philipp Zabel wrote:
> On Fri, 2017-01-20 at 15:08 +0100, Geert Uytterhoeven wrote:
>> Add optional support for the Reset Control feature of the Renesas Clock
>> Pulse Generator / Module Standby and Software Reset module on
On 01/15/2017 09:21 PM, Marek Vasut wrote:
> On 01/15/2017 08:53 PM, Jonathan Cameron wrote:
>> On 15/01/17 17:06, Marek Vasut wrote:
>>> On 01/15/2017 05:28 PM, Jonathan Cameron wrote:
On 15 January 2017 15:47:31 GMT+00:00, Marek Vasut
wrote:
> On
Hello Uffe,
On Friday, January 20, 2017, Ulf Hansson wrote:
> > The reality is that the chip guys cut up the standard SDHI IP to add a
> > 'cool new feature', but all I want to do is put it back the way it was.
> >
> > NOTE: The design guys like to reuse IP blocks from previous designs
> > that
On 18 January 2017 at 18:25, Chris Brandt wrote:
> Some controllers have 2 clock sources instead of 1, so they both need
> to be turned on/off.
This doesn't tell me enough. Please elaborate.
For example, tell how you treat the clocks, which of them that is
optional and
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