Hi Jacopo,
On Thursday, January 26, 2017, jacopo mondi wrote:
> > I think we should try to avoid the rz naming as much as possible since
> > this driver will hopefully be useful for other future Renesas devices
> > if they move to a similar pin-control type method. Maybe future "R-car"
> SoCs?
>
On Thursday, January 26, 2017, Rob Herring wrote:
> >> > +
> >> > +Example showing 2 clocks:
> >> > + sdhi0: sd@e804e000 {
> >>
> >> mmc@...
> >
> > I'm confused. I see that for all SDHI controllers, it either "sd@" or
> "sdhci@".
> >
> > $ grep sdhi $(find arch/arm/boot/dts -name "*.dtsi")
> >
A V4L2 driver for Renesas R-Car MIPI CSI-2 receiver. The driver
supports the rcar-vin driver on R-Car Gen3 SoCs where separate CSI-2
hardware blocks are connected between the video sources and the video
grabbers (VIN).
Driver is based on a prototype by Koji Matsuoka in the Renesas BSP.
Hi,
This is the latest incarnation of R-Car MIPI CSI-2 receiver driver. It's
based on top of v4.10-rc1 and are tested on Renesas Salvator-X together
with the out of tree patches for rcar-vin to add support for Gen3 VIN
and a prototype driver for ADV7482. If anyone is interested to test
video
Documentation for Renesas R-Car MIPI CSI-2 receiver. The CSI-2 receivers
are located between the video sources (CSI-2 transmitters) and the video
grabbers (VIN) on Gen3 of Renesas R-Car SoC.
Each CSI-2 device is connected to more then one VIN device which
simultaneously can receive video from the
On Thu, Jan 26, 2017 at 03:16:57PM +0100, Wolfram Sang wrote:
>
> > I have tested with "the new mmc/next" and things seem better.
>
> Good. The issue you saw is expected when you have not the enablement
> patches in place.
>
> > I am still of a mind to drop the M3-W patch of this series because
From: Vladimir Barinov
This patch updates memory region:
- After changes, the new map of the m3ulcb board on R8A7796 SoC
Bank0: 1GiB RAM : 0x4800 -> 0x0007fff
Bank1: 1GiB RAM : 0x0006 -> 0x0063fff
- Before
From: Vladimir Barinov
This supports I2C2 bus on M3ULCB board
Signed-off-by: Vladimir Barinov
---
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 12
1 file changed, 12 insertions(+)
diff
From: Vladimir Barinov
This patch adds memory region:
- After changes, the H3ULCB board has the following map:
Bank0: 1GiB RAM : 0x4800 -> 0x0007fff
Bank1: 1GiB RAM : 0x0005 -> 0x0053fff
Bank2: 1GiB RAM :
From: Vladimir Barinov
This supports HS200 mode for eMMC on H3ULCB board
Signed-off-by: Vladimir Barinov
---
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 1 +
1 file changed, 1 insertion(+)
diff
Hello,
This adds the folowing:
- R8A7795 SoC based H3ULCB board peripherals
Vladimir Barinov (2):
[1/2] arm64: dts: h3ulcb: Update memory node to 4 GiB map
[2/2] arm64: dts: h3ulcb: enable HS200 for eMMC
---
This patchset is against the 'kernel/git/horms/renesas.git' repo.
Hello,
This adds the folowing:
- R8A7796 SoC based M3ULCB board peripherals
Vladimir Barinov (4):
[1/4] arm64: dts: m3ulcb: enable I2C
[2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
[3/4] arm64: dts: m3ulcb: enable EthernetAVB
[4/4] arm64: dts: m3ulcb: enable HS200 for eMMC
---
This
> The issue happened with renesas-devel, i.e. without those patches.
> It was mentioned during last core meeting, so have a look at that log.
No need to. As I said, the behaviour is expected without the patches.
Thanks for the update!
signature.asc
Description: PGP signature
From: Vladimir Barinov
This supports Ethernet AVB on M3ULCB board
Signed-off-by: Vladimir Barinov
---
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 32 ++
1 file changed, 32
From: Vladimir Barinov
This supports HS200 mode for eMMC on M3ULCB board
Signed-off-by: Vladimir Barinov
---
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 1 +
1 file changed, 1 insertion(+)
diff
Hi Wolfram,
On Thu, Jan 26, 2017 at 11:03 AM, Wolfram Sang wrote:
> On Thu, Jan 26, 2017 at 11:01:17AM +0100, Simon Horman wrote:
>> On Fri, Jan 13, 2017 at 09:39:28AM +0100, Wolfram Sang wrote:
>> > > Sorry for missing these.
>> > > I have queued them up for v4.11.
>> >
>> >
From: Kazuya Mizuguchi
"swiotlb buffer is full" errors occur after repeated initialisation of a
device - f.e. suspend/resume or ip link set up/down. This is because memory
mapped using dma_map_single() in ravb_ring_format() and ravb_start_xmit()
is not released.
Hi Robin,
On Thu, Jan 26, 2017 at 12:23 PM, Robin Murphy wrote:
> On 26/01/17 09:53, Geert Uytterhoeven wrote:
>> Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses
>> only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force
>> a 32-bit
> > Do you already fetch from Ulf's kernel.org tree? He switched away from
> > the Linaro tree for MMC for a while. I only realized when he complained
"since a while" not "for a while", of course.
> Thanks, I had not realised that. I've pulled the kernel.org tree.
So, there is hope for the
On Thu, Jan 26, 2017 at 03:58:45PM +0300, Sergei Shtylyov wrote:
> On 01/26/2017 02:04 PM, Simon Horman wrote:
>
> >From: Kazuya Mizuguchi
> >
> >"swiotlb buffer is full" errors occur after repeated initialisation of a
> >device - f.e. suspend/resume or ip link
On Thursday, January 26, 2017, Wolfram Sang wrote:
> Subject: Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100
> clocks
>
>
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
>
> Can you add my tags as well. They
Hi Simon,
On Thursday, January 26, 2017, Simon Horman wrote:
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
>
> Thanks, I will take care of the 3rd patch.
>
> Chris, is it safe to apply the 3rd patch without the first 2
Hi Daniel,
On Thursday, January 26, 2017, Daniel Lezcano wrote:
> > ---
> > v3:
> > * Added more details to commit log
> > * Kconfig: SYS_SUPPORTS_RENESAS_OSTM to just RENESAS_OSTM
> > * removed all MODULE code (this driver is builtin only)
> > * removed items from 'struct ostm_device'
> > *
Hi Niklas,
On Thu, Jan 26, 2017 at 2:12 PM, Niklas Söderlund
wrote:
> diff --git a/drivers/media/v4l2-core/v4l2-of.c
> b/drivers/media/v4l2-core/v4l2-of.c
> index 93b33681776c..1042db6bb996 100644
> --- a/drivers/media/v4l2-core/v4l2-of.c
> +++
> > Do you have the HS200 enablement patches in that branch? They are
> > currently in -next.
>
> I tried mmc/next (but didn't notice anything special there).
> Which patches should I be looking for?
The series starting with 59c21074b582aa ("mmc: sh_mobile_sdhi: simplify
accessing DT data") up
Hi Wolfram,
On Thu, Jan 26, 2017 at 3:16 PM, Wolfram Sang wrote:
>> I have tested with "the new mmc/next" and things seem better.
>
> Good. The issue you saw is expected when you have not the enablement
> patches in place.
>
>> I am still of a mind to drop the M3-W patch of
On Mon, Jan 23, 2017 at 11:56 AM, Chris Brandt wrote:
> Hello Rob,
>
>
> On Monday, January 23, 2017, Rob Herring wrote:
>> > --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
>> > +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
>> > @@ -25,8 +25,32 @@
From: Kazuya Mizuguchi
"swiotlb buffer is full" errors occur after repeated initialisation of a
device - f.e. suspend/resume or ip link set up/down. This is because memory
mapped using dma_map_single() in ravb_ring_format() and ravb_start_xmit()
is not released.
> I have tested with "the new mmc/next" and things seem better.
Good. The issue you saw is expected when you have not the enablement
patches in place.
> I am still of a mind to drop the M3-W patch of this series because unless
> we can control the order that things are merged into Linus's tree
On 26/01/17 09:53, Geert Uytterhoeven wrote:
> Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses
> only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force
> a 32-bit IOVA space through the IOMMU Domain Geometry.
>
> Hence if a device (e.g. SYS-DMAC) rightfully
On 01/26/2017 02:04 PM, Simon Horman wrote:
From: Kazuya Mizuguchi
"swiotlb buffer is full" errors occur after repeated initialisation of a
device - f.e. suspend/resume or ip link set up/down. This is because memory
mapped using dma_map_single() in
All lines in data-lanes and clock-lanes properties must be unique.
Instead of drivers checking for this add it to the generic parser.
Signed-off-by: Niklas Söderlund
---
drivers/media/v4l2-core/v4l2-of.c | 18 +-
1 file changed, 17
On Thu, Jan 26, 2017 at 12:36:57PM +0100, Wolfram Sang wrote:
>
> > > Do you have the HS200 enablement patches in that branch? They are
> > > currently in -next.
> >
> > I tried mmc/next (but didn't notice anything special there).
> > Which patches should I be looking for?
>
> The series
On Thu, Jan 26, 2017 at 02:54:53PM +0100, Wolfram Sang wrote:
>
> > > Do you already fetch from Ulf's kernel.org tree? He switched away from
> > > the Linaro tree for MMC for a while. I only realized when he complained
>
> "since a while" not "for a while", of course.
>
> > Thanks, I had not
On 01/26/2017 04:29 PM, Simon Horman wrote:
From: Kazuya Mizuguchi
Well, Kazuya's patch is so far from your now, you could have said it was
reported by him or that your patch is loosely based on his one. :-)
"swiotlb buffer is full" errors occur after
Just some very minor nits... Probably not worth the resend.
On Mon, Jan 16, 2017 at 01:12:45PM +0100, Jacopo Mondi wrote:
> From: Magnus Damm
>
> Squash commits in Geert's renesas-driver/genmai-gpio-and-pfc branch that
> add support for r7s72100 PFC.
> This squash combines
This patch adds a OSTM driver for the Renesas architecture.
The OS Timer (OSTM) has independent channels that can be
used as a freerun or interval times.
This driver uses the first probed device as a clocksource
and then any additional devices as clock events.
Signed-off-by: Chris Brandt
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
This patch set adds a new clocksource driver that uses the OS Timer
(OSTM) that exists in the R7S72100 (RZ/A1) SoC.
The operation of the driver was tested with a simple user application
that does multiple calls to nanosleep() and gettimeofday().
The purpose of adding this driver is to get better
Dear Stefan,
Cc: Geert,
I've tested the linux v4.10-rc2 for Gen2 Lager and found two issues
about DISPLAY-UNIT: Does not support 640x480 resolution & Does not
support 16-bit for color numbers.
"root@linaro-naro:~# fbset -xres 640 -yres 480 -laced 0
ioctl FBIOPUT_VSCREENINFO: Invalid
From: Magnus Damm
Since of_iommu_configure() now skips over disabled devices
we can simply drop this check in the IPMMU driver.
Signed-off-by: Magnus Damm
---
drivers/iommu/ipmmu-vmsa.c |7 ---
1 file changed, 7 deletions(-)
iommu/ipmmu-vmsa: IPMMU slave device whitelist V2
[PATCH/RFC v2 1/4] iommu/of: Skip IOMMU devices disabled in DT
[PATCH/RFC v2 2/4] iommu/ipmmu-vmsa: Get rid of disabled device check
[PATCH/RFC v2 3/4] iommu/ipmmu-vmsa: Check devices in xlate()
[PATCH/RFC v2 3/4] iommu/ipmmu-vmsa: Opt-in slave
From: Magnus Damm
Match on r8a7795 ES2 and enable a certain DMA controller.
In other cases the IPMMU driver remains disabled.
Signed-off-by: Magnus Damm
---
Changes since V1:
- Perform white list check in ->xlate() instead of
From: Magnus Damm
Extend the shared IOMMU code to skip over ->xlate() in case the
IOMMU device pointed to by a slave device has been disabled in DT.
Difficult to trigger in case a single IOMMU device is used, however
when multiple IOMMUs are used and some of them are
From: Magnus Damm
Introduce the flag "no_size_align" to allow disabling size-alignment
on a per-domain basis. This follows the suggestion by the comment
in the code, however a per-device control may be preferred?
Needed to make virtual space contiguous for certain
On Thu, Jan 26, 2017 at 09:17:02PM +0100, Wolfram Sang wrote:
>
> > The problem I see is the following logged to the console
> > (which makes the console semi-unusable).
> >
> > sh_mobile_sdhi ee14.sd: timeout waiting for hardware interrupt (CMD13)
>
> Just to make sure: with the HS200
> Using renesas-next without mmc-next I see the problem above on the M3-W.
> Using renesas-next with mmc-next I do not see the problem above.
> Using v4.10-rc2 I also do not see the problem above.
OK. So there is no problem with the code, at least.
> So I believe we should delay the integration
Hi Dong,
On Fri, Jan 27, 2017 at 6:38 AM, DongCV wrote:
> I've tested the linux v4.10-rc2 for Gen2 Lager and found two issues about
> DISPLAY-UNIT: Does not support 640x480 resolution & Does not support 16-bit
> for color numbers.
>
> "root@linaro-naro:~# fbset -xres 640
Hi Chris,
On Fri, Jan 27, 2017 at 4:05 AM, Chris Brandt wrote:
> On Wednesday, January 25, 2017, Geert Uytterhoeven wrote:
>> >> I think you can handle that in drivers/clk/renesas/clk-mstp.c:
>> >> - in cpg_mstp_attach_dev(), add a call to pm_clk_resume(dev) after
>>
On 01/26/2017 12:42 AM, Sergei Shtylyov wrote:
Add the "vsps" property to the DU device node in order to link this node to
the VSPD nodes.
Signed-off-by: Sergei Shtylyov
---
Changes in version 2:
- rebased the patch.
This patch is against the
Hi Jacopo,
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
> Add pin controller driver for Renesas RZ/A1 SoC.
> The SoC driver registers to rz-pfc core module and provides pin
> description array and SoC specific pin mux operation.
>
> Signed-off-by: Jacopo Mondi
Hi Jacopo,
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
>after having discussed in great detail the RZ series per-pin PFC hardware
> peculiarities, this is a proposal for a possible pin-based pin controller
> driver for SoC devices of Renesas RZ family.
Hi Jacopo,
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
> Add core module for per-pin Renesas RZ series pin controller.
> The core module allows SoC driver to register their pins and SoC
> specific operations and interfaces with pinctrl and pinmux core on their
Hi Jacopo,
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
> Add dt-bindings header for Renesas RZ pincontroller.
> The header defines macros for pin description and alternate function
> numbers.
>
> Signed-off-by: Jacopo Mondi
> ---
>
This patch adds a OSTM driver for the Renesas architecture.
The OS Timer (OSTM) has independent channels that can be
used as a freerun or interval times.
This driver uses the first probed device as a clocksource
and then any additional devices as clock events.
Signed-off-by: Chris Brandt
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
This patch set adds a new clocksource driver that uses the OS Timer
(OSTM) that exists in the R7S72100 (RZ/A1) SoC.
The operation of the driver was tested with a simple user application
that does multiple calls to nanosleep() and gettimeofday().
The purpose of adding this driver is to get better
Hi Geert,
On Wednesday, January 25, 2017, Geert Uytterhoeven wrote:
> >> I think you can handle that in drivers/clk/renesas/clk-mstp.c:
> >> - in cpg_mstp_attach_dev(), add a call to pm_clk_resume(dev) after
> the
> >> call to pm_clk_add_clk(),
> >> - in cpg_mstp_detach_dev(), add a call
Explicitly list per-SoC binding for r8a7796. No driver change
is required as the initialisation sequence is currently the same
as for the R-Car Gen3 fallback binding.
Signed-off-by: Simon Horman
---
Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 1 +
1
Enable SH Mobile I2C controller for use on R-Car Gen3 SoCs.
Signed-off-by: Simon Horman
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 869dded0f09f..92a3ee26c6fd
From: Dien Pham
This patch adds support of I2C for DVFS device for Salvator-X board on
R8A7796 SoC.
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Horman
Hi,
this series enables I2C for DVFS on the salvator-x board for the
r8a7795 and r8a7796 SoCs.
Base:
* This series is based on renesas-next-20170126-v4.10-rc2
Dependencies:
* This series has a run-time dependency on
"[PATCH 0/2] clk: renesas: r8a7795/r8a7796: Add IIC-DVFS
From: Keita Kobayashi
This patch enables I2C for DVFS device for for Salvator-X board on
R8A7795 SoC.
Signed-off-by: Keita Kobayashi
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Horman
From: Dien Pham
This patch adds I2C for DVFS device node for R8A7796 SoC.
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Horman
---
From: Keita Kobayashi
This patch adds I2C for DVFS device support for R8A7795 SoC.
Signed-off-by: Keita Kobayashi
Signed-off-by: Gaku Inami
Signed-off-by: Dien Pham
On Thu, Jan 26, 2017 at 9:47 AM, Simon Horman
wrote:
> Explicitly list per-SoC binding for r8a7796. No driver change
> is required as the initialisation sequence is currently the same
> as for the R-Car Gen3 fallback binding.
>
> Signed-off-by: Simon Horman
Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses
only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force
a 32-bit IOVA space through the IOMMU Domain Geometry.
Hence if a device (e.g. SYS-DMAC) rightfully configures a 40-bit DMA
mask, it will still be handed
On Thu, Jan 26, 2017 at 9:52 AM, Simon Horman
wrote:
> Enable SH Mobile I2C controller for use on R-Car Gen3 SoCs.
>
> Signed-off-by: Simon Horman
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
On Thu, Jan 26, 2017 at 11:01:17AM +0100, Simon Horman wrote:
> On Fri, Jan 13, 2017 at 09:39:28AM +0100, Wolfram Sang wrote:
> > > Sorry for missing these.
> > > I have queued them up for v4.11.
> >
> > Thank you!
>
> On my r8a7796/salvator-x I see the following with this series applied:
>
>
Hi Geert,
On Thu, Jan 26, 2017 at 6:53 PM, Geert Uytterhoeven
wrote:
> Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses
> only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force
> a 32-bit IOVA space through the IOMMU Domain
On Thu, Jan 26, 2017 at 09:47:31AM +0100, Simon Horman wrote:
> Explicitly list per-SoC binding for r8a7796. No driver change
> is required as the initialisation sequence is currently the same
> as for the R-Car Gen3 fallback binding.
>
> Signed-off-by: Simon Horman
On Thu, Jan 26, 2017 at 9:52 AM, Simon Horman
wrote:
> From: Keita Kobayashi
>
> This patch adds I2C for DVFS device support for R8A7795 SoC.
>
> Signed-off-by: Keita Kobayashi
> Signed-off-by: Gaku
Hi Chris,
On 26/01/2017 03:58, Chris Brandt wrote:
Hi Jacopo,
On Wednesday, January 25, 2017, Jacopo Mondi wrote:
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile| 1 +
drivers/pinctrl/rz-pfc/Kconfig | 18 ++
drivers/pinctrl/rz-pfc/Makefile | 1
On Tue, Jan 10, 2017 at 10:08:48PM +0100, Niklas Söderlund wrote:
> Hi Simon,
>
> I started to se errors when I was testing DMAC+IPMMU patches on top of
> v4.10-rc1 on Koelsch.
There has been some discussion in this thread already. I would like to
provide some more information in case it is
On Thu, Jan 26, 2017 at 9:52 AM, Simon Horman
wrote:
> From: Dien Pham
>
> This patch adds I2C for DVFS device node for R8A7796 SoC.
>
> Signed-off-by: Dien Pham
> Signed-off-by: Takeshi Kihara
From: Geert Uytterhoeven
Device nodes representing I/O devices should be marked disabled in the
SoC-specific DTS, and overridden by board-specific DTSes where needed.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Chris Brandt
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r7s72100.dtsi | 18 ++
1 file changed, 18
From: Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +--
1 file changed, 29 insertions(+), 11
From: Chris Brandt
Signed-off-by: Chris Brandt
Reported-by: Geert Uytterhoeven
Acked-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Geert Uytterhoeven
Link the ARM GIC to the INTC-SYS module clock, and add it to the SYSC
"always-on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM based SoC updates for v4.11.
This pull request is based on the previous round of
such requests, tagged as renesas-soc-for-v4.11,
which you have already pulled.
The following changes since commit
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM based SoC DT updates for
v4.11.
This pull request is based on the previous round of
such requests, tagged as renesas-dt-for-v4.11,
which you have already pulled.
The following changes since commit
From: Chris Brandt
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8
1 file changed, 8
From: Chris Brandt
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r7s72100.dtsi| 9 +
> Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> guess!? (And I can add Rob's ack afterwards).
Can you add my tags as well. They got dropped somehow:
Reviewed-by: Wolfram Sang
signature.asc
Description: PGP signature
From: Geert Uytterhoeven
Link the ARM GIC to the INTC-SYS module clock, and add it to the SYSC
"always-on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be
On Thu, Jan 26, 2017 at 9:52 AM, Simon Horman
wrote:
> From: Dien Pham
>
> This patch adds support of I2C for DVFS device for Salvator-X board on
> R8A7796 SoC.
>
> Signed-off-by: Dien Pham
> Signed-off-by:
On Thu, Jan 26, 2017 at 9:52 AM, Simon Horman
wrote:
> From: Keita Kobayashi
>
> This patch enables I2C for DVFS device for for Salvator-X board on
> R8A7795 SoC.
>
> Signed-off-by: Keita Kobayashi
>
Hi Jacopo,
On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote:
> Add pincontroller node compatible with the new Renesas RZ/A1
> pincontroller driver.
>
> Signed-off-by: Jacopo Mondi
> ---
> arch/arm/boot/dts/r7s72100.dtsi | 12
On Thu, Jan 26, 2017 at 11:03:56AM +0100, Wolfram Sang wrote:
> On Thu, Jan 26, 2017 at 11:01:17AM +0100, Simon Horman wrote:
> > On Fri, Jan 13, 2017 at 09:39:28AM +0100, Wolfram Sang wrote:
> > > > Sorry for missing these.
> > > > I have queued them up for v4.11.
> > >
> > > Thank you!
> >
> >
On Thu, Jan 26, 2017 at 09:07:45AM +0100, Ulf Hansson wrote:
> On 25 January 2017 at 21:28, Chris Brandt wrote:
> > At first this started out as a simple typo fix, until I realized
> > that the SDHI in the RZ/A1 has 2 clocks per channel and both need
> > to be turned
> The problem I see is the following logged to the console
> (which makes the console semi-unusable).
>
> sh_mobile_sdhi ee14.sd: timeout waiting for hardware interrupt (CMD13)
Just to make sure: with the HS200 enablement patches present?
signature.asc
Description: PGP signature
On 01/23, Geert Uytterhoeven wrote:
> As the function header of cpg_mstp_clock_register() is split in an
> unusual way, "git diff" gets confused when changes to the body of
> the function are made, and attributes them to the wrong function.
>
> Reformat the function header to fix this.
>
>
From: Simon Horman
Date: Thu, 26 Jan 2017 14:29:27 +0100
> From: Kazuya Mizuguchi
>
> "swiotlb buffer is full" errors occur after repeated initialisation of a
> device - f.e. suspend/resume or ip link set up/down. This is because
94 matches
Mail list logo