The "official" Condor boards have always been wired to mount NFS via
GEther, not EtherAVB -- the boards resoldered for EtherAVB were local
to Cogent Embedded, so we've been having an unpleasant situation where
a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY
extension board is
Hi Chris,
On Fri, Oct 05, 2018 at 10:09:51AM -0500, Chris Brandt wrote:
> Add device tree binding documentation and header file for Renesas R7S9210
> (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> ---
> .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 76
> ++
>
Hi Geert,
Thanks for your patch.
On 2018-10-16 14:00:36 +0200, Geert Uytterhoeven wrote:
> Some VIN channels support less than 24 lanes. As union vin_data always
> consumes space for 24 lanes, this wastes memory.
>
> Hence introduce new smaller unions vin_data12 and vin_data16, to
>
Hi Jacopo,
On Thursday, October 18, 2018, jacopo mondi wrote:
> Here you define bindings that allows you to have only one
> gpio-controller node for the whole system.
Correct. Since DT describes HW, we do only have one gpio-controller for
the entire chip. It is one piece of hardware, not many
Hi Jacopo,
On Thursday, October 18, 2018, jacopo mondi wrote:
> > + Example: Assigning a GPIO:
> > +
> > + leds {
> > + status = "okay";
> > + compatible = "gpio-leds";
> > +
> > + led0 {
> > + /* P6_0 */
> > + gpios = <
Hi Jacopo,
>thanks for the patches.
Thanks for the review!
On Thursday, October 18, 2018, jacopo mondi wrote:
> > + * Combined GPIO and pin controller support for Renesas RZ/A2
> (R7S72100) SoC
>
> R7S9210
Thanks.
hmm, I wonder what pinctrl driver I copied that from... ;)
> > +#include
Hello!
On 09/24/2018 11:13 PM, Sergei Shtylyov wrote:
> Describe TMUs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
>
> ---
> This patch is against the
Hi Chris,
On Tue, Oct 16, 2018 at 05:47:00PM -0500, Rob Herring wrote:
> On Fri, Oct 05, 2018 at 10:09:51AM -0500, Chris Brandt wrote:
> > Add device tree binding documentation and header file for Renesas R7S9210
> > (RZ/A2) SoCs.
> >
> > Signed-off-by: Chris Brandt
> > ---
> >
Hi Simon-san, Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, October 17, 2018 6:35 PM
>
> Hi Simon,
>
> On Wed, Oct 17, 2018 at 10:57 AM Simon Horman wrote:
> > On Tue, Oct 16, 2018 at 03:04:50PM +0900, Yoshihiro Shimoda wrote:
> > > This patch revises the reg size of each hsusb
Hi Chris,
thanks for the patches.
On Fri, Oct 05, 2018 at 10:09:50AM -0500, Chris Brandt wrote:
> Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> ---
> drivers/pinctrl/Kconfig| 11 +
> drivers/pinctrl/Makefile | 1
On Friday 21 September 2018 04:26 AM, Wolfram Sang wrote:
>
>> Thanks looks nice to me:
>>
>> Acked-by: Tony Lindgren
>
> Thanks, Tony!
Hi Wolfram Sang,
Posted: https://lore.kernel.org/patchwork/patch/1001457/
Thanks for the series! I tested for poweroff on am572x-idk.
Tested-by: Keerthy
On Thu, Sep 20, 2018 at 06:14:23PM +0200, Wolfram Sang wrote:
> We had the request to access devices very late when interrupts are not
> available anymore multiple times now. Mostly to prepare shutdown or
> reboot. Allow adapters to specify a specific callback for this case.
> Note that we fall
On Wed, Oct 17, 2018 at 10:52:14AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Oct 17, 2018 at 10:13 AM Simon Horman wrote:
> > On Tue, Oct 16, 2018 at 10:36:33PM +0300, Sergei Shtylyov wrote:
> > > Describe MSIOF in the R8A779{7|8}0 device trees.
> > >
> > > The DMA props are
On Mon, Oct 15, 2018 at 02:14:25PM -0500, Rob Herring wrote:
> On Thu, 4 Oct 2018 09:53:10 +0100, Fabrizio Castro wrote:
> > Fix RZ/G2E part number from its description.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
> > ---
> >
On Wed, Oct 17, 2018 at 11:34:43AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Oct 17, 2018 at 10:57 AM Simon Horman wrote:
> > On Tue, Oct 16, 2018 at 03:04:50PM +0900, Yoshihiro Shimoda wrote:
> > > This patch revises the reg size of each hsusb device node for
> > > r8a7795,
On Wed, Oct 17, 2018 at 09:01:04PM +0300, Laurent Pinchart wrote:
> Hello,
>
> On Wednesday, 17 October 2018 20:48:01 EEST Laurent Pinchart wrote:
> > The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager,
> > are enabled in DT but have no device connected to their output. This
>
On Thu, Sep 27, 2018 at 10:53:41AM +, Fabrizio Castro wrote:
> Hello Simon,
>
> > Subject: Re: [PATCH v2 3/3] arm64: dts: renesas: r8a774a1: Add CAN nodes
> >
> > On Mon, Sep 10, 2018 at 11:43:15AM +0100, Fabrizio Castro wrote:
> > > From: Chris Paterson
> > >
> > > Add the device nodes for
On Tue, Sep 11, 2018 at 03:53:42PM +0200, Simon Horman wrote:
> On Mon, Sep 10, 2018 at 03:31:18PM +0100, Biju Das wrote:
> > Add VIN and CSI-2 nodes to RZ/G2M SoC dtsi.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
>
> Thanks, I would value a review of this entire series
On Tue, Oct 16, 2018 at 7:53 PM Chris Brandt wrote:
>
> On Tuesday, October 16, 2018, Rob Herring wrote:
> > > +Optional properties:
> > > + - gpio-controller
> > > +Include this in order to enable GPIO functionality. When included,
> > both
> > > +gpio_cells and gpio_ranges are then
19 matches
Mail list logo
