Re: [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock

On 24 May 2012 12:57, Kukjin Kim wrote: > Thomas Abraham wrote: >> >> The sclk_spi clock is derived currently from the first level divider >> (MMCx_RATIO) which is incorrect. The output of the first level clock >> is divided by a second level divider (MMCx_PRE_RATIO), the output of >> which is use

RE: [PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock

Thomas Abraham wrote: > > The sclk_spi clock is derived currently from the first level divider > (MMCx_RATIO) which is incorrect. The output of the first level clock > is divided by a second level divider (MMCx_PRE_RATIO), the output of > which is used as the spi bus clock (sclk_spi). Fix the cloc

[PATCH 1/6] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock

The sclk_spi clock is derived currently from the first level divider (MMCx_RATIO) which is incorrect. The output of the first level clock is divided by a second level divider (MMCx_PRE_RATIO), the output of which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy issues for the sclk_s