Hi Tomasz,
On Sat, Jun 8, 2013 at 5:47 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On Friday 31 of May 2013 18:01:34 Vikas Sajjan wrote:
This patch adds set_rate and round_rate clk_ops for PLL36xx
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan
Hi Mike,
On Tuesday 11 of June 2013 19:54:51 Mike Turquette wrote:
Quoting Tomasz Figa (2013-06-05 16:57:26)
This patch adds new, Common Clock Framework-based clock driver for
Samsung S3C64xx SoCs. The driver is just added, without actually
letting the platforms use it yet, since this
Add clock lookup information for i2s controllers on exynos5250 SoC.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git
Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This
subsystem
has a internal clock controller which controls i2s0 and pcm0 clocks. This patch
series adds the Samsung audio subsytem clock to the common clock framework and
provides the I2S controllers clock information in the
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos4.dtsi |2
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson
This patch updates the samsung i2s documentation for pinmux and
clock entries.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 46 ---
1 files changed, 19 insertions(+), 27 deletions(-)
diff --git
This patch corrects the base address of pinctrl_3 on Exynos5250
platform.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- Added platform name in the subject line.
arch/arm/boot/dts/exynos5250-pinctrl.dtsi |2 +-
arch/arm/boot/dts/exynos5250.dtsi |
This patch adds the required regulator supplies and properties
for wm8994 codec on smdk5250 board.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- Clubbed the same supply regulators as suggested by Mark.
arch/arm/boot/dts/exynos5250-smdk5250.dts | 37
On Wednesday 12 June 2013, Subash Patel wrote:
I would definitely leave on exynos5440 support in defconfig. It's not a
lot of extra code, and if you have a system with less than 4GB memory,
you really don't want to enable LPAE because of the overhead.
Even if we have = 4GB memory, and the
Hi,
This series of patches introduces PCIe support for Samsung Exynos5440,
and is based on the latest 'linux-next' tree (20130607).
These patches was tested with Intel e1000e LAN card on Exynos5440.
This PATCH v4 follows:
* PATCH v3, sent on June, 6th 2013
* PATCH v2, sent on March, 23rd 2013
Enable PCIe support for Exynos5440 which has two PCIe controllers.
Signed-off-by: Jingoo Han jg1@samsung.com
---
Tested on Exynos5440.
Changes since v3:
- Selected PCI_DOMAINS
arch/arm/Kconfig |1 +
arch/arm/mach-exynos/Kconfig |2 ++
2 files changed, 3 insertions(+)
Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.
Signed-off-by: Jingoo Han jg1@samsung.com
---
Tested on Exynos5440.
Changes since v3:
- Removed 'bus-range' property from DT
- Added 'interrupt-map-mask', 'interrupt-map' properties to DT
- Fixed the
On Wednesday, June 12, 2013 7:18 PM, Jingoo Han wrote:
Hi,
This series of patches introduces PCIe support for Samsung Exynos5440,
and is based on the latest 'linux-next' tree (20130607).
These patches was tested with Intel e1000e LAN card on Exynos5440.
This PATCH v4 follows:
* PATCH
Thanks for the update! A few comments again:
On Wednesday 12 June 2013 19:20:00 Jingoo Han wrote:
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..efe7d39 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++
On Wednesday 12 June 2013 19:19:05 Jingoo Han wrote:
+
+struct pcie_port {
+ struct device *dev;
+ u8 controller;
+ u8 root_bus_nr;
+ void __iomem*dbi_base;
+ void __iomem*elbi_base;
+ void
This patch series contains a couple of fixes in cpuidle/PM due to
1) exynos5440 platform which does not support cpuidle C1 state.
2) Compilations error when generic PM options are enabled.
This patch series depends on earlier posted patch
http://www.spinics.net/lists/arm-kernel/msg248831.html
This patch enables the selection of samsung pm related stuffs
when SAMSUNG_PM config is enabled and not just when generic PM
config is enabled. Power management for s3c64XX and s3c24XX
is enabled by default and for other platform depends on S5P_PM.
This patch also fixes the following compilation
This patch registers the basic C0 state for all exynos SOC's but
limits the C1(AFTR -Arm off top running) state in only the supported
SOC's(ie. EXYNOS 4210, 4212, 4412 and 5250).
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
arch/arm/mach-exynos/cpuidle.c |4 +++-
1 files
Add the required pin configuration support to Exynos5420 using pinctrl
interface.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 680 +
arch/arm/boot/dts/exynos5420.dtsi | 45 ++
2 files changed,
Skip exynos5420 gpiolib registration if pinctrl support is enabled.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
drivers/gpio/gpio-samsung.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 83a0d71..b3dd984
Add Samsung Exynos5420 SoC specific data to enable pinctrl support for
all platforms based on Exynos5420.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-exynos.c | 115
On Sat, Jun 8, 2013 at 5:42 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On Friday 31 of May 2013 18:01:33 Vikas Sajjan wrote:
From: Yadwinder Singh Brar yadi.b...@samsung.com
This patch add set_rate() and round_rate() for PLL35xx
Reviewed-by: Doug Anderson diand...@chromium.org
On Wednesday 12 June 2013, Jingoo Han wrote:
On Friday, June 07, 2013 7:53 PM, Arnd Bergmann wrote:
On Friday 07 June 2013 18:22:50 Jingoo Han wrote:
+- ranges: ranges for the PCI memory and I/O regions
+- reset-gpio: gpio pin number of power good signal
The 'reset-gpio' property
On Tuesday 11 June 2013, Jingoo Han wrote:
+ ranges = 0x0800 0 0x4000 0x4000 0 0x0020
/* configuration space */
+ 0x8100 0 0 0x4020 0 0x4000
/* downstream I/O */
+ 0x8200 0 0
This patch series does the following:
1) Unifies the clk strutures used for PLL35xx PLL36xx and usues clk-base
instead of clk-con0, to factor out possible common code.
2) Defines a common rate_table which will contain recommended p, m, s and k
values for supported rates that needs to
This patch unifies clk strutures used for PLL35xx PLL36xx and uses clk-base
instead of directly using clk-con0, so that possible common code can be
factored out.
It also introdues common pll_[readl/writel] macros for the users of common
samsung_clk_pll struct.
Reviewed-by: Tomasz Figa
This patch add set_rate() and round_rate() for PLL35xx
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 104 -
1 files changed, 103 insertions(+), 1 deletions(-)
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
From: Vikas Sajjan vikas.saj...@linaro.org
This patch adds set_rate and round_rate clk_ops for PLL36xx
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 79
From: Vikas Sajjan vikas.saj...@linaro.org
While trying to get rate of mout_vpllsrc MUX (parent) for registering the
fout_vpll (child), we found get rate was failing.
So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL
Adds the EPLL and VPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 53 --
drivers/clk/samsung/clk.h|2 +
2 files changed, 52 insertions(+), 3 deletions(-)
diff
Quoting Padmavathi Venna (2013-06-12 01:07:43)
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Looks good. Did you want me to take the clk patches or just gathering
Acks?
Regards,
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
This patch unifies clk strutures used for PLL35xx PLL36xx and uses clk-base
instead of directly using clk-con0, so that possible common code can be
factored out.
It also introdues common
Yadwinder,
On Wed, Jun 12, 2013 at 1:33 PM, Doug Anderson diand...@chromium.org wrote:
So. We just found that this type of solution doesn't work on
exynos5420, since the LOCK and CON registers aren't always 0x100 away
from each other. Perhaps you can adjust to use a solution like Andrew
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
Reviewed-by: Doug Anderson
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
Adds the EPLL and VPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 53
--
Hi Leela Krishna,
On Wednesday 12 of June 2013 20:21:26 Leela Krishna Amudala wrote:
Add the required pin configuration support to Exynos5420 using pinctrl
interface.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 680
Hi Leela Krishna,
On Wednesday 12 of June 2013 20:21:27 Leela Krishna Amudala wrote:
Add Samsung Exynos5420 SoC specific data to enable pinctrl support for
all platforms based on Exynos5420.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
On Wednesday 12 of June 2013 20:21:28 Leela Krishna Amudala wrote:
Skip exynos5420 gpiolib registration if pinctrl support is enabled.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
drivers/gpio/gpio-samsung.c |1 +
1 file changed, 1 insertion(+)
diff --git
On Monday 03 of June 2013 20:39:53 Yadwinder Singh Brar wrote:
This patch add set_rate() and round_rate() for PLL35xx
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 104
Hi Yadwinder, Vikas,
On Monday 03 of June 2013 20:39:54 Yadwinder Singh Brar wrote:
From: Vikas Sajjan vikas.saj...@linaro.org
This patch adds set_rate and round_rate clk_ops for PLL36xx
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
On Monday 03 of June 2013 20:39:55 Yadwinder Singh Brar wrote:
From: Vikas Sajjan vikas.saj...@linaro.org
While trying to get rate of mout_vpllsrc MUX (parent) for registering
the fout_vpll (child), we found get rate was failing.
So this patch moves the mout_vpllsrc MUX out of the existing
Hi Chander,
One more thing inline.
On Thursday 06 of June 2013 16:31:23 Chander Kashyap wrote:
The Exynos5420 clocks are statically listed and registered using the
Samsung specific common clock helper functions.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by:
Hi,
On Wednesday 12 of June 2013 13:33:50 Doug Anderson wrote:
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
This patch unifies clk strutures used for PLL35xx PLL36xx and uses
clk-base instead of directly using clk-con0, so that possible
Tomasz,
On Wed, Jun 12, 2013 at 1:58 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
+ pinctrl@1340 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+
Hi Doug,
On Wednesday 12 of June 2013 13:43:37 Doug Anderson wrote:
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
This patch defines a common rate_table which will contain recommended
p, m, s, k values for supported rates that needs to be
Tomasz,
+ apll = samsung_clk_register_pll35xx(fout_apll, oscclk,
+ reg_base + 0x100);
+ bpll = samsung_clk_register_pll35xx(fout_bpll, oscclk,
+ reg_base + 0x20110);
+ cpll = samsung_clk_register_pll35xx(fout_cpll, oscclk,
+
Tomasz,
On Wed, Jun 12, 2013 at 2:20 PM, Doug Anderson diand...@chromium.org wrote:
Tomasz,
On Wed, Jun 12, 2013 at 1:58 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
+ pinctrl@1340 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells
Leela,
On Wed, Jun 12, 2013 at 7:51 AM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Add Samsung Exynos5420 SoC specific data to enable pinctrl support for
all platforms based on Exynos5420.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
On Wednesday 12 of June 2013 14:35:30 Doug Anderson wrote:
Tomasz,
On Wed, Jun 12, 2013 at 2:20 PM, Doug Anderson diand...@chromium.org
wrote:
Tomasz,
On Wed, Jun 12, 2013 at 1:58 PM, Tomasz Figa tomasz.f...@gmail.com
wrote:
+ pinctrl@1340 {
+ gpy7: gpy7 {
+
Hi,
On Wednesday 05 of June 2013 23:18:05 Tomasz Figa wrote:
Since we now have a proper Samsung PWM clocksource driver in place,
we can proceed with further cleanup of PWM timers support on Samsung
SoCs.
This series attempts to achieve this goal by:
1) moving remaining Samsung platforms
Tomasz,
On Wed, Jun 12, 2013 at 2:19 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hmm, if done properly, it could simplify PLL registration in SoC clock
initialization code a lot.
I'm not sure if this is really the best solution (feel free to suggest
anything better), but we could put PLLs
Doug,
Hmm, if done properly, it could simplify PLL registration in SoC clock
initialization code a lot.
I'm not sure if this is really the best solution (feel free to suggest
anything better), but we could put PLLs in an array, like other clocks,
e.g.
... exynos4210_pll_clks[] = {
On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote:
Needs testing on other platforms as I could only compile test for them.
How/who can help here? WHo has and still cares for other affected platforms?
66 files changed, 627 insertions(+), 1580 deletions(-)
Nice cleanup.
Any
Hi Olof,
On Wednesday 12 of June 2013 16:00:23 Olof Johansson wrote:
On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote:
Needs testing on other platforms as I could only compile test for
them.
How/who can help here? WHo has and still cares for other affected
platforms?
66
On Wed, Jun 12, 2013 at 06:08:48AM +0900, Kukjin Kim wrote:
The following changes since commit 317ddd256b9c24b0d78fa8018f80f1e495481a10:
Linux 3.10-rc5 (2013-06-08 17:41:04 -0700)
are available in the git repository at:
Am Donnerstag, 13. Juni 2013, 01:13:47 schrieb Tomasz Figa:
Hi Olof,
On Wednesday 12 of June 2013 16:00:23 Olof Johansson wrote:
On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote:
Needs testing on other platforms as I could only compile test for
them.
How/who can help
On 06/13/2013 01:38 AM, Heiko Stübner wrote:
Am Donnerstag, 13. Juni 2013, 01:13:47 schrieb Tomasz Figa:
Hi Olof,
On Wednesday 12 of June 2013 16:00:23 Olof Johansson wrote:
On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote:
Needs testing on other platforms as I could only compile
On Wed, Jun 12, 2013 at 06:09:10AM +0900, Kukjin Kim wrote:
The following changes since commit 317ddd256b9c24b0d78fa8018f80f1e495481a10:
Linux 3.10-rc5 (2013-06-08 17:41:04 -0700)
are available in the git repository at:
On Wed, Jun 12, 2013 at 06:08:19AM +0900, Kukjin Kim wrote:
Hi Arnd, Olof
Please pull Samsung stuff for v3.11.
If any problems, please kindly let me know.
Hi,
I've pulled 1, 2, 4 and 6. Please fix the comments on 3 and 5 and send fresh
requests.
Also, I see you've based a bunch of
Olof Johansson wrote:
On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote:
Needs testing on other platforms as I could only compile test for
them.
How/who can help here? WHo has and still cares for other affected
platforms?
66 files changed, 627 insertions(+), 1580
Olof Johansson wrote:
On Wed, Jun 12, 2013 at 06:09:10AM +0900, Kukjin Kim wrote:
The following changes since commit
317ddd256b9c24b0d78fa8018f80f1e495481a10:
Linux 3.10-rc5 (2013-06-08 17:41:04 -0700)
are available in the git repository at:
Olof Johansson wrote:
On Wed, Jun 12, 2013 at 06:09:03AM +0900, Kukjin Kim wrote:
The following changes since commit
317ddd256b9c24b0d78fa8018f80f1e495481a10:
Linux 3.10-rc5 (2013-06-08 17:41:04 -0700)
are available in the git repository at:
Olof Johansson wrote:
On Wed, Jun 12, 2013 at 06:08:48AM +0900, Kukjin Kim wrote:
The following changes since commit
317ddd256b9c24b0d78fa8018f80f1e495481a10:
Linux 3.10-rc5 (2013-06-08 17:41:04 -0700)
are available in the git repository at:
Olof Johansson wrote:
On Wed, Jun 12, 2013 at 06:08:19AM +0900, Kukjin Kim wrote:
Hi Arnd, Olof
Please pull Samsung stuff for v3.11.
If any problems, please kindly let me know.
Hi,
I've pulled 1, 2, 4 and 6. Please fix the comments on 3 and 5 and send
fresh
requests.
Thanks.
Hi Mike,
On Wed, Jun 12, 2013 at 10:15 PM, Mike Turquette mturque...@linaro.org wrote:
Quoting Padmavathi Venna (2013-06-12 01:07:43)
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Mr. Dae,
Thanks for your valuable inputs.
I posted it as RFC because, I also have received comments to register
hdmiphy as a clock controller. As we always configure it for specific
frequency, hdmi-phy looks similar to a PLL. But it really doesn't
belong to that class. Secondly prior to
On 13 June 2013 03:02, Andrew Bresticker abres...@chromium.org wrote:
Tomasz,
+ apll = samsung_clk_register_pll35xx(fout_apll, oscclk,
+ reg_base + 0x100);
+ bpll = samsung_clk_register_pll35xx(fout_bpll, oscclk,
+ reg_base + 0x20110);
+
On Wednesday, June 12, 2013 7:56 PM, Arnd Bergmann wrote:
Thanks for the update! A few comments again:
On Wednesday 12 June 2013 19:20:00 Jingoo Han wrote:
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..efe7d39
72 matches
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