Ok, I have one question when reading drivers/spi/spi-s3c64xx.c
In s3c64xx_spi_setup, cs-line(S3C64XX_GPC(3)) is set to
GPIOF_OUT_INIT_HIGH, that means an general output pin.
But the other three(clk, mosi, miso) was set to 2 by
s3c64xx_spi0_cfg_gpio. This is just what is needed by SPI.
My question
On Thu, 10 Oct 2013 14:54:29 -0600, Alex Williamson wrote:
On Mon, 2013-10-07 at 10:58 +0900, Cho KyongHo wrote:
Patch written by Antonios Motakis a.mota...@virtualopensystems.com:
IOMMU groups are expected by certain users of the IOMMU API,
e.g. VFIO. Since each device is behind its own
On Mon, Oct 14, 2013 at 03:05:58AM +0800, YouShenghui wrote:
Please fix your mailer to word wrap within paragraphs, your messages are
very hard to read.
Ok, I have one question when reading drivers/spi/spi-s3c64xx.c
In s3c64xx_spi_setup, cs-line(S3C64XX_GPC(3)) is set to GPIOF_OUT_INIT_HIGH,
On 09-10-2013 08:08, Naveen Krishna Chatradhi wrote:
On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.
To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the reg property of the node.
Naveen,
On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
Hi,
All patches (#1-#3) look good to me, FWIW you can add:
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
fixup patchset:
On 11-10-2013 11:57, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
Hi Naveen,
On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
Hi,
All patches (#1-#3) look good to me, FWIW you can add:
Reviewed-by: Bartlomiej
On Sun, Oct 13, 2013 at 08:29:47PM +0200, Tomasz Figa wrote:
On Saturday 12 of October 2013 13:33:29 Mark Brown wrote:
Did the s3c64xx pl08x stuff get merged?
Most of. All the patches for the amba-pl08x driver got merged. Just the
platform glue remains. I will rebase and send respective
On 09-10-2013 02:29, Lukasz Majewski wrote:
Up till now Exynos5250 and Exynos4412 had the same definitions for TMU
data. Following commit changes that, by introducing separate
exynos4412_default_tmu_data structure.
Since Exynos4412 was chronologically first, the corresponding name for
TMU
On 09-10-2013 02:29, Lukasz Majewski wrote:
The commit d0a0ce3e77c795258d47f9163e92d5031d0c5221 (thermal: exynos: Add
missing definations and code cleanup) has removed setting of test MUX address
value at TMU configuration setting.
This field is not present on Exynos4210 and Exynos5 SoCs.
On 2013-10-14 19:25, Mark Brown wrote:
On Mon, Oct 14, 2013 at 03:05:58AM +0800, YouShenghui wrote:
Please fix your mailer to word wrap within paragraphs, your messages are
very hard to read.
Ok, I have one question when reading drivers/spi/spi-s3c64xx.c
In s3c64xx_spi_setup,
Hi Eduardo,
On 09-10-2013 02:29, Lukasz Majewski wrote:
Up till now Exynos5250 and Exynos4412 had the same definitions for
TMU data. Following commit changes that, by introducing separate
exynos4412_default_tmu_data structure.
Since Exynos4412 was chronologically first, the
Hi Eduardo,
On 09-10-2013 02:29, Lukasz Majewski wrote:
The commit d0a0ce3e77c795258d47f9163e92d5031d0c5221 (thermal:
exynos: Add missing definations and code cleanup) has removed
setting of test MUX address value at TMU configuration setting.
This field is not present on Exynos4210
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
Patches add new platform description, support of clock controller,
dual cluster
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 12
From: Tarek Dakhran t.dakh...@samsung.com
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile| 1 +
From: Tarek Dakhran t.dakh...@samsung.com
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
On Monday, October 14, 2013 10:18:03 AM Eduardo Valentin wrote:
On 11-10-2013 11:57, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
Hi Naveen,
On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
Hi,
All patches
On Mon, Oct 14, 2013 at 10:51:06PM +0800, ysh wrote:
Got it, then what about the setting of clk, mosi, miso pin in slave mode?
Do you mean I need to simulate spi slave side using four gpios?
Hrm, now I think about it clock is going to be a problem... you're
probably stuck with bitbanging
On 14-10-2013 01:52, Zhang, Rui wrote:
Eduardo,
What's your opinion on this patch set?
BTW, please send me all the urgent fixes for thermal soc drivers that
you think should go to 3.12.
I will be sending these + one fix on ti soc thermal for 3.12 soon.
The new chip support on exynos needs
On 14-10-2013 11:00, Lukasz Majewski wrote:
Hi Eduardo,
On 09-10-2013 02:29, Lukasz Majewski wrote:
The commit d0a0ce3e77c795258d47f9163e92d5031d0c5221 (thermal:
exynos: Add missing definations and code cleanup) has removed
setting of test MUX address value at TMU configuration setting.
On 14-10-2013 15:13, Eduardo Valentin wrote:
On 14-10-2013 01:52, Zhang, Rui wrote:
Eduardo,
What's your opinion on this patch set?
BTW, please send me all the urgent fixes for thermal soc drivers that
you think should go to 3.12.
I will be sending these + one fix on ti soc thermal for
Tomasz,
On Fri, Oct 11, 2013 at 7:06 PM, Tomasz Figa t.f...@samsung.com wrote:
Well, it's some kind of difference indeed. However, how often can
a frequency transition happen?
I believe that ondemand allows minimum sampling period of
100 * transition latency, so even without considering the
From: Simon Glass s...@chromium.org
At present the i2c ports are enumerated in a strange way - the
fdtdec_find_aliases_for_id() function is used, but then the ID returned
is ignored and the ports are renumbered. The effect is the same provided
that the device tree has the ports in the same order,
The Exynos5 i2c driver does not handle NACKs properly. This change:
- fixes the NACK processing problem (do not continue transaction if
address cycle was NACKed)
- eliminates a fair amount of duplicate code
Signed-off-by: Vadim Bendebury vben...@chromium.org
Reviewed-by: Simon Glass
Add support for hsi2c controller available on exynos5420.
Note: driver currently supports only fast speed mode 100kbps
Change-Id: I02555b1dc8f4ac21c50aa5158179768563c92f43
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Signed-off-by: R. Chandrasekar rc.se...@samsung.com
---
This patch does the following
1. The irq routine is so simple (just one register read) shouldn't be long
Hence, reduce the timeout to 100milli secs,
2. With 100ms of wait time, interruptible is very much unnecessary.
Hence, use wait_for_completion_timeout instead of
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