Re: [PATCH v2] ARM: dts: Exynos5420: Add device nodes for TMU blocks
Hello Tomasz,
On 7 November 2013 22:15, Tomasz Figa wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 22:02:10 Naveen Krishna Ch wrote:
>> Hello Tomasz,
>>
>> On 7 November 2013 19:53, Tomasz Figa wrote:
>> > Hi Naveen,
>> >
>> > On Thursday 07 of November 2013 18:37:49 Naveen Krishna Chatradhi wrote:
>> >> Exynos5420 SoC has per core thermal management unit.
>> >> 5 TMU channels 4 for CPUs and 5th for GPU.
>> >>
>> >> This patch adds the device tree nodes to the DT device list.
>> >>
>> >> Nodes carry the misplaced second base address and the second
>> >> clock to access the misplaced base address.
>> >>
>> >> Signed-off-by: Leela Krishna Amudala
>> >> Signed-off-by: Naveen Krishna Chatradhi
>> >> Signed-off-by: Andrew Bresticker
>> >> ---
>> >> Changes since v1:
>> >> 1. Nodes carry the misplaced second base address and the second
>> >>clock to access the misplaced base address.
>> >> 2. Correct the clock number for the TMU4
>> >
>> > First of all, this patch should be a part of the whole series adding
>> > support for thermal on Exynos 5420.
>> Right, Reason why i posted this patch myself fixing the nits (As Leela
>> and i work closely)
>> Should have been along with the set.
>
> OK.
>
>> >
>> > In addition, see my comment below.
>> >
>> >> arch/arm/boot/dts/exynos5420.dtsi | 48
>> >> +
>> >> 1 file changed, 48 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> >> b/arch/arm/boot/dts/exynos5420.dtsi
>> >> index 6ffefd1..d736b40 100644
>> >> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> >> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> >> @@ -369,4 +369,52 @@
>> >> clock-names = "gscl";
>> >> samsung,power-domain = <&gsc_pd>;
>> >> };
>> >> +
>> >> + /* tmu for CPU0 */
>> >> + tmu@1006 {
>> >> + compatible = "samsung,exynos5420-tmu";
>> >> + reg = <0x1006 0x100>;
>> >> + interrupts = <0 65 0>;
>> >> + clocks = <&clock 318>;
>> >> + clock-names = "tmu_apbif";
>> >> + };
>> >> +
>> >> + /* tmu for CPU1 */
>> >> + tmu@10064000 {
>> >> + compatible = "samsung,exynos5420-tmu";
>> >> + reg = <0x10064000 0x100>;
>> >> + interrupts = <0 183 0>;
>> >> + clocks = <&clock 318>;
>> >> + clock-names = "tmu_apbif";
>> >> + };
>> >> +
>> >> + /* tmu for CPU2 */
>> >> + tmu@10068000 {
>> >> + compatible = "samsung,exynos5420-tmu";
>> >> + /* 2nd reg is for the misplaced TRIMINFO register */
>> >
>> > Instead of this comment, such broken TMU variant should use a separate
>> > compatible value, like "samsung,exynos5420-tmu-broken-triminfo", like
>> > I mentioned in my comments to your other patch.
>> Will make a note of it.
>
> OK.
>
>> >
>> > For this compatible value, both second reg entry and second clock would
>> > be required.
>> >
>> >> + reg = <0x10068000 0x100>, <0x1006c000 0x4>;
>> >> + interrupts = <0 184 0>;
>> >> + clocks = <&clock 318>;
>> >> + clock-names = "tmu_apbif";
>> >> + };
>> >> +
>> >> + /* tmu for CPU3 */
>> >> + tmu@1006c000 {
>> >> + compatible = "samsung,exynos5420-tmu";
>> >> + /* 2nd reg is for the misplaced TRIMINFO register */
>> >> + reg = <0x1006c000 0x100>, <0x100a 0x4>;
>> >> + interrupts = <0 185 0>;
>> >> + clocks = <&clock 318>, <&clock 319>;
>> >> + clock-names = "tmu_apbif", "tmu_apbif_triminfo";
>> >
>> > The "tmu_apbif_triminfo" clock is not specified in exynos-thermal binding
>> > documentation. In addition, the patch of yours adding support for second
>> > clock uses another name - "tmu_apbif_sec".
>> >
>> > As for the name itself, I would prefer "tmu_apbif_triminfo" as it's more
>> > meaningful.
>> TMU hardware on Exynos5440 and Exynos5420 has two different abnormalities
>> On Exynos5440 Some registers are interleaved between the channels
>> On Exynos5420, TRIMINFO is misplaced between, channels 2, 3 and 4.
>
> I know that those cases are different, but my point was not about it.
>
> In your patch adding support for this second clock, you add following call
> to devm_clk_get():
>
> data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_sec");
>
> However in device tree nodes added by this patch, you have
>
> clock-names = "tmu_apbif", "tmu_apbif_triminfo";
>
> and this where my confusion comes from.
Sure will use one name in DTS, Documentation and the driver.
tmu_apbif_triminfo makes correct sense for Exyns5420, But, for Exynos5440
I prefer something that rhymes with the second_XXX.
Will confirm with the Exynos5440 spec first.
>
>> having second_base was for the fix by Amit to address Exynos5440 problem,
>> Which was already merged.
>> After several reviews i tried to solve it by reusing the second_base
>> for Exynos5420 aswell.
>> Hence, I t
Re: [PATCH 3/7] Return info for device and its memory regions and interrupts
>>> I will look into this. However, can we rely to have access to all >>> device resources through platform abstractions, for every type of >>> platform device >> >> The only resources we care about in vfio are mappable regions >> and irqs. So, yes I think we can rely on access to those >> resources. >> >>> It seems to me that platform devices that are not >>> backed by a specific description mechanism (such as device tree) may >>> include a lot of hard coded values etc in their drivers. >> >> If the platform device struct does not have reg/irq resources described >> then we can't expose them to user space with vfio. > > Which is my concern actually. If the struct does not describe reg/irq > resources, or even worse if it describes them partially, do we want to > let the user shoot himself on the foot? > > Granted this might happen with device tree too, but I find it much > more likely with generic platform devices. > > Maybe we should adopt a whitelist instead? Just realize I never replied to this query... If there are no IRQs in the platform device struct we should just return 0x0 for number of interrupts. If the information in the platform device struct is only partially complete, we should just return an error to the caller of the ioctl. Stuart -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Exynos5420: Add device nodes for TMU blocks
Hi Naveen,
On Thursday 07 of November 2013 22:02:10 Naveen Krishna Ch wrote:
> Hello Tomasz,
>
> On 7 November 2013 19:53, Tomasz Figa wrote:
> > Hi Naveen,
> >
> > On Thursday 07 of November 2013 18:37:49 Naveen Krishna Chatradhi wrote:
> >> Exynos5420 SoC has per core thermal management unit.
> >> 5 TMU channels 4 for CPUs and 5th for GPU.
> >>
> >> This patch adds the device tree nodes to the DT device list.
> >>
> >> Nodes carry the misplaced second base address and the second
> >> clock to access the misplaced base address.
> >>
> >> Signed-off-by: Leela Krishna Amudala
> >> Signed-off-by: Naveen Krishna Chatradhi
> >> Signed-off-by: Andrew Bresticker
> >> ---
> >> Changes since v1:
> >> 1. Nodes carry the misplaced second base address and the second
> >>clock to access the misplaced base address.
> >> 2. Correct the clock number for the TMU4
> >
> > First of all, this patch should be a part of the whole series adding
> > support for thermal on Exynos 5420.
> Right, Reason why i posted this patch myself fixing the nits (As Leela
> and i work closely)
> Should have been along with the set.
OK.
> >
> > In addition, see my comment below.
> >
> >> arch/arm/boot/dts/exynos5420.dtsi | 48
> >> +
> >> 1 file changed, 48 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> >> b/arch/arm/boot/dts/exynos5420.dtsi
> >> index 6ffefd1..d736b40 100644
> >> --- a/arch/arm/boot/dts/exynos5420.dtsi
> >> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> >> @@ -369,4 +369,52 @@
> >> clock-names = "gscl";
> >> samsung,power-domain = <&gsc_pd>;
> >> };
> >> +
> >> + /* tmu for CPU0 */
> >> + tmu@1006 {
> >> + compatible = "samsung,exynos5420-tmu";
> >> + reg = <0x1006 0x100>;
> >> + interrupts = <0 65 0>;
> >> + clocks = <&clock 318>;
> >> + clock-names = "tmu_apbif";
> >> + };
> >> +
> >> + /* tmu for CPU1 */
> >> + tmu@10064000 {
> >> + compatible = "samsung,exynos5420-tmu";
> >> + reg = <0x10064000 0x100>;
> >> + interrupts = <0 183 0>;
> >> + clocks = <&clock 318>;
> >> + clock-names = "tmu_apbif";
> >> + };
> >> +
> >> + /* tmu for CPU2 */
> >> + tmu@10068000 {
> >> + compatible = "samsung,exynos5420-tmu";
> >> + /* 2nd reg is for the misplaced TRIMINFO register */
> >
> > Instead of this comment, such broken TMU variant should use a separate
> > compatible value, like "samsung,exynos5420-tmu-broken-triminfo", like
> > I mentioned in my comments to your other patch.
> Will make a note of it.
OK.
> >
> > For this compatible value, both second reg entry and second clock would
> > be required.
> >
> >> + reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> >> + interrupts = <0 184 0>;
> >> + clocks = <&clock 318>;
> >> + clock-names = "tmu_apbif";
> >> + };
> >> +
> >> + /* tmu for CPU3 */
> >> + tmu@1006c000 {
> >> + compatible = "samsung,exynos5420-tmu";
> >> + /* 2nd reg is for the misplaced TRIMINFO register */
> >> + reg = <0x1006c000 0x100>, <0x100a 0x4>;
> >> + interrupts = <0 185 0>;
> >> + clocks = <&clock 318>, <&clock 319>;
> >> + clock-names = "tmu_apbif", "tmu_apbif_triminfo";
> >
> > The "tmu_apbif_triminfo" clock is not specified in exynos-thermal binding
> > documentation. In addition, the patch of yours adding support for second
> > clock uses another name - "tmu_apbif_sec".
> >
> > As for the name itself, I would prefer "tmu_apbif_triminfo" as it's more
> > meaningful.
> TMU hardware on Exynos5440 and Exynos5420 has two different abnormalities
> On Exynos5440 Some registers are interleaved between the channels
> On Exynos5420, TRIMINFO is misplaced between, channels 2, 3 and 4.
I know that those cases are different, but my point was not about it.
In your patch adding support for this second clock, you add following call
to devm_clk_get():
data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_sec");
However in device tree nodes added by this patch, you have
clock-names = "tmu_apbif", "tmu_apbif_triminfo";
and this where my confusion comes from.
> having second_base was for the fix by Amit to address Exynos5440 problem,
> Which was already merged.
> After several reviews i tried to solve it by reusing the second_base
> for Exynos5420 aswell.
> Hence, I tried to use the "clk_sec" or "clk_second" which will rhyme
> along with the
> "second_base" in the driver.
>
> I'm still not sure this having second clock is needed for Exynos5440 aswell.
> Will figure it out tomorrow.
Even if Exynos 5440 does not need the second clock, it uses a different
compatible value, so you can easily distinguish the cases when the second
clock is required or not.
Best regards,
Tomasz
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Re: [PATCH v2] ARM: dts: Exynos5420: Add device nodes for TMU blocks
Hello Tomasz,
On 7 November 2013 19:53, Tomasz Figa wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 18:37:49 Naveen Krishna Chatradhi wrote:
>> Exynos5420 SoC has per core thermal management unit.
>> 5 TMU channels 4 for CPUs and 5th for GPU.
>>
>> This patch adds the device tree nodes to the DT device list.
>>
>> Nodes carry the misplaced second base address and the second
>> clock to access the misplaced base address.
>>
>> Signed-off-by: Leela Krishna Amudala
>> Signed-off-by: Naveen Krishna Chatradhi
>> Signed-off-by: Andrew Bresticker
>> ---
>> Changes since v1:
>> 1. Nodes carry the misplaced second base address and the second
>>clock to access the misplaced base address.
>> 2. Correct the clock number for the TMU4
>
> First of all, this patch should be a part of the whole series adding
> support for thermal on Exynos 5420.
Right, Reason why i posted this patch myself fixing the nits (As Leela
and i work closely)
Should have been along with the set.
>
> In addition, see my comment below.
>
>> arch/arm/boot/dts/exynos5420.dtsi | 48
>> +
>> 1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> b/arch/arm/boot/dts/exynos5420.dtsi
>> index 6ffefd1..d736b40 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -369,4 +369,52 @@
>> clock-names = "gscl";
>> samsung,power-domain = <&gsc_pd>;
>> };
>> +
>> + /* tmu for CPU0 */
>> + tmu@1006 {
>> + compatible = "samsung,exynos5420-tmu";
>> + reg = <0x1006 0x100>;
>> + interrupts = <0 65 0>;
>> + clocks = <&clock 318>;
>> + clock-names = "tmu_apbif";
>> + };
>> +
>> + /* tmu for CPU1 */
>> + tmu@10064000 {
>> + compatible = "samsung,exynos5420-tmu";
>> + reg = <0x10064000 0x100>;
>> + interrupts = <0 183 0>;
>> + clocks = <&clock 318>;
>> + clock-names = "tmu_apbif";
>> + };
>> +
>> + /* tmu for CPU2 */
>> + tmu@10068000 {
>> + compatible = "samsung,exynos5420-tmu";
>> + /* 2nd reg is for the misplaced TRIMINFO register */
>
> Instead of this comment, such broken TMU variant should use a separate
> compatible value, like "samsung,exynos5420-tmu-broken-triminfo", like
> I mentioned in my comments to your other patch.
Will make a note of it.
>
> For this compatible value, both second reg entry and second clock would
> be required.
>
>> + reg = <0x10068000 0x100>, <0x1006c000 0x4>;
>> + interrupts = <0 184 0>;
>> + clocks = <&clock 318>;
>> + clock-names = "tmu_apbif";
>> + };
>> +
>> + /* tmu for CPU3 */
>> + tmu@1006c000 {
>> + compatible = "samsung,exynos5420-tmu";
>> + /* 2nd reg is for the misplaced TRIMINFO register */
>> + reg = <0x1006c000 0x100>, <0x100a 0x4>;
>> + interrupts = <0 185 0>;
>> + clocks = <&clock 318>, <&clock 319>;
>> + clock-names = "tmu_apbif", "tmu_apbif_triminfo";
>
> The "tmu_apbif_triminfo" clock is not specified in exynos-thermal binding
> documentation. In addition, the patch of yours adding support for second
> clock uses another name - "tmu_apbif_sec".
>
> As for the name itself, I would prefer "tmu_apbif_triminfo" as it's more
> meaningful.
TMU hardware on Exynos5440 and Exynos5420 has two different abnormalities
On Exynos5440 Some registers are interleaved between the channels
On Exynos5420, TRIMINFO is misplaced between, channels 2, 3 and 4.
having second_base was for the fix by Amit to address Exynos5440 problem,
Which was already merged.
After several reviews i tried to solve it by reusing the second_base
for Exynos5420 aswell.
Hence, I tried to use the "clk_sec" or "clk_second" which will rhyme
along with the
"second_base" in the driver.
I'm still not sure this having second clock is needed for Exynos5440 aswell.
Will figure it out tomorrow.
>
> Best regards,
> Tomasz
>
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(: Nav :)
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Re: [PATCH] thermal: exynos: handle gate clock for misplaced TRIMINFO register
On 7 November 2013 19:48, Tomasz Figa wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 18:12:34 Naveen Krishna Chatradhi wrote:
>> On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
>> the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
>> should be acompanied by enabling the respective clock.
>>
>> This patch which allow for a "clk_sec" clock to be specified in the
>> device-tree which will be ungated when accessing the TRIMINFO register.
>>
>> Signed-off-by: Andrew Bresticker
>> Signed-off-by: Naveen Krishna Chatradhi
>> ---
>> drivers/thermal/samsung/exynos_tmu.c | 24 +++-
>> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> This patch modifies the device binding, but fails to mention anything
> about the modification in respective documentation. Please do not do that.
Will make a note to update Documentation from now on.
>
> In addition, since the series adding support for Exynos 5420 has not been
> merged yet, I would rather make this patch a part of that series.
Will merge and upload the whole set, first thing tomorrow.
>
> Also please see my comment below.
>
>> diff --git a/drivers/thermal/samsung/exynos_tmu.c
>> b/drivers/thermal/samsung/exynos_tmu.c
>> index b54825a..33edd1a 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> +++ b/drivers/thermal/samsung/exynos_tmu.c
> [snip]
>> @@ -641,6 +650,15 @@ static int exynos_tmu_probe(struct platform_device
>> *pdev)
>> if (ret)
>> return ret;
>>
>> + data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_sec");
>> + if (!IS_ERR(data->clk_sec)) {
>
> This code does not check if the clock was specified for TMU channels that
> require it, i.e. the driver will not fail if you don't specify this clock.
I thought of making it mandatory, And TMU on Exynos5440 may not need
second clock for accessing the second base. I Will confirm with the Exynso5440
specs and update accordingly.
>
> Instead, it would be better create a separate compatible value for such
> channels, like "samsung,exynos5420-tmu-broken-triminfo", for which this
> clock would be mandatory and for which, if this clock is not specified,
> the driver would fail.
Right
Sure Tomasz,
Creating a new compatible makes handling this case really simple
Thanks for reviewing.
>
> Best regards,
> Tomasz
>
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Re: [PATCH 3/3 v8] thermal: samsung: Add TMU support for Exynos5420 SoCs
Hi Naveen,
On Thursday 07 of November 2013 11:23:32 Naveen Krishna Chatradhi wrote:
> This patch adds the neccessary register changes and arch information
> to support Exynos5420 SoCs
> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
>
> Also updated the Documentation at
> Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>
> Note: The platform data structure will be handled properly once the driver
> moves to complete device driver solution.
Huh? I'm not sure what do you mean here.
> Signed-off-by: Naveen Krishna Chatradhi
> ---
> Changes since v1:
> 1. modified the platform data structure in order to pass SHARED flag
>for channels that need sharing of address space.
> 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
>As the changes are minimum and can be added here.
> Changes since v3:
>a. Rearraged the code alphabetically, make exynso5420 come before
> exynso5440
>b. Reduce code duplication in passing platform data by introducing a
> common macro
> Bartlomiej Zolnierkiewicz Thanks for review and suggestions
> Changes since v4:
> None
> Changes since v5:
> None
> Changes since v6:
> - removed the unsued field "inten_fall_shift"
> - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using
> EXYNOS_TMU_FALL_INT_SHIFT
> Changes since v7:
> - changes ins v6 were moved to the patch 1/3 of this patchset.
> - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using
> EXYNOS_TMU_FALL_INT_SHIFT
>
> .../devicetree/bindings/thermal/exynos-thermal.txt | 39
> drivers/thermal/samsung/exynos_tmu.c | 12 ++-
> drivers/thermal/samsung/exynos_tmu.h |1 +
> drivers/thermal/samsung/exynos_tmu_data.c | 98
>
> drivers/thermal/samsung/exynos_tmu_data.h |8 ++
> 5 files changed, 157 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 116cca0..c5f9a74 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -6,6 +6,7 @@
> "samsung,exynos4412-tmu"
> "samsung,exynos4210-tmu"
> "samsung,exynos5250-tmu"
> +"samsung,exynos5420-tmu"
I would add a second compatible value here for TMU units that have
misplaced TRIMINFO data, e.g. "samsung,exynos5420-tmu-broken-triminfo"
and explicitly specify that second reg and clock-names entry is required
for this compatible value.
> "samsung,exynos5440-tmu"
> - interrupt-parent : The phandle for the interrupt controller
> - reg : Address range of the thermal registers. For soc's which has multiple
> @@ -13,6 +14,16 @@
> interrupt related then 2 set of register has to supplied. First set
> belongs to each instance of TMU and second set belongs to second set
> of common TMU registers.
nit: A blank line here would be nice.
> + NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> + channels 2, 3 and 4
> +
> + TRIMINFO at 0x1006c000 contains data for TMU channel 3
> + TRIMINFO at 0x100a contains data for TMU channel 4
> + TRIMINFO at 0x10068000 contains data for TMU channel 2
> +
> + The misplaced register address is passed through devicetree as the
> + second base
> +
> - interrupts : Should contain interrupt for thermal system
> - clocks : The main clock for TMU device
> - clock-names : Thermal system clock name
> @@ -43,6 +54,34 @@ Example 2):
> clock-names = "tmu_apbif";
> };
>
> +Example 3): (In case of Exynos5420)
Maybe "in case of misplaced TRIMINFO register" would be better?
> + /* tmu for CPU2 */
> + tmu@10068000 {
> + compatible = "samsung,exynos5420-tmu";
> + reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> + interrupts = <0 184 0>;
> + clocks = <&clock 318>;
> + clock-names = "tmu_apbif";
> + };
> +
I believe that just a single example of a node for a TMU with misplaced
TRIMINFO register will be enough.
> + /* tmu for CPU3 */
> + tmu@1006c000 {
> + compatible = "samsung,exynos5420-tmu";
> + reg = <0x1006c000 0x100>, <0x100a 0x4>;
> + interrupts = <0 185 0>;
> + clocks = <&clock 318>;
> + clock-names = "tmu_apbif";
> + };
> +
> + /* tmu for GPU */
> + tmu@100a {
> + compatible = "samsung,exynos5420-tmu";
> + reg = <0x100a 0x100>, <0x10068000 0x4>;
> + interrupts = <0 215 0>;
> + clocks = <&clock 318>;
> + clock-names = "tmu_apbif";
> + };
> +
> Note: For multi-instance tmu each instance should have an alias correctly
> numbered in "aliases" node.
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c
> b/dri
Re: [PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct
Hi Naveen, On Thursday 07 of November 2013 11:22:42 Naveen Krishna Chatradhi wrote: > On Exynos5250, the FALL interrupt related en, status and clear bits are > available at an offset of > 16 in INTEN, INTSTAT registers and at an offset of > 12 in INTCLEAR register. > > On Exynos5420, the FALL interrupt related en, status and clear bits are > available at an offset of > 16 in INTEN, INTSTAT and INTCLEAR registers. > > On Exynos5440, > the FALL_IRQEN bits are at an offset of 4 > and the RISE_IRQEN bits are at an offset of 0 > > This patch introduces a new bit field intclr_fall_shift to handle the > offset for exyns5250 and exynos5440 > Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and > EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field >From what I can see in this patch, the field intclr_fall_shift is not really introduced, but rather inten_fall_shift is renamed to it. Please match patch description with what the patch actually does. I believe this patch is also touches code and data related to Exynos 4x12 SoCs, but the description only covers Exynos 5 SoCs. In addition, if this patch does not introduce any functional changes, but only refactors some code, the description should say so. Also, please see my comment below. > Signed-off-by: Naveen Krishna Chatradhi > --- > Changes since v1: > Changes since v2: > Changes since v3: > None > Changes since v4: > Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440 > Changes since v5: > Modify the commit message > Changes since v6: > - Use EXYNOS_TMU_CLEAR_FALL_INT_SHIFT instead of > EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT > as the same is being used for Exynos4412 > Changes since v7: > - also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and > EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field > > > drivers/thermal/samsung/exynos_tmu.c |2 +- > drivers/thermal/samsung/exynos_tmu.h |4 ++-- > drivers/thermal/samsung/exynos_tmu_data.c |4 ++-- > drivers/thermal/samsung/exynos_tmu_data.h |4 ++-- > 4 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/thermal/samsung/exynos_tmu.c > b/drivers/thermal/samsung/exynos_tmu.c > index 32f38b9..b2202fa 100644 > --- a/drivers/thermal/samsung/exynos_tmu.c > +++ b/drivers/thermal/samsung/exynos_tmu.c > @@ -265,7 +265,7 @@ skip_calib_data: > data->base + reg->threshold_th1); > > writel((reg->inten_rise_mask << reg->inten_rise_shift) | > - (reg->inten_fall_mask << reg->inten_fall_shift), > + (reg->inten_fall_mask << reg->intclr_fall_shift), Shouldn't also the mask values be called intclr_*_mask? They seem to be used only with tmu_intclear register. Same goes for inten_fall_shift, Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Exynos5420: Add device nodes for TMU blocks
Hi Naveen,
On Thursday 07 of November 2013 18:37:49 Naveen Krishna Chatradhi wrote:
> Exynos5420 SoC has per core thermal management unit.
> 5 TMU channels 4 for CPUs and 5th for GPU.
>
> This patch adds the device tree nodes to the DT device list.
>
> Nodes carry the misplaced second base address and the second
> clock to access the misplaced base address.
>
> Signed-off-by: Leela Krishna Amudala
> Signed-off-by: Naveen Krishna Chatradhi
> Signed-off-by: Andrew Bresticker
> ---
> Changes since v1:
> 1. Nodes carry the misplaced second base address and the second
>clock to access the misplaced base address.
> 2. Correct the clock number for the TMU4
First of all, this patch should be a part of the whole series adding
support for thermal on Exynos 5420.
In addition, see my comment below.
> arch/arm/boot/dts/exynos5420.dtsi | 48
> +
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> b/arch/arm/boot/dts/exynos5420.dtsi
> index 6ffefd1..d736b40 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -369,4 +369,52 @@
> clock-names = "gscl";
> samsung,power-domain = <&gsc_pd>;
> };
> +
> + /* tmu for CPU0 */
> + tmu@1006 {
> + compatible = "samsung,exynos5420-tmu";
> + reg = <0x1006 0x100>;
> + interrupts = <0 65 0>;
> + clocks = <&clock 318>;
> + clock-names = "tmu_apbif";
> + };
> +
> + /* tmu for CPU1 */
> + tmu@10064000 {
> + compatible = "samsung,exynos5420-tmu";
> + reg = <0x10064000 0x100>;
> + interrupts = <0 183 0>;
> + clocks = <&clock 318>;
> + clock-names = "tmu_apbif";
> + };
> +
> + /* tmu for CPU2 */
> + tmu@10068000 {
> + compatible = "samsung,exynos5420-tmu";
> + /* 2nd reg is for the misplaced TRIMINFO register */
Instead of this comment, such broken TMU variant should use a separate
compatible value, like "samsung,exynos5420-tmu-broken-triminfo", like
I mentioned in my comments to your other patch.
For this compatible value, both second reg entry and second clock would
be required.
> + reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> + interrupts = <0 184 0>;
> + clocks = <&clock 318>;
> + clock-names = "tmu_apbif";
> + };
> +
> + /* tmu for CPU3 */
> + tmu@1006c000 {
> + compatible = "samsung,exynos5420-tmu";
> + /* 2nd reg is for the misplaced TRIMINFO register */
> + reg = <0x1006c000 0x100>, <0x100a 0x4>;
> + interrupts = <0 185 0>;
> + clocks = <&clock 318>, <&clock 319>;
> + clock-names = "tmu_apbif", "tmu_apbif_triminfo";
The "tmu_apbif_triminfo" clock is not specified in exynos-thermal binding
documentation. In addition, the patch of yours adding support for second
clock uses another name - "tmu_apbif_sec".
As for the name itself, I would prefer "tmu_apbif_triminfo" as it's more
meaningful.
Best regards,
Tomasz
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Re: [PATCH] thermal: exynos: handle gate clock for misplaced TRIMINFO register
Hi Naveen,
On Thursday 07 of November 2013 18:12:34 Naveen Krishna Chatradhi wrote:
> On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
> the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
> should be acompanied by enabling the respective clock.
>
> This patch which allow for a "clk_sec" clock to be specified in the
> device-tree which will be ungated when accessing the TRIMINFO register.
>
> Signed-off-by: Andrew Bresticker
> Signed-off-by: Naveen Krishna Chatradhi
> ---
> drivers/thermal/samsung/exynos_tmu.c | 24 +++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
This patch modifies the device binding, but fails to mention anything
about the modification in respective documentation. Please do not do that.
In addition, since the series adding support for Exynos 5420 has not been
merged yet, I would rather make this patch a part of that series.
Also please see my comment below.
> diff --git a/drivers/thermal/samsung/exynos_tmu.c
> b/drivers/thermal/samsung/exynos_tmu.c
> index b54825a..33edd1a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
[snip]
> @@ -641,6 +650,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> + data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_sec");
> + if (!IS_ERR(data->clk_sec)) {
This code does not check if the clock was specified for TMU channels that
require it, i.e. the driver will not fail if you don't specify this clock.
Instead, it would be better create a separate compatible value for such
channels, like "samsung,exynos5420-tmu-broken-triminfo", for which this
clock would be mandatory and for which, if this clock is not specified,
the driver would fail.
Best regards,
Tomasz
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Re: [PATCH 1/1] ARM: dts: Add hs-i2c nodes to exynos5420
Hi Sachin,
Please see my comments inline.
On Tuesday 05 of November 2013 17:09:20 Sachin Kamat wrote:
> Added high speed I2C nodes to Exynos5420 DT file.
>
> Signed-off-by: Sachin Kamat
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 98
> +
> 1 file changed, 98 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> b/arch/arm/boot/dts/exynos5420.dtsi
> index 9ce5f82..469769a 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -34,6 +34,13 @@
> i2c1 = &i2c_1;
> i2c2 = &i2c_2;
> i2c3 = &i2c_3;
> + i2c4 = &hsi2c_4;
> + i2c5 = &hsi2c_5;
> + i2c6 = &hsi2c_6;
> + i2c7 = &hsi2c_7;
> + i2c8 = &hsi2c_8;
> + i2c9 = &hsi2c_9;
> + i2c10 = &hsi2c_10;
> gsc0 = &gsc_0;
> gsc1 = &gsc_1;
> };
> @@ -339,6 +346,97 @@
> status = "disabled";
> };
>
> + hsi2c_4: hsi2c@12CA {
nit: Node name should be generic, so simply i2c@unit-address should be
enough.
The same for remaining instances.
Best regards,
Tomasz
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Re: [PATCH] ARM: dts: Exynos5420: Add device nodes for HSI2C blocks
On 7 November 2013 18:52, Naveen Krishna Chatradhi
wrote:
> Exynos5420 SoC has 7 High speed I2C channels, This patch adds
> the device tree nodes to the DT device list.
>
> Signed-off-by: Naveen Krishna Chatradhi
> Signed-off-by: Andrew Bresticker
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 98
> +
> 1 file changed, 98 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> b/arch/arm/boot/dts/exynos5420.dtsi
> index 6ffefd1..12f612d 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -34,6 +34,13 @@
> i2c1 = &i2c_1;
> i2c2 = &i2c_2;
> i2c3 = &i2c_3;
> + i2c4 = &hsi2c_4;
> + i2c5 = &hsi2c_5;
> + i2c6 = &hsi2c_6;
> + i2c7 = &hsi2c_7;
> + i2c8 = &hsi2c_8;
> + i2c9 = &hsi2c_9;
> + i2c10 = &hsi2c_10;
> gsc0 = &gsc_0;
> gsc1 = &gsc_1;
> };
> @@ -333,6 +340,97 @@
> status = "disabled";
> };
>
> + hsi2c_4: hsi2c@12CA {
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CA 0x1000>;
> + interrupts = <0 60 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c4_hs_bus>;
> + clocks = <&clock 265>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_5: hsi2c@12CB {
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CB 0x1000>;
> + interrupts = <0 61 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c5_hs_bus>;
> + clocks = <&clock 266>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_6: hsi2c@12CC {
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CC 0x1000>;
> + interrupts = <0 62 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c6_hs_bus>;
> + clocks = <&clock 267>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_7: hsi2c@12CD {
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12CD 0x1000>;
> + interrupts = <0 63 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c7_hs_bus>;
> + clocks = <&clock 268>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_8: hsi2c@12E0 {
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12E0 0x1000>;
> + interrupts = <0 87 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c8_hs_bus>;
> + clocks = <&clock 281>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_9: hsi2c@12E1 {
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12E1 0x1000>;
> + interrupts = <0 88 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c9_hs_bus>;
> + clocks = <&clock 282>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_10: hsi2c@12E2 {
> + compatible = "samsung,exynos5-hsi2c";
> + reg = <0x12E2 0x1000>;
> + interrupts = <0 203 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c10_hs_bus>;
> + clocks = <&clock 283>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> hdmi@1453 {
> compatible = "samsung,exynos4212-hdmi";
> reg = <0x1453 0x7>;
> --
> 1.7.10.4
>
Just found that Sachin Kamat already tried to post a similar patch.
http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/24581
I was actually waiting for the High speed I2C driver to get merged
before adding the device tree nodes.
The High speed I2C driver was accepted only a couple of days ago.
--
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(: Nav :)
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[PATCH] ARM: dts: Exynos5420: Add device nodes for HSI2C blocks
Exynos5420 SoC has 7 High speed I2C channels, This patch adds
the device tree nodes to the DT device list.
Signed-off-by: Naveen Krishna Chatradhi
Signed-off-by: Andrew Bresticker
---
arch/arm/boot/dts/exynos5420.dtsi | 98 +
1 file changed, 98 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6ffefd1..12f612d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -34,6 +34,13 @@
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
+ i2c4 = &hsi2c_4;
+ i2c5 = &hsi2c_5;
+ i2c6 = &hsi2c_6;
+ i2c7 = &hsi2c_7;
+ i2c8 = &hsi2c_8;
+ i2c9 = &hsi2c_9;
+ i2c10 = &hsi2c_10;
gsc0 = &gsc_0;
gsc1 = &gsc_1;
};
@@ -333,6 +340,97 @@
status = "disabled";
};
+ hsi2c_4: hsi2c@12CA {
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CA 0x1000>;
+ interrupts = <0 60 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_hs_bus>;
+ clocks = <&clock 265>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_5: hsi2c@12CB {
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CB 0x1000>;
+ interrupts = <0 61 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_hs_bus>;
+ clocks = <&clock 266>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_6: hsi2c@12CC {
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CC 0x1000>;
+ interrupts = <0 62 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_hs_bus>;
+ clocks = <&clock 267>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_7: hsi2c@12CD {
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12CD 0x1000>;
+ interrupts = <0 63 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_hs_bus>;
+ clocks = <&clock 268>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_8: hsi2c@12E0 {
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12E0 0x1000>;
+ interrupts = <0 87 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_hs_bus>;
+ clocks = <&clock 281>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_9: hsi2c@12E1 {
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12E1 0x1000>;
+ interrupts = <0 88 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c9_hs_bus>;
+ clocks = <&clock 282>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_10: hsi2c@12E2 {
+ compatible = "samsung,exynos5-hsi2c";
+ reg = <0x12E2 0x1000>;
+ interrupts = <0 203 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c10_hs_bus>;
+ clocks = <&clock 283>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
hdmi@1453 {
compatible = "samsung,exynos4212-hdmi";
reg = <0x1453 0x7>;
--
1.7.10.4
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[PATCH v2] ARM: dts: Exynos5420: Add device nodes for TMU blocks
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: Leela Krishna Amudala
Signed-off-by: Naveen Krishna Chatradhi
Signed-off-by: Andrew Bresticker
---
Changes since v1:
1. Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
2. Correct the clock number for the TMU4
arch/arm/boot/dts/exynos5420.dtsi | 48 +
1 file changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6ffefd1..d736b40 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -369,4 +369,52 @@
clock-names = "gscl";
samsung,power-domain = <&gsc_pd>;
};
+
+ /* tmu for CPU0 */
+ tmu@1006 {
+ compatible = "samsung,exynos5420-tmu";
+ reg = <0x1006 0x100>;
+ interrupts = <0 65 0>;
+ clocks = <&clock 318>;
+ clock-names = "tmu_apbif";
+ };
+
+ /* tmu for CPU1 */
+ tmu@10064000 {
+ compatible = "samsung,exynos5420-tmu";
+ reg = <0x10064000 0x100>;
+ interrupts = <0 183 0>;
+ clocks = <&clock 318>;
+ clock-names = "tmu_apbif";
+ };
+
+ /* tmu for CPU2 */
+ tmu@10068000 {
+ compatible = "samsung,exynos5420-tmu";
+ /* 2nd reg is for the misplaced TRIMINFO register */
+ reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+ interrupts = <0 184 0>;
+ clocks = <&clock 318>;
+ clock-names = "tmu_apbif";
+ };
+
+ /* tmu for CPU3 */
+ tmu@1006c000 {
+ compatible = "samsung,exynos5420-tmu";
+ /* 2nd reg is for the misplaced TRIMINFO register */
+ reg = <0x1006c000 0x100>, <0x100a 0x4>;
+ interrupts = <0 185 0>;
+ clocks = <&clock 318>, <&clock 319>;
+ clock-names = "tmu_apbif", "tmu_apbif_triminfo";
+ };
+
+ /* tmu for GPU */
+ tmu@100a {
+ compatible = "samsung,exynos5420-tmu";
+ /* 2nd reg is for the misplaced TRIMINFO register */
+ reg = <0x100a 0x100>, <0x10068000 0x4>;
+ interrupts = <0 215 0>;
+ clocks = <&clock 319>, <&clock 318>;
+ clock-names = "tmu_apbif", "tmu_apbif_triminfo";
+ };
};
--
1.7.10.4
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[PATCH] thermal: exynos: handle gate clock for misplaced TRIMINFO register
On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
should be acompanied by enabling the respective clock.
This patch which allow for a "clk_sec" clock to be specified in the
device-tree which will be ungated when accessing the TRIMINFO register.
Signed-off-by: Andrew Bresticker
Signed-off-by: Naveen Krishna Chatradhi
---
drivers/thermal/samsung/exynos_tmu.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index b54825a..33edd1a 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -47,6 +47,7 @@
* @irq_work: pointer to the irq work structure.
* @lock: lock to implement synchronization.
* @clk: pointer to the clock structure.
+ * @clk_sec: pointer to the clock structure for accessing the base_second.
* @temp_error1: fused value of the first point trim.
* @temp_error2: fused value of the second point trim.
* @regulator: pointer to the TMU regulator structure.
@@ -61,7 +62,7 @@ struct exynos_tmu_data {
enum soc_type soc;
struct work_struct irq_work;
struct mutex lock;
- struct clk *clk;
+ struct clk *clk, *clk_sec;
u8 temp_error1, temp_error2;
struct regulator *regulator;
struct thermal_sensor_conf *reg_conf;
@@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device
*pdev)
mutex_lock(&data->lock);
clk_enable(data->clk);
+ if (!IS_ERR(data->clk_sec))
+ clk_enable(data->clk_sec);
if (TMU_SUPPORTS(pdata, READY_STATUS)) {
status = readb(data->base + reg->tmu_status);
@@ -306,6 +309,8 @@ skip_calib_data:
out:
clk_disable(data->clk);
mutex_unlock(&data->lock);
+ if (!IS_ERR(data->clk_sec))
+ clk_disable(data->clk_sec);
return ret;
}
@@ -457,12 +462,16 @@ static void exynos_tmu_work(struct work_struct *work)
const struct exynos_tmu_registers *reg = pdata->registers;
unsigned int val_irq, val_type;
+ if (!IS_ERR(data->clk_sec))
+ clk_enable(data->clk_sec);
/* Find which sensor generated this interrupt */
if (reg->tmu_irqstatus) {
val_type = readl(data->base_second + reg->tmu_irqstatus);
if (!((val_type >> data->id) & 0x1))
goto out;
}
+ if (!IS_ERR(data->clk_sec))
+ clk_disable(data->clk_sec);
exynos_report_trigger(data->reg_conf);
mutex_lock(&data->lock);
@@ -641,6 +650,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
if (ret)
return ret;
+ data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_sec");
+ if (!IS_ERR(data->clk_sec)) {
+ ret = clk_prepare(data->clk_sec);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to get clock\n");
+ return PTR_ERR(data->clk_sec);
+ }
+ }
+
if (pdata->type == SOC_ARCH_EXYNOS4210 ||
pdata->type == SOC_ARCH_EXYNOS4412 ||
pdata->type == SOC_ARCH_EXYNOS5250 ||
@@ -713,6 +731,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
return 0;
err_clk:
clk_unprepare(data->clk);
+ if (!IS_ERR(data->clk_sec))
+ clk_unprepare(data->clk_sec);
return ret;
}
@@ -725,6 +745,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
exynos_unregister_thermal(data->reg_conf);
clk_unprepare(data->clk);
+ if (!IS_ERR(data->clk_sec))
+ clk_unprepare(data->clk_sec);
if (!IS_ERR(data->regulator))
regulator_disable(data->regulator);
--
1.7.10.4
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[PATCH V6 2/3] ARM: dts: add watchdog device nodes for Exynos5250 and Exynos5420
Adds watchdog device nodes to the DT device list for Exynos5250 and Exynos5420
Signed-off-by: Leela Krishna Amudala
---
arch/arm/boot/dts/exynos5.dtsi|7 ---
arch/arm/boot/dts/exynos5250.dtsi |6 +-
arch/arm/boot/dts/exynos5420.dtsi |9 +
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index ad6e47c9..e6ab5d9 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -81,13 +81,6 @@
status = "disabled";
};
- watchdog {
- compatible = "samsung,s3c2410-wdt";
- reg = <0x101D 0x100>;
- interrupts = <0 42 0>;
- status = "disabled";
- };
-
fimd@1440 {
compatible = "samsung,exynos5250-fimd";
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index c4a8662..42b8682 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -158,9 +158,13 @@
interrupts = <0 47 0>;
};
- watchdog {
+ watchdog@101D {
+ compatible = "samsung,exynos5250-wdt";
+ reg = <0x101D 0x100>;
+ interrupts = <0 42 0>;
clocks = <&clock 336>;
clock-names = "watchdog";
+ samsung,syscon-phandle = <&pmu_syscon>;
};
g2d@1085 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6ffefd1..4f5fda3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -369,4 +369,13 @@
clock-names = "gscl";
samsung,power-domain = <&gsc_pd>;
};
+
+watchdog@101D {
+ compatible = "samsung,exynos5420-wdt";
+ reg = <0x101D 0x100>;
+ interrupts = <0 42 0>;
+ clocks = <&clock 316>;
+ clock-names = "watchdog";
+ samsung,syscon-phandle = <&pmu_syscon>;
+};
};
--
1.7.10.4
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[PATCH V6 0/3] Add watchdog DT nodes and use syscon regmap interfac to configure pmu registers
This patchset does the following things - Adds pmusysreg device node to exynos5.dtsi file - Adds watchdog DT nodes to Exynos5250 and 5420 - Uses syscon regmap interface to configure pmu registers to mask/unmask enable/disable of watchdog. This patch set is rebased on Kgene's for-next branch and tested on SMDK5420 Changes since V5: - removed status property in DT nodes - changed the return type for the function s3c2410wdt_mask_and_disable_reset() and handled error cases - Handled to get driver data in non-DT cases - Addressed comments given by Tomasz Figa Changes since V4: - changed the node name from pmusysreg to syscon and node label from pmu_sys_reg to pmu_syscon - changed the property name from samsung,pmusysreg to samsung,syscon-phandle - used regmap_update_bits instead of remap_read/regmap_write - Addressed other comments given by Tomasz Figa Changes since V3: - changed the compatible strings for watchdog node - splitted up adding pmusysreg node and made it separate patch - Addressed comments given by Sachin Kamat Changes since V2: - used syscon regmap interface to configure pmu registers in WDT driver (suggested by Tomasz Figa ) Changes since V1: - Added new compatible string for Exynos5 SoCs - Introduced quirk mechanism to program PMU registers - Addressed comments given by Tomasz Figa Leela Krishna Amudala (3): ARM: dts: Add pmu sysreg node to Exynos5 dtsi file ARM: dts: add watchdog device nodes for Exynos5250 and Exynos5420 watchdog: s3c2410_wdt: use syscon regmap interface to configure pmu register .../devicetree/bindings/watchdog/samsung-wdt.txt | 21 ++- arch/arm/boot/dts/exynos5.dtsi | 12 +- arch/arm/boot/dts/exynos5250.dtsi |6 +- arch/arm/boot/dts/exynos5420.dtsi |9 ++ drivers/watchdog/s3c2410_wdt.c | 139 ++-- 5 files changed, 170 insertions(+), 17 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V6 1/3] ARM: dts: Add pmu sysreg node to Exynos5 dtsi file
This patch adds pmusysreg node to Exynos5 dtsi file to handle PMU
register accesses in a centralized way using syscon driver
Signed-off-by: Leela Krishna Amudala
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/exynos5.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index e52b038..ad6e47c9 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -106,4 +106,9 @@
#size-cells = <0>;
status = "disabled";
};
+
+ pmu_syscon: syscon@1004 {
+ compatible = "syscon";
+ reg = <0x1004 0x5000>;
+ };
};
--
1.7.10.4
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[PATCH V6 3/3] watchdog: s3c2410_wdt: use syscon regmap interface to configure pmu register
The syscon regmap interface is used to configure AUTOMATIC_WDT_RESET_DISABLE
and MASK_WDT_RESET_REQUEST registers of PMU to mask/unmask enable/disable of
watchdog in probe and s2r scenarios.
Signed-off-by: Leela Krishna Amudala
---
.../devicetree/bindings/watchdog/samsung-wdt.txt | 21 ++-
drivers/watchdog/s3c2410_wdt.c | 139 ++--
2 files changed, 151 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
index 2aa486c..5dea363 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
@@ -5,10 +5,29 @@ after a preset amount of time during which the WDT reset
event has not
occurred.
Required properties:
-- compatible : should be "samsung,s3c2410-wdt"
+- compatible : should be one among the following
+ (a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs
+ (b) "samsung,exynos5250-wdt" for Exynos5250
+ (c) "samsung,exynos5420-wdt" for Exynos5420
+
- reg : base physical address of the controller and length of memory mapped
region.
- interrupts : interrupt number to the cpu.
+- samsung,syscon-phandle : reference to syscon node (This property required
only
+ in case of compatible being "samsung,exynos5250-wdt" or
"samsung,exynos5420-wdt".
+ In case of Exynos5250 and 5420 this property points to syscon node
holding the PMU
+ base address)
Optional properties:
- timeout-sec : contains the watchdog timeout in seconds.
+
+Example:
+
+watchdog@101D {
+ compatible = "samsung,exynos5250-wdt";
+ reg = <0x101D 0x100>;
+ interrupts = <0 42 0>;
+ clocks = <&clock 336>;
+ clock-names = "watchdog";
+ samsung,syscon-phandle = <&pmu_sys_reg>;
+};
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 23aad7c..a151c20 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -41,6 +41,8 @@
#include
#include
#include
+#include
+#include
#define S3C2410_WTCON 0x00
#define S3C2410_WTDAT 0x04
@@ -61,6 +63,10 @@
#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
+#define WDT_DISABLE_REG_OFFSET 0x0408
+#define WDT_MASK_RESET_REG_OFFSET 0x040c
+#define QUIRK_NEEDS_PMU_CONFIG (1 << 0)
+
static bool nowayout = WATCHDOG_NOWAYOUT;
static int tmr_margin;
static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
@@ -84,6 +90,13 @@ MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to
ignore reboots, "
"0 to reboot (default 0)");
MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
+struct s3c2410_wdt_variant {
+ int disable_reg;
+ int mask_reset_reg;
+ int mask_bit;
+ u32 quirks;
+};
+
struct s3c2410_wdt {
struct device *dev;
struct clk *clock;
@@ -94,7 +107,40 @@ struct s3c2410_wdt {
unsigned long wtdat_save;
struct watchdog_device wdt_device;
struct notifier_block freq_transition;
+ struct s3c2410_wdt_variant *pmu_config;
+ struct regmap *pmureg;
+};
+
+#ifdef CONFIG_OF
+static const struct s3c2410_wdt_variant pmu_config_s3c2410 = {
+ .quirks = 0
+};
+
+static const struct s3c2410_wdt_variant pmu_config_5250 = {
+ .disable_reg = WDT_DISABLE_REG_OFFSET,
+ .mask_reset_reg = WDT_MASK_RESET_REG_OFFSET,
+ .mask_bit = 20,
+ .quirks = QUIRK_NEEDS_PMU_CONFIG
+};
+
+static const struct s3c2410_wdt_variant pmu_config_5420 = {
+ .disable_reg = WDT_DISABLE_REG_OFFSET,
+ .mask_reset_reg = WDT_MASK_RESET_REG_OFFSET,
+ .mask_bit = 0,
+ .quirks = QUIRK_NEEDS_PMU_CONFIG
+};
+
+static const struct of_device_id s3c2410_wdt_match[] = {
+ { .compatible = "samsung,s3c2410-wdt",
+ .data = &pmu_config_s3c2410 },
+ { .compatible = "samsung,exynos5250-wdt",
+ .data = &pmu_config_5250 },
+ { .compatible = "samsung,exynos5420-wdt",
+ .data = &pmu_config_5420 },
+ {},
};
+MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
+#endif
/* watchdog control routines */
@@ -111,6 +157,30 @@ static inline struct s3c2410_wdt *freq_to_wdt(struct
notifier_block *nb)
return container_of(nb, struct s3c2410_wdt, freq_transition);
}
+static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool
mask)
+{
+ int ret;
+ u32 mask_val = 1 << wdt->pmu_config->mask_bit;
+ u32 val = 0;
+
+ if (mask)
+ val = mask_val;
+
+ ret = regmap_update_bits(wdt->pmureg,
+ wdt->pmu_config->disable_reg,
+ mask_val, val);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_update_bits(wdt->pmureg,
+
Re: [PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct
Hi Bartlomiej, On 7 November 2013 16:18, Bartlomiej Zolnierkiewicz wrote: > > Hi, > > On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote: >> On Exynos5250, the FALL interrupt related en, status and clear bits are >> available at an offset of >> 16 in INTEN, INTSTAT registers and at an offset of >> 12 in INTCLEAR register. >> >> On Exynos5420, the FALL interrupt related en, status and clear bits are >> available at an offset of >> 16 in INTEN, INTSTAT and INTCLEAR registers. >> >> On Exynos5440, >> the FALL_IRQEN bits are at an offset of 4 >> and the RISE_IRQEN bits are at an offset of 0 >> >> This patch introduces a new bit field intclr_fall_shift to handle the >> offset for exyns5250 and exynos5440 >> Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and >> EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field > > Thanks for fixing this. All three patches look good to me now. > > Reviewed-by: Bartlomiej Zolnierkiewicz Thanks for all the following up. > > Best regards, > -- > Bartlomiej Zolnierkiewicz > Samsung R&D Institute Poland > Samsung Electronics > -- Shine bright, (: Nav :) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct
Hi, On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote: > On Exynos5250, the FALL interrupt related en, status and clear bits are > available at an offset of > 16 in INTEN, INTSTAT registers and at an offset of > 12 in INTCLEAR register. > > On Exynos5420, the FALL interrupt related en, status and clear bits are > available at an offset of > 16 in INTEN, INTSTAT and INTCLEAR registers. > > On Exynos5440, > the FALL_IRQEN bits are at an offset of 4 > and the RISE_IRQEN bits are at an offset of 0 > > This patch introduces a new bit field intclr_fall_shift to handle the > offset for exyns5250 and exynos5440 > Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and > EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field Thanks for fixing this. All three patches look good to me now. Reviewed-by: Bartlomiej Zolnierkiewicz Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4] spi: s3c64xx: Enable Word transfer
On 11/07/2013 10:39 AM, Tomasz Figa wrote: [CCing Sylwester, Andrzej and Lukasz] On Thursday 07 of November 2013 14:52:36 Rajeshwari Birje wrote: Hi Mark Brown, On Wed, Nov 6, 2013 at 1:51 PM, Mark Brown wrote: On Wed, Nov 06, 2013 at 10:23:07AM +0530, Rajeshwari Birje wrote: On Thu, Oct 31, 2013 at 6:07 PM, Tomasz Figa wrote: The driver as of today's linux-next does not seem to support word transfers. Do you have some additional, out of tree patches that add such support? Yes I set the bits_per_word to 32/16 in drivers/mtd/devices/m25p80.c m25p_probe function and the call spi_setup(spi). This sound wrong. If you just set bits per word then this should result in data corruption on the bus since it should cause the words written to the bus to be reordered. Are you sure that the existing driver isn't working correctly? The reordering of the words is taken care by the Swap configuration (swap_cfg) register, which I have set for both 16 and 32 bits_per_word case. I have tested this patch and works fine for me and also has improved the timing performance. This driver seems to have already worked fine with 32 bits per word, using the s5c73m3 camera sensor, which uses SPI for firmware upload. Yes, You are right. Sylwester, Andrzej or Lukasz: Can you confirm this? Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4] spi: s3c64xx: Enable Word transfer
[CCing Sylwester, Andrzej and Lukasz] On Thursday 07 of November 2013 14:52:36 Rajeshwari Birje wrote: > Hi Mark Brown, > > On Wed, Nov 6, 2013 at 1:51 PM, Mark Brown wrote: > > On Wed, Nov 06, 2013 at 10:23:07AM +0530, Rajeshwari Birje wrote: > >> On Thu, Oct 31, 2013 at 6:07 PM, Tomasz Figa wrote: > >> > The driver as of today's linux-next does not seem to support word > >> > transfers. Do you have some additional, out of tree patches that > >> > add > >> > such support? > >> > >> Yes I set the bits_per_word to 32/16 in drivers/mtd/devices/m25p80.c > >> m25p_probe function and the call spi_setup(spi). > > > > This sound wrong. If you just set bits per word then this should > > result in data corruption on the bus since it should cause the words > > written to the bus to be reordered. Are you sure that the existing > > driver isn't working correctly? > > The reordering of the words is taken care by the Swap configuration > (swap_cfg) register, which I have set for both 16 and 32 bits_per_word > case. I have tested this patch and works fine for me and also has > improved the timing performance. This driver seems to have already worked fine with 32 bits per word, using the s5c73m3 camera sensor, which uses SPI for firmware upload. Sylwester, Andrzej or Lukasz: Can you confirm this? Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4] spi: s3c64xx: Enable Word transfer
Hi Mark Brown, On Wed, Nov 6, 2013 at 1:51 PM, Mark Brown wrote: > On Wed, Nov 06, 2013 at 10:23:07AM +0530, Rajeshwari Birje wrote: >> On Thu, Oct 31, 2013 at 6:07 PM, Tomasz Figa wrote: > >> > The driver as of today's linux-next does not seem to support word >> > transfers. Do you have some additional, out of tree patches that add >> > such support? > >> Yes I set the bits_per_word to 32/16 in drivers/mtd/devices/m25p80.c >> m25p_probe function and the call spi_setup(spi). > > This sound wrong. If you just set bits per word then this should result > in data corruption on the bus since it should cause the words written to > the bus to be reordered. Are you sure that the existing driver isn't > working correctly? The reordering of the words is taken care by the Swap configuration (swap_cfg) register, which I have set for both 16 and 32 bits_per_word case. I have tested this patch and works fine for me and also has improved the timing performance. -- Regards, Rajeshwari Shinde -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +
include/dt-bindings/clock/exynos5410.h | 175 +++
4 files changed, 452 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * sus
[PATCH v3 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e991739 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..06ae479
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ oscclk: oscclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..9921b66
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cci-control-port = <&cci_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cci-control-port = <&cci_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ cci-control-port = <&cci_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+
[PATCH v3 0/4] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.12. Has been tested on Exynos 5410 reference board (exynos_defconfig). Thanks, Vyacheslav. Changelog: v3: In drivers/clk/samsung/clk-exynos5410.c 1. Fixed rate clock "samsung,clock-oscclk" removed. In arch/arm/boot/dts/exynos5410.dtsi 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. Fixed rate oscclk clock added. In arch/arm/mach-exynos/edcs.c 1. Added write memory barrier in exynos_core_power_control function. 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed. 3. #define added for some magic constants. 4. Disabled the GIC CPU interface in exynos_power_down function. v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status="disabled" field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = "okay" field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. "kfs_" prefix replaced with "edcs_" 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (4): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: EXYNOS: add Exynos Dual Cluster Support ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 + arch/arm/boot/dts/exynos5410.dtsi | 209 arch/arm/mach-exynos/Kconfig | 12 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 278 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 239 ++ include/dt-bindings/clock/exynos5410.h | 175 + 14 files changed, 1047 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 arch/arm/mach-exynos/edcs.c create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 278 ++
2 files changed, 280 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..980bfdd
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,278 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+(_nr) * EDCS_CPUS_PER_CLUSTER)
+
+#define SECONDARY_RESET(1 << 1)
+#define REG_ENTRY_ADDR (S5P_VA_SYSRAM_NS + 0x1c)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((readl_relaxed(EDCS_CORE_STATUS(offset)) & 0x3) != value) {
+ wmb();
+ writel_relaxed(value, EDCS_CORE_CONFIGURATION(offset));
+ }
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, false);
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ writel_relaxed(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(&edcs_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ set_boot_flag(cpu, SECONDARY_RESET);
+ exynos_core_power_up(cpu, cluster);
+ } else if (edcs_use_count[cpu][cluster] != 2) {
+ /*
+* The only possible values are:
+* 0 = CPU down
+* 1 = CPU (still) up
+* 2 = CPU requested to be up before it had a chance
+* to actually make itself down.
+* Any other value is a bug.
+*/
+ BUG();
+ }
+
+ arch_spin_unlock(&edcs_lock);
+ local_irq_enable();
+
+ return 0;
+}
+static void exynos_power_down(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man = false, skip_wfi = false;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: CORE%d on CLUSTER %d\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ __mcpm_cpu_going_down(cpu, cluster);
+
+ arch_spin_lock(&edcs_lock);
+ BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+ edcs_use_count[cpu][cluster]--;
+ if
[PATCH v3 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Kconfig | 12
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..9ea1799 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select MCPM
+ select ARM_CCI
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_S
