Hello!
> > + for_each_child_of_node(np, child)
> > + decode_sromc(srom, child);
>
> You ignore the return value here so bank may be not configured but
> device probe will return 0.
Yes, so that banks which are described correctly, will still be configured.
> Maybe clean up and fai
On 25.10.2015 08:58, Tobias Jakobi wrote:
> Hello Krzysztof,
>
>
> Krzysztof Kozlowski wrote:
>> On 20.10.2015 01:11, Tobias Jakobi wrote:
>>> Hello Krzysztof,
>>>
>>> I can confirm that this also works on a Odroid-X2, so I guess it's safe
>>> to enable the PRNG for all Exynos4412-based Odroid de
On 29.10.2015 13:58, Alim Akhtar wrote:
> From: Thomas Abraham
>
> Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
> is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.
>
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Thomas Abraham
> Signed-o
On 29.10.2015 13:58, Alim Akhtar wrote:
> RTC found in s2mps15 is almost same as one found on s2mps14/13
> with few differences in RTC_UPDATE register fields, like
> bit fields are changed for WUDR and AUDR.
> This patch add required changes to enable s2mps15 rtc timer.
>
> Cc: Alexandre Belloni
On 10/29/2015 10:37 AM, Krzysztof Kozlowski wrote:
On 29.10.2015 13:58, Alim Akhtar wrote:
RTC found in s2mps15 is almost same as one found on s2mps14/13
with few differences in RTC_UPDATE register fields, like
bit fields are changed for WUDR and AUDR.
This patch add required changes to enable
On 29.10.2015 13:58, Alim Akhtar wrote:
> RTC found in s2mps15 is almost same as one found on s2mps14/13
> with few differences in RTC_UPDATE register fields, like
> bit fields are changed for WUDR and AUDR.
> This patch add required changes to enable s2mps15 rtc timer.
>
> Cc: Alexandre Belloni
Samsung's S2MPS15 PMIC is targetted to be used with Samsung's Exynos7 SoC.
The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators, RTC, three 32.768 KHz clock outputs and allows
programming these blocks via a I2C interface. This patch series adds
From: Thomas Abraham
Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
clock outputs and battery charger. This patch adds initial support for
LDO and buck regulators of S2MPS15 device.
Signed-off-b
From: Thomas Abraham
Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device
is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators.
Cc: devicet...@vger.kernel.org
Signed-off-by: Thomas Abraham
Signed-off-by: Alim Akhtar
Reviewed-by: Krzysztof Kozlowski
Ac
From: Thomas Abraham
The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains
27 LDO and 10 Buck regulators and allows programming these regulators via a
I2C interface. This patch adds initial support for LDO/Buck regulators of
S2MPS15 PMIC.
Signed-off-by: Thomas Abraham
Sig
RTC found in s2mps15 is almost same as one found on s2mps14/13
with few differences in RTC_UPDATE register fields, like
bit fields are changed for WUDR and AUDR.
This patch add required changes to enable s2mps15 rtc timer.
Cc: Alexandre Belloni
Signed-off-by: Alim Akhtar
---
drivers/rtc/rtc-s5m
On 10/28/2015 07:21 PM, Lee Jones wrote:
On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
W dniu 28.10.2015 o 17:46, Lee Jones pisze:
On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
On 26.10.2015 23:34, Lee Jones wrote:
On Mon, 26 Oct 2015, Alim Akhtar wrote:
From: Thomas Abraham
Add s
Hi, All.
Is there any other opinion about this patch?
Best Regards,
Jaehoon Chung
On 09/16/2015 03:43 PM, Shawn Lin wrote:
> DesignWare MMC Controller's transfer mode should be decided
> at runtime instead of compile-time. So we remove this config
> option and read dw_mmc's register to select D
Hi, All.
Is there any other opinion about this patch?
Best Regards,
Jaehoon Chung
On 09/16/2015 03:43 PM, Shawn Lin wrote:
> DesignWare MMC Controller's transfer mode should be decided
> at runtime instead of compile-time. So we remove this config
> option and read dw_mmc's register to select DM
On 28.10.2015 16:57, Pavel Fedin wrote:
> Add documentation for new properties, allowing bank configuration.
>
> Signed-off-by: Pavel Fedin
> ---
> .../bindings/arm/samsung/exynos-srom.txt | 24
> +-
> 1 file changed, 23 insertions(+), 1 deletion(-)
You missed her
On 28.10.2015 16:57, Pavel Fedin wrote:
> Bindings are based on u-boot implementation, however they are stored in
> subnodes, providing support for more than one bank.
>
> Since the driver now does more than suspend-resume support, dependency on
> CONFIG_PM is removed.
>
> Signed-off-by: Pavel Fe
On 29.10.2015 11:06, Pankaj Dubey wrote:
> Hi Pavel,
>
> On 29 October 2015 at 07:11, Krzysztof Kozlowski
> wrote:
>> On 28.10.2015 18:36, Pavel Fedin wrote:
>>> Since 8cfc7fdd33080e30b86d21b1a8c9ad0686427ddc ("ARM: EXYNOS: move restart
>>
>> This should be sufficient (although full is okay as we
On 29 October 2015 at 07:10, Krzysztof Kozlowski
wrote:
> The Exynos5420 instance of exynos_pmu_data structure is not modified and
> can be made const.
>
> Signed-off-by: Krzysztof Kozlowski
> Suggested-by: Pavel Fedin
Reviewed-by: Pankaj Dubey
Thanks,
Pankaj Dubey
>
> --
> To unsubscribe fr
Hi Pavel,
On 29 October 2015 at 07:11, Krzysztof Kozlowski
wrote:
> On 28.10.2015 18:36, Pavel Fedin wrote:
>> Since 8cfc7fdd33080e30b86d21b1a8c9ad0686427ddc ("ARM: EXYNOS: move restart
>
> This should be sufficient (although full is okay as well):
> $ git config core.abbrev 12
>
>> code into pmu
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused head file.
Chang
On 28.10.2015 18:36, Pavel Fedin wrote:
> Since 8cfc7fdd33080e30b86d21b1a8c9ad0686427ddc ("ARM: EXYNOS: move restart
This should be sufficient (although full is okay as well):
$ git config core.abbrev 12
> code into pmu driver") PMU support is required in order for the reboot to
> work. Unfortuna
The Exynos5420 instance of exynos_pmu_data structure is not modified and
can be made const.
Signed-off-by: Krzysztof Kozlowski
Suggested-by: Pavel Fedin
---
arch/arm/mach-exynos/pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct rockchip_dp
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> index 7a3a9cd..9905081 100644
> --- a/Documentation/devicetree/bindings/display/
Another ping!
With best wishes,
Tobias
Tobias Jakobi wrote:
> Hello,
>
> this series mostly touches G2D code. It introduces the following:
>
> (1) drmHandleEvent2() is added to enable processing of vendor-specific
> events. This will be used to expose asynchronous operation of the
> G2
On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
> W dniu 28.10.2015 o 17:46, Lee Jones pisze:
> > On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
> >
> >> On 26.10.2015 23:34, Lee Jones wrote:
> >>> On Mon, 26 Oct 2015, Alim Akhtar wrote:
> >>>
> From: Thomas Abraham
>
> Add suppo
W dniu 28.10.2015 o 20:21, Alim Akhtar pisze:
> Hello,
>
> On 10/28/2015 02:16 PM, Lee Jones wrote:
>> On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
>>
>>> On 26.10.2015 23:34, Lee Jones wrote:
On Mon, 26 Oct 2015, Alim Akhtar wrote:
> From: Thomas Abraham
>
> Add support
W dniu 28.10.2015 o 17:46, Lee Jones pisze:
> On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
>
>> On 26.10.2015 23:34, Lee Jones wrote:
>>> On Mon, 26 Oct 2015, Alim Akhtar wrote:
>>>
From: Thomas Abraham
Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
>
On 28/10/2015 at 22:31:48 +0900, Krzysztof Kozlowski wrote :
> > So you don't care about DT backward compatibility because when a
> > workaround will be needed for one of the IPs, then you will have to
> > update the old dtb to use it.
>
> Nope, DTB does not contain the name for RTC driver (s2mps1
W dniu 28.10.2015 o 19:30, Alim Akhtar pisze:
> Hi Alexandre,
>
> On 10/28/2015 03:18 PM, Alexandre Belloni wrote:
>> On 28/10/2015 at 12:31:43 +0900, Krzysztof Kozlowski wrote :
>>> The s2mps13 clock driver added new name and compatible... which was
>>> probably totally unneeded (I missed that du
W dniu 28.10.2015 o 18:48, Alexandre Belloni pisze:
> On 28/10/2015 at 12:31:43 +0900, Krzysztof Kozlowski wrote :
>> The s2mps13 clock driver added new name and compatible... which was
>> probably totally unneeded (I missed that during review). We don't have
>> to make this as a rule...
>>
>> Sinc
W dniu 28.10.2015 o 19:14, Alexandre Belloni pisze:
> Hi,
>
> There are three pending patches (from 2010 and 2011) for rtc-s3c. I'd
> like to get an update and either drop or apply those.
>
> Can someone take a few minutes to review them?
>
> The patches are:
> http://patchwork.ozlabs.org/patch/
Hello,
On 10/28/2015 02:16 PM, Lee Jones wrote:
On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
On 26.10.2015 23:34, Lee Jones wrote:
On Mon, 26 Oct 2015, Alim Akhtar wrote:
From: Thomas Abraham
Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
PMIC supports 27 LD
Hello Ulf,
On 10/27/2015 11:10 AM, Ulf Hansson wrote:
> On 21 October 2015 at 17:15, Javier Martinez Canillas
> wrote:
>> The pwrseq_emmc driver does a eMMC card reset before a system reboot to
>> allow broken or limited ROM boot-loaders (that don't have an eMMC reset
>> logic) to be able to read
Hi Alexandre,
On 10/28/2015 03:18 PM, Alexandre Belloni wrote:
On 28/10/2015 at 12:31:43 +0900, Krzysztof Kozlowski wrote :
The s2mps13 clock driver added new name and compatible... which was
probably totally unneeded (I missed that during review). We don't have
to make this as a rule...
Since
Hi,
There are three pending patches (from 2010 and 2011) for rtc-s3c. I'd
like to get an update and either drop or apply those.
Can someone take a few minutes to review them?
The patches are:
http://patchwork.ozlabs.org/patch/71318/
http://patchwork.ozlabs.org/patch/99857/
http://patchwork.ozlab
On 28/10/2015 at 12:31:43 +0900, Krzysztof Kozlowski wrote :
> The s2mps13 clock driver added new name and compatible... which was
> probably totally unneeded (I missed that during review). We don't have
> to make this as a rule...
>
> Since we do not have any data about future workarounds and the
Hello!
> There is no offset such as SROM_BC{4,5} at least in these SoC
> manuals. Accordingly I modified size from 0x100 to 0x10.
0x10 is indeed an offset for SROM_BC3. But, it occupies 4 bytes by itself, and
you have to include it, because you are describing
*SIZE* of the region. :)
Kind reg
Since 8cfc7fdd33080e30b86d21b1a8c9ad0686427ddc ("ARM: EXYNOS: move restart
code into pmu driver") PMU support is required in order for the reboot to
work. Unfortunately, there is currently no PMU support for 5410.
This patch adds exynos5410-pmu to the list of recognized devices. It is
okay for the
On 28.10.2015 18:30, Pankaj Dubey wrote:
> Hi
>
> On Wednesday 28 October 2015 12:54 PM, Krzysztof Kozlowski wrote:
>> On 28.10.2015 16:06, Pavel Fedin wrote:
>>> Hello!
>>>
> +sromc: sromc@1225 {
> +compatible = "samsung,exynos-srom";
> +reg = <0x
Hi
On Wednesday 28 October 2015 12:54 PM, Krzysztof Kozlowski wrote:
On 28.10.2015 16:06, Pavel Fedin wrote:
Hello!
+ sromc: sromc@1225 {
+ compatible = "samsung,exynos-srom";
+ reg = <0x1225 0x10>;
Isn't 0x10 too small (SR
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes
Hello!
> The noticeable change between v4.1 and v4.2 was for example:
> c4241a582d22 ("ARM: EXYNOS: use PS_HOLD based poweroff for all supported
> SoCs")
First of all, sorry for misinforming you. It was not v4.1 which worked, but
3.18 one. I never ran 4.1 on this board, it's my
memory's fault.
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- S
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix co
On Wed, 28 Oct 2015, Krzysztof Kozlowski wrote:
> On 26.10.2015 23:34, Lee Jones wrote:
> > On Mon, 26 Oct 2015, Alim Akhtar wrote:
> >
> >> From: Thomas Abraham
> >>
> >> Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
> >> PMIC supports 27 LDO regulators, 10 buck reg
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepa
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit message. (Kishon)
Changes in v6: None
Changes in v5:
- Split
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
C
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7G
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
control
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
-
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
--
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compati
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
Reviewed-by: Krzyszt
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
C
On 28.10.2015 17:00, Pavel Fedin wrote:
> Hello!
>
>> The Exynos5410 in current form does not have suspend capability. During
>> boot you should see in dmesg:
>> Failed to find PMU node
>> coming from mach-exynos/suspend.c.
>
> Indeed. By the way, can this be a reason why reboot stopped wo
Hello!
> The Exynos5410 in current form does not have suspend capability. During
> boot you should see in dmesg:
> Failed to find PMU node
> coming from mach-exynos/suspend.c.
Indeed. By the way, can this be a reason why reboot stopped working? It worked
in v4.1. Isn't this a regression?
Add documentation for new properties, allowing bank configuration.
Signed-off-by: Pavel Fedin
---
.../bindings/arm/samsung/exynos-srom.txt | 24 +-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-sro
This patch extends Exynos SROM controller driver with ability to configure
controller outputs and enables SMSC9115 Ethernet chip on SMDK5410 board,
which is connected via SROMc bank #3.
With this patchset, support for the whole existing SMDK range can be added.
Actually, only bank number is differ
This machine uses own SoC device tree file, add missing part.
Signed-off-by: Pavel Fedin
---
arch/arm/boot/dts/exynos5410.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
index 4603356..e2b58f8 100644
--- a/arch/
The chip is smsc9115, connected via SROMc bank 3. Additionally, some GPIO
initialization is required.
Signed-off-by: Pavel Fedin
---
arch/arm/boot/dts/exynos5410-smdk5410.dts | 42 +++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410-smdk541
Bindings are based on u-boot implementation, however they are stored in
subnodes, providing support for more than one bank.
Since the driver now does more than suspend-resume support, dependency on
CONFIG_PM is removed.
Signed-off-by: Pavel Fedin
---
arch/arm/mach-exynos/Kconfig | 2 +-
d
On 28.10.2015 16:49, Pavel Fedin wrote:
> Hello!
>
>> The question is - do you prefer us to send a following up patch or to
>> fix it by amending the commit?
>>
>> Here is a fix which can be squashed into these two commits:
>
> By the way, since we are discussing fixing these commits...
> Afte
Hello!
> The question is - do you prefer us to send a following up patch or to
> fix it by amending the commit?
>
> Here is a fix which can be squashed into these two commits:
By the way, since we are discussing fixing these commits...
After hardcoded SROMc handling has been removed, Exynos54
On 24.10.2015 06:26, Kukjin Kim wrote:
> The following changes since commit 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f:
>
> Linux 4.3-rc1 (2015-09-12 16:35:56 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> tags/sam
Hello!
> Yes. It hasn't been pulled yet by arm-soc... Let's wait Kukjin's opinion
> how to deal with exynos[45].dtsi.
I can simply include it into my patchset, two more lines aren't a problem for
me.
Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia
--
To
On 28.10.2015 16:06, Pavel Fedin wrote:
> Hello!
>
>>> + sromc: sromc@1225 {
>>> + compatible = "samsung,exynos-srom";
>>> + reg = <0x1225 0x10>;
>>
>> Isn't 0x10 too small (SROM_BC3 won't be mapped)?
>
> Muhaha, indeed, thanks for noticing
Hello!
> > + sromc: sromc@1225 {
> > + compatible = "samsung,exynos-srom";
> > + reg = <0x1225 0x10>;
>
> Isn't 0x10 too small (SROM_BC3 won't be mapped)?
Muhaha, indeed, thanks for noticing this.
By the way, i've just checked exynos4.dtsi
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