Re: [PATCH v2 0/4] Improvements on exynos7 clock
On 26/08/15 05:30, Alim Akhtar wrote: > This patch series are minor improvement over the current > exynos7 clock file. This fix some bugs and update the clock > bits as per user manual. That one applied as well, thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] Samsung clock changes for 3.19
Hi Mike, I've collected Exynos clk patches in this pull request, as Tomasz has been busy recently. This includes addition of clock controller drivers for Exynos4415 and Exynos7 SoCs and related refactoring of the Samsung common clk API. As I mentioned in my other e-mail, it might be sensible to put these patches into a separate topic branch, so Kukjin can pull it as a dependency for the related dts changes. There are also few Samsung clk cleanup patches not included here, I thought I'd send them separately. The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1: Linux 3.18-rc1 (2014-10-19 18:08:38 -0700) are available in the git repository at: git://linuxtv.org/snawrocki/samsung.git for-v3.19/exynos-clk for you to fetch changes up to 932e98224d5602be17ed61d0e057e9326f12b59d: clk: samsung: exynos7: add gate clock for ADC block (2014-10-31 10:45:54 +0100) Abhilash Kesavan (1): clk: samsung: exynos7: add gate clock for ADC block Chanwoo Choi (2): clk: samsung: Document binding for Exynos4415 clock controller clk: samsung: exynos4415: Add clocks using common clock framework Naveen Krishna Ch (8): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC clk: samsung: exynos7: add clocks for I2C block clk: samsung: exynos7: add clocks for MMC block clk: samsung: exynos7: add clocks for RTC block clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks .../devicetree/bindings/clock/exynos4415-clock.txt | 38 + .../devicetree/bindings/clock/exynos7-clock.txt| 93 ++ drivers/clk/samsung/Makefile |2 + drivers/clk/samsung/clk-exynos4415.c | 1142 drivers/clk/samsung/clk-exynos5260.c | 185 +--- drivers/clk/samsung/clk-exynos7.c | 743 + drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h |4 + drivers/clk/samsung/clk.c | 98 ++ drivers/clk/samsung/clk.h | 37 + include/dt-bindings/clock/exynos4415.h | 360 ++ include/dt-bindings/clock/exynos7-clk.h| 92 ++ 12 files changed, 2655 insertions(+), 164 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4415-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos4415.c create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos4415.h create mode 100644 include/dt-bindings/clock/exynos7-clk.h -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 7/7] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd4e81a..b4d1dc2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -134,6 +134,18 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 6/8] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd4e81a..b4d1dc2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -134,6 +134,18 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 6/8] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd4e81a..b4d1dc2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -134,6 +134,18 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 1/4] dwc3: exynos: Add support for SCLK present on Exynos7
Hello, Hi Anton, On 13.10.2014 06:54, Anton Tikhomirov wrote: Hi Vivek, Exynos7 also has a separate special gate clock going to the IP apart from the usual AHB clock. So add support for the same. As we discussed before, Exynos7 SoCs have 7 clocks to be controlled by the driver. Adding only sclk is not enough. I'm quite interested in this discussion. Has it happened on mailing lists? No, we used company messenger for the discussion. In general, previous SoCs also gave the possibility of controlling all the bus clocks separately, in addition to bulk gates, but there was no correct real advantage in using those, while burdening the clock tree with numerous clocks. Isn't Exynos7 similar in this aspect? Exynos7 doesn't have Gating all clocks for USBDRD30 bit. The clocks should be controlled separately. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-usb in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND] serial: samsung: Fix serial config dependencies for exynos7
On Mon, Nov 17, 2014 at 10:14:51AM +0530, Abhilash Kesavan wrote: From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- Acked-by: Greg Kroah-Hartman gre...@linuxfoundation.org -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] serial: samsung: Fix serial config dependencies for exynos7
On 11/19/14 16:56, Abhilash Kesavan wrote: From: Pankaj Dubey pankaj.du...@samsung.com Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org Acked-by: Greg Kroah-Hartman gre...@linuxfoundation.org --- Changes in v2: - Added Greg's ack and Kukjin Kim as a recepient Applied, thanks. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: clk: samsung: exynos7: Add clocks for MSCL block
Hi Pankaj, On 23/12/14 05:59, Pankaj Dubey wrote: diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index a79bf23..95c1160 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -34,6 +34,7 @@ #define DIV_TOPC00x0600 #define DIV_TOPC10x0604 #define DIV_TOPC30x060C +#define ENABLE_ACLK_TOPC1 0x0804 nit: Tab space between #define and ENABLE_ACLK_TOPC1, should be removed. I verified register settings and clock relationships are as per UM I have with me. So other than above nit, everything looks fine. Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks for you review, I have already fixed the whitespace issue when applying. -- Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL 2/5] Late Samsung DT64 update for v4.4
The following changes since commit 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f: Linux 4.3-rc1 (2015-09-12 16:35:56 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-dt64 for you to fetch changes up to c60ce7fe82c46d9480b85858828e3042dfe6c9bf: arm64: dts: Add BUS1 instance pinctrl support for exynos7 (2015-10-08 07:18:33 +0900) Samsung arm64 DT update for v4.4 - add BUS1 instance pinctrl support on exynos7 SoC Alim Akhtar (1): arm64: dts: Add BUS1 instance pinctrl support for exynos7 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 103 arch/arm64/boot/dts/exynos/exynos7.dtsi | 7 ++ 2 files changed, 110 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] arm64: dts: Exynos ARMv8 improvements for 4.4
Dear Kukjin, One ARMv8 DTS change for 4.4. Best regards, Krzysztof The following changes since commit 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f: Linux 4.3-rc1 (2015-09-12 16:35:56 -0700) are available in the git repository at: https://github.com/krzk/linux.git tags/samsung-dt64-4.4 for you to fetch changes up to 235c8e96f54a76bee201a7c86620c351a30b1ac6: arm64: dts: Add BUS1 instance pinctrl support for exynos7 (2015-09-16 09:03:09 +0900) Device Tree improvements for Exynos ARMv8 based boards: 1. Add a BUS1 instance pinctrl for Exynos7 SoC. Alim Akhtar (1): arm64: dts: Add BUS1 instance pinctrl support for exynos7 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 103 arch/arm64/boot/dts/exynos/exynos7.dtsi | 7 ++ 2 files changed, 110 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL] arm64: dts: Exynos ARMv8 improvements for 4.4
Krzysztof Kozlowski wrote: > > Dear Kukjin, > > One ARMv8 DTS change for 4.4. > > Best regards, > Krzysztof > > The following changes since commit 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f: > > Linux 4.3-rc1 (2015-09-12 16:35:56 -0700) > > are available in the git repository at: > > https://github.com/krzk/linux.git tags/samsung-dt64-4.4 > > for you to fetch changes up to 235c8e96f54a76bee201a7c86620c351a30b1ac6: > > arm64: dts: Add BUS1 instance pinctrl support for exynos7 (2015-09-16 > 09:03:09 +0900) > > > Device Tree improvements for Exynos ARMv8 based boards: > 1. Add a BUS1 instance pinctrl for Exynos7 SoC. > > > Alim Akhtar (1): > arm64: dts: Add BUS1 instance pinctrl support for exynos7 > > arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 103 > > arch/arm64/boot/dts/exynos/exynos7.dtsi | 7 ++ > 2 files changed, 110 insertions(+) Looks good to me. Since just one patch in this pull-request if you don't mind, let me take the patch directly with your signed-off. - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/6] Add initial support for pinctrl on Exynos7
On 29.09.2014 07:15, Abhilash Kesavan wrote: Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham Following patches have been tested on linux-next (20140926). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1) tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2) dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3) arch: arm64: enable support for Samsung Exynos7 SoC patchset (v5) http://www.spinics.net/lists/arm-kernel/msg364014.html Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 196 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 799 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi For patches 1-2, 4-6: Acked-by: Tomasz Figa tomasz.f...@gmail.com Linus, I have replied for patch 3 with 2 minor issues with coding style. If you don't mind them, feel free to take the whole series with my Ack. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/6] Add initial support for pinctrl on Exynos7
Changes since v3: - Changed variable name from exynos_wkup_irq_chip to irq_chip - Added acked-by tag from Tomasz Figa Changes since v2: - Added a .irq_chip field to the samsung_pin_bank struct - Consolidated the wakeup and gpio irqd_ops Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham Following patches have been tested on linux-next (20140926). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1) tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2) dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3) arch: arm64: enable support for Samsung Exynos7 SoC patchset (v5) http://www.spinics.net/lists/arm-kernel/msg364014.html Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 196 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 799 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Tue, Sep 30, 2014 at 8:00 PM, Abhilash Kesavan a.kesa...@samsung.com wrote: Changes since v3: - Changed variable name from exynos_wkup_irq_chip to irq_chip - Added acked-by tag from Tomasz Figa Changes since v2: - Added a .irq_chip field to the samsung_pin_bank struct - Consolidated the wakeup and gpio irqd_ops Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham Following patches have been tested on linux-next (20140926). https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ Following patches are required for this series: 1) tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2) dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3) arch: arm64: enable support for Samsung Exynos7 SoC patchset (v5) http://www.spinics.net/lists/arm-kernel/msg364014.html Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 196 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 799 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi Does this series look OK to you ? Regards, Abhilash -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/7] clk: samsung: exynos7: add clocks for RTC block
Hello Sylwester, On Mon, Oct 27, 2014 at 10:01 PM, Sylwester Nawrocki s.nawro...@samsung.com wrote: Hi, On 21/10/14 07:43, Abhilash Kesavan wrote: From: Naveen Krishna Ch naveenkrishna...@gmail.com Add clock support for the RTC block in Exynos7. Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- .../devicetree/bindings/clock/exynos7-clock.txt|5 ++ drivers/clk/samsung/clk-exynos7.c | 54 include/dt-bindings/clock/exynos7-clk.h| 17 +++--- 3 files changed, 70 insertions(+), 6 deletions(-) [...] diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index ff63c4e..3227679 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -11,12 +11,13 @@ #define _DT_BINDINGS_CLOCK_EXYNOS7_H /* TOPC */ -#define DOUT_ACLK_PERIS 1 -#define DOUT_SCLK_BUS0_PLL 2 -#define DOUT_SCLK_BUS1_PLL 3 -#define DOUT_SCLK_CC_PLL 4 -#define DOUT_SCLK_MFC_PLL5 -#define TOPC_NR_CLK 6 +#define DOUT_ACLK_CCORE_133 1 +#define DOUT_ACLK_PERIS 2 +#define DOUT_SCLK_BUS0_PLL 3 +#define DOUT_SCLK_BUS1_PLL 4 +#define DOUT_SCLK_CC_PLL 5 +#define DOUT_SCLK_MFC_PLL6 +#define TOPC_NR_CLK 7 Please don't do that, don't change the meaning of already defined clock identifiers. We should carefully assign the clock identifiers based on the SoC documentation beforehand, not at will when we see fit for development of the Linux driver. Please either add DOUT_ACLK_CCORE_133 at the end of list or move this change to the first patch in your series adding initial support for Exynos7 SoC. Thanks for reviewing this series and picking up the initial patchset. I will re-post this patchset with the ccore clock at the end of the list. All the future clock id entries will be added at the bottom of the list. Regards, Abhilash -- Thanks, Sylwester ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|3 +
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 247 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..4c69b66 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
- reg: physical base address of the controller and the length of
memory mapped region.
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0, mout_aclk_fsys1_200, mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+ MUX(0, mout_aclk_fsys0_200, mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+ MUX(0, mout_sclk_mmc2, mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+ MUX(0, mout_sclk_mmc1, mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+ MUX(0, mout_sclk_mmc0, mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+ DIV(DOUT_ACLK_FSYS1_200, dout_aclk_fsys1_200, mout_aclk_fsys1_200,
+ DIV_TOP13, 24, 4),
+ DIV(DOUT_ACLK_FSYS0_200, dout_aclk_fsys0_200, mout_aclk_fsys0_200,
+ DIV_TOP13, 28, 4),
+
+ DIV(DOUT_SCLK_MMC2, dout_sclk_mmc2, mout_sclk_mmc2,
+ DIV_TOP1_FSYS0, 24, 4),
+
+ DIV
Re: [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
Hi Abhilash,
On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan a.kesa...@samsung.com wrote:
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|3 +
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 247 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..4c69b66 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
same here, the input clocks for top1, fsys0 and fsys1 block need to be
mentioned in this doc.
- reg: physical base address of the controller and the length of
memory mapped region.
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0, mout_aclk_fsys1_200, mout_top1_group1, MUX_SEL_TOP13, 24, 2),
+ MUX(0, mout_aclk_fsys0_200, mout_top1_group1, MUX_SEL_TOP13, 28, 2),
+
+ MUX(0, mout_sclk_mmc2, mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+
+ MUX(0, mout_sclk_mmc1, mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
+ MUX(0, mout_sclk_mmc0, mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+ DIV(DOUT_ACLK_FSYS1_200
Re: [PATCH 2/7] clk: samsung: exynos7: add clocks for MMC block
Hi Vivek,
On Mon, Oct 20, 2014 at 3:19 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
Hi Abhilash,
On Fri, Oct 17, 2014 at 9:41 PM, Abhilash Kesavan a.kesa...@samsung.com
wrote:
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|3 +
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 247 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..4c69b66 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
same here, the input clocks for top1, fsys0 and fsys1 block need to be
mentioned in this doc.
Thanks for the review. I missed adding these, will fix in the next version.
Regards,
Abhilash
- reg: physical base address of the controller and the length of
memory mapped region.
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4,
1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0, mout_aclk_fsys1_200, mout_top1_group1, MUX_SEL_TOP13, 24,
2),
+ MUX(0, mout_aclk_fsys0_200, mout_top1_group1, MUX_SEL_TOP13, 28,
2),
+
+ MUX(0, mout_sclk_mmc2, mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24,
2),
+
+ MUX(0, mout_sclk_mmc1, mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24,
2
[PATCH v2 2/7] clk: samsung: exynos7: add clocks for MMC block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt| 21 ++
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 265 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..b29cb50 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -50,6 +53,13 @@ Input clocks for top0 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for top1 clock controller:
+ - fin_pll
+ - dout_sclk_bus0_pll
+ - dout_sclk_bus1_pll
+ - dout_sclk_cc_pll
+ - dout_sclk_mfc_pll
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
@@ -65,3 +75,14 @@ Input clocks for peric1 clock controller:
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+ - fin_pll
+ - dout_aclk_fsys0_200
+ - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+ - fin_pll
+ - dout_aclk_fsys1_200
+ - dout_sclk_mmc0
+ - dout_sclk_mmc1
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0
[PATCH v3 2/5] clk: samsung: exynos7: add clocks for MMC block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt| 21 ++
drivers/clk/samsung/clk-exynos7.c | 224
include/dt-bindings/clock/exynos7-clk.h| 20 ++
3 files changed, 265 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..b29cb50 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
- samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -50,6 +53,13 @@ Input clocks for top0 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for top1 clock controller:
+ - fin_pll
+ - dout_sclk_bus0_pll
+ - dout_sclk_bus1_pll
+ - dout_sclk_cc_pll
+ - dout_sclk_mfc_pll
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
@@ -65,3 +75,14 @@ Input clocks for peric1 clock controller:
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+ - fin_pll
+ - dout_aclk_fsys0_200
+ - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+ - fin_pll
+ - dout_aclk_fsys1_200
+ - dout_sclk_mmc0
+ - dout_sclk_mmc1
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index c700f65..f5e43fa 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -267,6 +267,132 @@ static void __init exynos7_clk_top0_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top0, samsung,exynos7-clock-top0,
exynos7_clk_top0_init);
+/* Register Offset definitions for CMU_TOP1 (0x105E) */
+#define MUX_SEL_TOP10 0x0200
+#define MUX_SEL_TOP11 0x0204
+#define MUX_SEL_TOP13 0x020C
+#define MUX_SEL_TOP1_FSYS0 0x0224
+#define MUX_SEL_TOP1_FSYS1 0x0228
+#define DIV_TOP13 0x060C
+#define DIV_TOP1_FSYS0 0x0624
+#define DIV_TOP1_FSYS1 0x0628
+#define ENABLE_ACLK_TOP13 0x080C
+#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
+#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)= { fin_pll, dout_sclk_bus0_pll };
+PNAME(mout_top1_bus1_pll_p)= { fin_pll, dout_sclk_bus1_pll_b };
+PNAME(mout_top1_cc_pll_p) = { fin_pll, dout_sclk_cc_pll_b };
+PNAME(mout_top1_mfc_pll_p) = { fin_pll, dout_sclk_mfc_pll_b };
+
+PNAME(mout_top1_half_bus0_pll_p) = {mout_top1_bus0_pll,
+ ffac_top1_bus0_pll_div2};
+PNAME(mout_top1_half_bus1_pll_p) = {mout_top1_bus1_pll,
+ ffac_top1_bus1_pll_div2};
+PNAME(mout_top1_half_cc_pll_p) = {mout_top1_cc_pll,
+ ffac_top1_cc_pll_div2};
+PNAME(mout_top1_half_mfc_pll_p) = {mout_top1_mfc_pll,
+ ffac_top1_mfc_pll_div2};
+
+PNAME(mout_top1_group1) = {mout_top1_half_bus0_pll,
+ mout_top1_half_bus1_pll, mout_top1_half_cc_pll,
+ mout_top1_half_mfc_pll};
+
+static unsigned long top1_clk_regs[] __initdata = {
+ MUX_SEL_TOP10,
+ MUX_SEL_TOP11,
+ MUX_SEL_TOP13,
+ MUX_SEL_TOP1_FSYS0,
+ MUX_SEL_TOP1_FSYS1,
+ DIV_TOP13,
+ DIV_TOP1_FSYS0,
+ DIV_TOP1_FSYS1,
+ ENABLE_ACLK_TOP13,
+ ENABLE_SCLK_TOP1_FSYS0,
+ ENABLE_SCLK_TOP1_FSYS1,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+ MUX(0, mout_top1_mfc_pll, mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+ MUX(0, mout_top1_cc_pll, mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+ MUX(0, mout_top1_bus1_pll, mout_top1_bus1_pll_p,
+ MUX_SEL_TOP10, 12, 1),
+ MUX(0, mout_top1_bus0_pll, mout_top1_bus0_pll_p,
+ MUX_SEL_TOP10, 16, 1),
+
+ MUX(0, mout_top1_half_mfc_pll, mout_top1_half_mfc_pll_p,
+ MUX_SEL_TOP11, 4, 1),
+ MUX(0, mout_top1_half_cc_pll, mout_top1_half_cc_pll_p,
+ MUX_SEL_TOP11, 8, 1),
+ MUX(0, mout_top1_half_bus1_pll, mout_top1_half_bus1_pll_p,
+ MUX_SEL_TOP11, 12, 1),
+ MUX(0, mout_top1_half_bus0_pll, mout_top1_half_bus0_pll_p,
+ MUX_SEL_TOP11, 16, 1),
+
+ MUX(0
Re: [PATCH v2 5/7] arm64: dts: Add initial device tree support for EXYNOS7
On 9 September 2014 08:58, kg...@kernel.org wrote:
Naveen Krishna Chatradhi wrote:
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 31 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 168
+++
3 files changed, 200 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
[...]
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..e593af55
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,168 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #address-cells = 1; ?
Hmm...I can't see any 64-bit address here.
All the SoC peripherals have been put into the soc node and ranges
property in that node is used to convert 64-bit to 32-bit addresses.
But since this is a 64-bit SoC, we use #address-cells as 2.
+ #size-cells = 2;
+
[...]
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
Maybe this is not required? There is no check chipid in arm/arm64.
This is only describing the hardware and it does not depend on linux
using this information. And support for chip id can be used later for
64-bit Exynos platforms as well.
[...]
+ timer {
+ compatible = arm,armv8-timer;
+ interrupts = 1 13 0xff01,
+ 1 14 0xff01,
+ 1 11 0xff01,
+ 1 10 0xff01;
clock-frequency ?
That is programmed by the bootloader / firmware.
[...]
- Kukjin
Thanks,
--
Shine bright,
(: Nav :)
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 14 ++
include/dt-bindings/clock/exynos7-clk.h |9 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_PWM, pclk_pwm, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, sclk_uart0_user, mout_sclk_uart0_user,
ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, sclk_pwm, fin_pll, ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
samsung,exynos7-clock-peric1,
/* Register Offset definitions for CMU_PERIS (0x1004) */
#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { fin_pll,
dout_aclk_peris_66 };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ GATE(PCLK_WDT, pclk_wdt, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, pclk_tmu_apbif, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
GATE(PCLK_CHIPID, pclk_chipid, mout_aclk_peris_66_user,
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, sclk_chipid, fin_pll,
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, sclk_tmu, fin_pll, ENABLE_SCLK_PERIS, 10, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 3227679..28c8aa7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
#define PCLK_HSI2C97
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
-#define PERIC0_NR_CLK 10
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PERIC0_NR_CLK 12
/* PERIC1 */
#define PCLK_UART1 1
@@ -72,7 +74,10 @@
/* PERIS */
#define PCLK_CHIPID1
#define SCLK_CHIPID2
-#define PERIS_NR_CLK 3
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 14 ++
include/dt-bindings/clock/exynos7-clk.h |9 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_PWM, pclk_pwm, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, sclk_uart0_user, mout_sclk_uart0_user,
ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, sclk_pwm, fin_pll, ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
samsung,exynos7-clock-peric1,
/* Register Offset definitions for CMU_PERIS (0x1004) */
#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { fin_pll,
dout_aclk_peris_66 };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ GATE(PCLK_WDT, pclk_wdt, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, pclk_tmu_apbif, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
GATE(PCLK_CHIPID, pclk_chipid, mout_aclk_peris_66_user,
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, sclk_chipid, fin_pll,
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, sclk_tmu, fin_pll, ENABLE_SCLK_PERIS, 10, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 3227679..28c8aa7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
#define PCLK_HSI2C97
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
-#define PERIC0_NR_CLK 10
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PERIC0_NR_CLK 12
/* PERIC1 */
#define PCLK_UART1 1
@@ -72,7 +74,10 @@
/* PERIS */
#define PCLK_CHIPID1
#define SCLK_CHIPID2
-#define PERIS_NR_CLK 3
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 4/5] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 14 ++
include/dt-bindings/clock/exynos7-clk.h |9 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 3a30f43..17e5cf4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[]
__initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_PWM, pclk_pwm, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, sclk_uart0_user, mout_sclk_uart0_user,
ENABLE_SCLK_PERIC0, 16, 0, 0),
+ GATE(SCLK_PWM, sclk_pwm, fin_pll, ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static struct samsung_cmu_info peric0_cmu_info __initdata = {
@@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
samsung,exynos7-clock-peric1,
/* Register Offset definitions for CMU_PERIS (0x1004) */
#define MUX_SEL_PERIS 0x0200
+#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID0x0910
+#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
@@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { fin_pll,
dout_aclk_peris_66 };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
+ ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
+ ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
@@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+ GATE(PCLK_WDT, pclk_wdt, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 6, 0, 0),
+ GATE(PCLK_TMU, pclk_tmu_apbif, mout_aclk_peris_66_user,
+ ENABLE_PCLK_PERIS, 10, 0, 0),
+
GATE(PCLK_CHIPID, pclk_chipid, mout_aclk_peris_66_user,
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, sclk_chipid, fin_pll,
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+ GATE(SCLK_TMU, sclk_tmu, fin_pll, ENABLE_SCLK_PERIS, 10, 0, 0),
};
static struct samsung_cmu_info peris_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index dd89aa0..f255bb7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -53,7 +53,9 @@
#define PCLK_HSI2C97
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
-#define PERIC0_NR_CLK 10
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PERIC0_NR_CLK 12
/* PERIC1 */
#define PCLK_UART1 1
@@ -72,7 +74,10 @@
/* PERIS */
#define PCLK_CHIPID1
#define SCLK_CHIPID2
-#define PERIS_NR_CLK 3
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] arm64: dts: Add pinctrl support for audio IPs on exynos7
Add pinctrl support for I2S,PCM,SPDIF
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 56 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi |7 +++
2 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index c367f0a..a5aeb07 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -333,6 +333,29 @@
samsung,pin-pud = 3;
samsung,pin-drv = 0;
};
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = gpd4-0, gpd4-1, gpd4-2,
+ gpd4-3, gpd4-4;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = gpd4-0, gpd4-2,
+ gpd4-3, gpd4-4;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ spdif_bus: spdif-bus {
+ samsung,pins = gpd4-3, gpd4-4;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
};
pinctrl_bus1 {
@@ -668,3 +691,36 @@
samsung,pin-drv = 2;
};
};
+
+pinctrl_aud {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = gpz0-0, gpz0-1, gpz0-2, gpz0-3,
+ gpz0-4;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = gpz1-0, gpz1-1, gpz1-2, gpz1-3;
+ samsung,pin-function = 5;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index e633b02..eeaa9b8d 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -27,6 +27,7 @@
pinctrl6 = pinctrl_fsys0;
pinctrl7 = pinctrl_fsys1;
pinctrl8 = pinctrl_bus1;
+ pinctrl9 = pinctrl_aud;
};
cpus {
@@ -285,6 +286,12 @@
interrupts = 0 203 0;
};
+ pinctrl_aud: pinctrl@114b {
+ compatible = samsung,exynos7-pinctrl;
+ reg = 0x114b 0x1000;
+ interrupts = 0 92 0;
+ };
+
hsi2c_0: hsi2c@1364 {
compatible = samsung,exynos7-hsi2c;
reg = 0x1364 0x1000;
--
1.7.4.4
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] arm64: dts: Add BUS1 instance pinctrl support
This adds BUS1 instance pinctrl for exynos7 soc.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 111 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi |7 ++
2 files changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 2eef4a2..96be6e3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -586,3 +586,114 @@
samsung,pin-drv = 2;
};
};
+
+pinctrl_bus1 {
+ etc1: etc1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf5: gpf5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ spi5_bus: spi5-bus {
+ samsung,pins = gpf2-0, gpf2-1, gpf2-2, gpf2-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ ufs_refclk_out: ufs-refclk-out {
+ samsung,pins = gpg2-4;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 2;
+ };
+
+ ufs_rst_n: ufs-rst-n {
+ samsung,pins = gph1-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..f9c5a54 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -26,6 +26,7 @@
pinctrl5 = pinctrl_ese;
pinctrl6 = pinctrl_fsys0;
pinctrl7 = pinctrl_fsys1;
+ pinctrl8 = pinctrl_bus1;
};
cpus {
@@ -278,6 +279,12 @@
interrupts = 0 203 0;
};
+ pinctrl_bus1: pinctrl@1487 {
+ compatible = samsung,exynos7-pinctrl;
+ reg = 0x1487 0x1000;
+ interrupts = 0 384 0;
+ };
+
hsi2c_0: hsi2c@1364 {
compatible = samsung,exynos7-hsi2c;
reg = 0x1364 0x1000;
--
1.7.10.4
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] arm64: dts: Add BUS1 instance pinctrl support
This adds BUS1 instance pinctrl for exynos7 soc.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
Changes since v1:
- Removed etc1 gpio as per Krzysztof review comments.
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 103 +++
arch/arm64/boot/dts/exynos/exynos7.dtsi |7 ++
2 files changed, 110 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 2eef4a2..f77ddaf 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -586,3 +586,106 @@
samsung,pin-drv = <2>;
};
};
+
+_bus1 {
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf5: gpf5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph1: gph1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpv6: gpv6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ spi5_bus: spi5-bus {
+ samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ ufs_refclk_out: ufs-refclk-out {
+ samsung,pins = "gpg2-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <2>;
+ };
+
+ ufs_rst_n: ufs-rst-n {
+ samsung,pins = "gph1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..f9c5a54 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -26,6 +26,7 @@
pinctrl5 = _ese;
pinctrl6 = _fsys0;
pinctrl7 = _fsys1;
+ pinctrl8 = _bus1;
};
cpus {
@@ -278,6 +279,12 @@
interrupts = <0 203 0>;
};
+ pinctrl_bus1: pinctrl@1487 {
+ compatible = "samsung,exynos7-pinctrl";
+ reg = <0x1487 0x1000>;
+ interrupts = <0 384 0>;
+ };
+
hsi2c_0: hsi2c@1364 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x1364 0x1000>;
--
1.7.10.4
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/7] arm64: dts: Add initial device tree support for EXYNOS7
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 31 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 168 +++
3 files changed, 200 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..a3bc18a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos/exynos7-espresso.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..f6a8879
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,31 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..e593af55
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,168 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial_0;
+ serial1 = serial_1;
+ serial2 = serial_2;
+ serial3 = serial_3;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000
[PATCH v3 5/8] arm64: dts: Add initial device tree support for EXYNOS7
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 35 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 167 +++
3 files changed, 203 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..a3bc18a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos/exynos7-espresso.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..4f69991
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,35 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..56ec5f4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,167 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial_0;
+ serial1 = serial_1;
+ serial2 = serial_2;
+ serial3 = serial_3;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000
[PATCH v4 5/8] arm64: dts: Add initial device tree support for EXYNOS7
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/Makefile |5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 ++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 160 +++
4 files changed, 205 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 309c3dc..b13bf21 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dts-dirs += apm
dts-dirs += arm
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..c5b1b86
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,160 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000
RE: [PATCH v4 5/8] arm64: dts: Add initial device tree support for EXYNOS7
Naveen Krishna Chatradhi wrote:
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
Looks good to me,
Acked-by: Kukjin Kim kgene@samsung.com
Thanks,
Kukjin
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/Makefile |5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 ++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 160
+++
4 files changed, 205 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 309c3dc..b13bf21 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dts-dirs += apm
dts-dirs += arm
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-
espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..c5b1b86
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,160 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock
[PATCH v5 5/8] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Thomas Abraham thomas...@samsung.com
Tested-by: Thomas Abraham thomas...@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/exynos/Makefile | 5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 309c3dc..b13bf21 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dts-dirs += apm
dts-dirs += arm
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..a326fbf
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti
[PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
Adding required support for clocks and additional VBUS regulators to enable USB 3.0 support on Exynos7 SoC. This series depends for ACRH_EXYNOS7 support on following series: [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg37047.html The series is based on usb-next branch. Changes since v1: -- Addressed review comments for unnecessary warning messages after clk_get() fails for dwc3-exynos and phy-exynos5-usbdrd. -- Assigned exynos-sclk as well as phy_drd-utmiclk and phy_drd-pipeclk to NULL in case of clk_get() failure to avoid unnecessary check for clock. -- Modified dependency for symbol PHY_EXYNOS5_USBDRD to depend on ARCH_EXYNOS which includes both Exynos5 as well as Exynos7. -- Dropped [PATCH 4/5] usb: dwc3: Adding Kconfig dependency for Exynos7 from v1 of this series, since its not required now. Vivek Gautam (4): dwc3: exynos: Add support for SCLK present on Exynos7 phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS .../devicetree/bindings/phy/samsung-phy.txt|4 ++ drivers/phy/Kconfig|2 +- drivers/phy/phy-exynos5-usbdrd.c | 52 +++- drivers/usb/dwc3/dwc3-exynos.c | 16 ++ 4 files changed, 71 insertions(+), 3 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 2/7] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Thomas Abraham thomas...@samsung.com
Tested-by: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/Makefile |5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183 +++
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8f..fdda246 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,6 +1,7 @@
dts-dirs += apm
dts-dirs += arm
dts-dirs += cavium
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..c4cabc6
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti
[PATCH v7 2/7] arm64: dts: Add initial device tree support for EXYNOS7
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Reviewed-by: Thomas Abraham thomas...@samsung.com
Tested-by: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/exynos/Makefile | 5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 183
4 files changed, 228 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8f..fdda246 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,6 +1,7 @@
dts-dirs += apm
dts-dirs += arm
dts-dirs += cavium
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..6d6a4c2
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,183 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x0;
+ enable-method = psci;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x1;
+ enable-method = psci;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x2;
+ enable-method = psci;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x3;
+ enable-method = psci;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti
[PATCH 11/11] arm64: dts: exynos7-espresso: Add regulators for Vbus and Vbus-Boost
Adding fixed voltage regulators for Vbus and Vbus-boost required
by USB 3.0 DRD controller on Exynos7-espresso board.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 43 +++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 5424cc4..2dedd5e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -30,6 +30,28 @@
device_type = memory;
reg = 0x0 0x4000 0x0 0xC000;
};
+
+ usb30_vbus_reg: regulator-usb30 {
+ compatible = regulator-fixed;
+ regulator-name = VBUS_5V;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ gpio = gph1 1 0;
+ pinctrl-names = default;
+ pinctrl-0 = usb30_vbus_en;
+ enable-active-high;
+ };
+
+ usb3drd_vboost_5v: regulator-usb3drd-vboost {
+ compatible = regulator-fixed;
+ regulator-name = VUSB_VBUS_5V;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ gpio = gpf4 1 0;
+ pinctrl-names = default;
+ pinctrl-0 = usb3drd_vboost_en;
+ enable-active-high;
+ };
};
fin_pll {
@@ -40,6 +62,22 @@
status = okay;
};
+pinctrl_bus1 {
+ usb30_vbus_en: usb30-vbus-en {
+ samsung,pins = gph1-1;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ usb3drd_vboost_en: usb3drd-vboost-en {
+ samsung,pins = gpf4-1;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+};
+
rtc {
status = okay;
};
@@ -82,3 +120,8 @@
bus-width = 4;
disable-wp;
};
+
+usbdrd_phy {
+ vbus-supply = usb30_vbus_reg;
+ vbus-boost-supply = usb3drd_vboost_5v;
+};
--
1.7.10.4
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 4/4] Samsung exynos7 updates for v3.19
Arnd Bergmann wrote: On Thursday 27 November 2014, Kukjin Kim wrote: Samsung arch/arm64 DT updates for v3.19 - to support ARMv8 based exynos7 SoC : add initial device tree and add pinctrl, PMU, mmc, i2c, rtc, watchdog, and adc nodes for exynos7 SoC and exynos7 based espresso board. NOTE that this is including following dependencies : cleanup/dts-subdirs in arm-soc for arm64 vendor support : tags/samsung-driver for samsung serial : for-v3.19/exynos-clk in samsung-clk tree for exynos7 clk One more NOTE, for support exynos7 we need Liviu's arm64: Create link to include/dt-bindings to enable C preprocessor use in arm-soc tree and arm64 defconfig update should be handled directly. I'm confused by the dependencies. I don't see a for-v3.19/exynos-clk in arm-soc, you haven't put the clk maintainer on Cc and I see no indication that he has this in his tree already, so I'm not pulling this until further clarification. Hi, Sorry for insufficient description. Since the exynos7 stuff requires regarding clk stuff for kernel build, I talked to Mike, Sylwester and Mike suggested pulling the branch into Samsung tree. http://www.spinics.net/lists/linux-samsung-soc/msg39368.html If any problems, please let me know. Thanks, Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 4/4] Samsung exynos7 updates for v3.19
Kukjin Kim wrote: Arnd Bergmann wrote: On Thursday 27 November 2014, Kukjin Kim wrote: Samsung arch/arm64 DT updates for v3.19 - to support ARMv8 based exynos7 SoC : add initial device tree and add pinctrl, PMU, mmc, i2c, rtc, watchdog, and adc nodes for exynos7 SoC and exynos7 based espresso board. NOTE that this is including following dependencies : cleanup/dts-subdirs in arm-soc for arm64 vendor support : tags/samsung-driver for samsung serial : for-v3.19/exynos-clk in samsung-clk tree for exynos7 clk One more NOTE, for support exynos7 we need Liviu's arm64: Create link to include/dt-bindings to enable C preprocessor use in arm-soc tree and arm64 defconfig update should be handled directly. I'm confused by the dependencies. I don't see a for-v3.19/exynos-clk in arm-soc, you haven't put the clk maintainer on Cc and I see no indication that he has this in his tree already, so I'm not pulling this until further clarification. Hi, Sorry for insufficient description. Since the exynos7 stuff requires regarding clk stuff for kernel build, I talked to Mike, Sylwester and Mike suggested pulling the branch into Samsung tree. http://www.spinics.net/lists/linux-samsung-soc/msg39368.html If any problems, please let me know. Hi Arnd, Do you have any concerns on this? - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] arm64: dts: exynos7: Enable HS200 mode operation
This patch enables HS200 mode operation on exynos7 based
espresso board.
This also removes _broken-cd_ property as per mmc binding documentation
which says one of the properties between broken-cd and non-removable
should be used. And we already use _non-removable_ as emmc mounted
on board which is a non-removable device.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
Reviewed-by: Javier Martinez Canillas <jav...@osg.samsung.com>
---
Changes since v1:
* Addressed Krzysztof review comments
arch/arm64/boot/dts/exynos/exynos7-espresso.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index f5a3da50ac57..d8767b00862e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -333,8 +333,8 @@
_0 {
status = "okay";
num-slots = <1>;
- broken-cd;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
non-removable;
card-detect-delay = <200>;
clock-frequency = <8>;
--
1.7.10.4
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] arm64: dts: exynos7: Enable HS200 mode operation
This patch enables HS200 mode operation on exynos7 based
espresso board.
This also remove _broken-cd_ property as per mmc binding documentation
which say one of the properties between broken-cd and non-removable
should be used. And we already use _non-removable_ as emmc mounted
on board which is a non-removable device.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 8ce04a0ec928..7f19b99fc85b 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -405,8 +405,8 @@
_0 {
status = "okay";
num-slots = <1>;
- broken-cd;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
non-removable;
card-detect-delay = <200>;
clock-frequency = <8>;
--
1.7.10.4
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] arm64: dts: exynos7: Enable HS200 mode operation
Hello Alim,
On 11/02/2015 11:04 AM, Alim Akhtar wrote:
> This patch enables HS200 mode operation on exynos7 based
> espresso board.
> This also remove _broken-cd_ property as per mmc binding documentation
> which say one of the properties between broken-cd and non-removable
> should be used. And we already use _non-removable_ as emmc mounted
> on board which is a non-removable device.
>
> Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos7-espresso.dts |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> index 8ce04a0ec928..7f19b99fc85b 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> @@ -405,8 +405,8 @@
> _0 {
> status = "okay";
> num-slots = <1>;
> - broken-cd;
> cap-mmc-highspeed;
> + mmc-hs200-1_8v;
> non-removable;
> card-detect-delay = <200>;
> clock-frequency = <8>;
>
Reviewed-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] arm64: dts: exynos7: Enable HS200 mode operation
This patch enables HS200 mode operation on exynos7 based
espresso board.
This also removes _broken-cd_ property as per mmc binding documentation
which says one of the properties between broken-cd and non-removable
should be used. And we already use _non-removable_ as emmc mounted
on board which is a non-removable device.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
Reviewed-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
Chnages since v2:
* none
Changes since v1:
* Addressed Krzysztof review comments
arch/arm64/boot/dts/exynos/exynos7-espresso.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index f5a3da50ac57..d8767b00862e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -333,8 +333,8 @@
_0 {
status = "okay";
num-slots = <1>;
- broken-cd;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
non-removable;
card-detect-delay = <200>;
clock-frequency = <8>;
--
1.7.10.4
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 08/12] clk: samsung: exynos7: Corrects CMU_PERIS clocks names
This patch renames CMU_PERIS clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
drivers/clk/samsung/clk-exynos7.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 7796712..ae6836e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -791,7 +791,7 @@ CLK_OF_DECLARE(exynos7_clk_peric1,
"samsung,exynos7-clock-peric1",
#define ENABLE_SCLK_PERIS_SECURE_CHIPID0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
-PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
+PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
static unsigned long peris_clk_regs[] __initdata = {
MUX_SEL_PERIS,
@@ -803,7 +803,7 @@ static unsigned long peris_clk_regs[] __initdata = {
static struct samsung_mux_clock peris_mux_clks[] __initdata = {
MUX(0, "mout_aclk_peris_66_user",
- mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
+ mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
};
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
--
1.7.10.4
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] clk/samsung updates for v4.4
On 10/02, Sylwester Nawrocki wrote:
>
> The following changes since commit 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f:
>
> Linux 4.3-rc1 (2015-09-12 16:35:56 -0700)
>
> are available in the git repository at:
>
> git://linuxtv.org/snawrocki/samsung.git tags/clk-samsung-4.4
>
> for you to fetch changes up to 7993b3ebec979b23c2d7425959c9d232c452498b:
>
> clk: samsung: exynos7: Add required clock tree for UFS (2015-09-15 11:18:15
> +0200)
>
Thanks, pulled. I put this patch on top though.
-8<-
From: Stephen Boyd <sb...@codeaurora.org>
Subject: [PATCH] clk: samsung: exynos7: Staticize file scope symbols
drivers/clk/samsung/clk-exynos7.c:896:33:
warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should
it be static?
drivers/clk/samsung/clk-exynos7.c:1010:33:
warning: symbol 'fixed_rate_clks_fsys1' was not declared. Should
it be static?
Cc: Sylwester Nawrocki <s.nawro...@samsung.com>
Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
---
drivers/clk/samsung/clk-exynos7.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 924215b219da..55f8e2e24ab8 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -893,7 +893,7 @@ PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p)
= { "fin_pll",
"phyclk_usbdrd300_udrd30_pipe_pclk" };
/* fixed rate clocks used in the FSYS0 block */
-struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
+static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
CLK_IS_ROOT, 6000),
FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
@@ -1007,7 +1007,7 @@ PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll",
"phyclk_ufs20_rx0_symbol" };
PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
/* fixed rate clocks used in the FSYS1 block */
-struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
+static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
CLK_IS_ROOT, 3),
FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/14] Support 64bit Cortex A57 based Exynos7 SoC
Hi Naveen, On 27.08.2014 11:44, Naveen Krishna Chatradhi wrote: This patchset supports new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. A general issue with this series is that it introduces a very generic name for a very specific single SoC. We remember exactly the same cases for Exynos4 (original name used for Exynos5250) and Exynos5 (Exynos5250) and we should have learned that it is better to use a specific name first and only then try to make things common if it turns out to be appropriate. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5] phy: exynos5-usbdrd: Adding Kconfig dependency for Exynos7
2014-08-28 10:02 GMT+02:00 Vivek Gautam: This USB 3.0 PHY controller is also present on Exynos7 platform, so adding the dependency on ARCH_EXYNOS7 for this driver. +++ b/drivers/phy/Kconfig @@ -186,7 +186,7 @@ config PHY_EXYNOS5250_USB2 config PHY_EXYNOS5_USBDRD tristate Exynos5 SoC series USB DRD PHY driver - depends on ARCH_EXYNOS5 OF + depends on (ARCH_EXYNOS5 || ARCH_EXYNOS7) OF shouldn't that prompt and its help text be updated to mention also Exynos7? -- Daniele Forsi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 5/8] arm64: dts: Add initial device tree support for EXYNOS7
On Thursday 11 September 2014 15:50:49 Naveen Krishna Chatradhi wrote:
+ aliases {
+ serial0 = serial_0;
+ serial1 = serial_1;
+ serial2 = serial_2;
+ serial3 = serial_3;
+ };
+
Please move the aliases from the exynos7.dtsi file into the
exynos7-espresso.dts file, and only list the ones that are
present, starting with alias 0, like
aliases {
serial0 = serial_2;
};
If the machine has only one serial port, it should be the first
alias.
Arnd
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 5/8] arm64: dts: Add initial device tree support for EXYNOS7
On 11 September 2014 16:11, Arnd Bergmann a...@arndb.de wrote:
On Thursday 11 September 2014 15:50:49 Naveen Krishna Chatradhi wrote:
+ aliases {
+ serial0 = serial_0;
+ serial1 = serial_1;
+ serial2 = serial_2;
+ serial3 = serial_3;
+ };
+
Please move the aliases from the exynos7.dtsi file into the
exynos7-espresso.dts file, and only list the ones that are
present, starting with alias 0, like
aliases {
serial0 = serial_2;
};
If the machine has only one serial port, it should be the first
alias.
Okay, will fix this in the next version.
Arnd
Thanks,
--
Shine bright,
(: Nav :)
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/8] clk: samsung: add initial clock support for Exynos7 SoC
Hi Naveen,
Please see my comments inline.
On 12.09.2014 17:26, Naveen Krishna Chatradhi wrote:
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
[snip]
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - fin_pll - PLL input clock from XXTI
In addition to just relying on clock names (which I hope to finally go
away from common clock framework some day) the binding should be defined
to take all input clocks using generic clock bindings (i.e. clocks and
clock-names). Even if the driver wouldn't use that yet, this would help
with determining initialization order of clock providers.
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+ compatible strings to indicate the clock controller
+ functionality.
+
+ - samsung,exynos7-clock-topc
+ - samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-peric0
+ - samsung,exynos7-clock-peric1
+ - samsung,exynos7-clock-peris
+
+ - reg: physical base address of the controller and the length of
+ memory mapped region.
+
+ - #clock-cells: should be 1.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..5da0ba9 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
+obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
Please keep the entries sorted alphabetically.
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644
index 000..3ea8d0e
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7.c
[snip]
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata
= {
+ FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus0_pll_div4,
+ ffac_topc_bus0_pll_div2, 1, 2, 0),
Please use a consistent way of breaking long lines. Here you have 3
tabs, but further in the driver I can see 1 tab or 2 tabs. I'd recommend
making them all 1 tab.
+ FFACTOR(0, ffac_topc_bus1_pll_div2, mout_bus1_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_cc_pll_div2, mout_cc_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_mfc_pll_div2, mout_mfc_pll_ctrl, 1, 2, 0),
+};
[snip]
+static void __init exynos7_clk_topc_init(struct device_node *np)
+{
+ struct exynos_cmu_info cmu = {0};
+
+ cmu.pll_clks = topc_pll_clks;
+ cmu.nr_pll_clks = ARRAY_SIZE(topc_pll_clks);
+ cmu.mux_clks = topc_mux_clks;
+ cmu.nr_mux_clks = ARRAY_SIZE(topc_mux_clks);
+ cmu.div_clks = topc_div_clks;
+ cmu.nr_div_clks = ARRAY_SIZE(topc_div_clks);
+ cmu.fixed_factor_clks = topc_fixed_factor_clks;
+ cmu.nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks);
+ cmu.clk_regs = topc_clk_regs;
+ cmu.nr_clk_regs = ARRAY_SIZE(topc_clk_regs);
I wonder if you couldn't simply make this struct statically initialized
and marked as __initdata.
Otherwise looks good.
Best regards,
Tomasz
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 6/8] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
On Fri, Sep 12, 2014 at 04:26:30PM +0100, Naveen Krishna Chatradhi wrote: From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 12 Please update the defconfig as well as we want the default image build to contain all the available platforms. -- Catalin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/8] clk: samsung: add initial clock support for Exynos7 SoC
Hi Tomasz,
On Sat, Sep 13, 2014 at 4:47 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Naveen,
Please see my comments inline.
On 12.09.2014 17:26, Naveen Krishna Chatradhi wrote:
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
[snip]
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - fin_pll - PLL input clock from XXTI
In addition to just relying on clock names (which I hope to finally go
away from common clock framework some day) the binding should be defined
to take all input clocks using generic clock bindings (i.e. clocks and
clock-names). Even if the driver wouldn't use that yet, this would help
with determining initialization order of clock providers.
OK, will fix.
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+ compatible strings to indicate the clock controller
+ functionality.
+
+ - samsung,exynos7-clock-topc
+ - samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-peric0
+ - samsung,exynos7-clock-peric1
+ - samsung,exynos7-clock-peris
+
+ - reg: physical base address of the controller and the length of
+ memory mapped region.
+
+ - #clock-cells: should be 1.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..5da0ba9 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
+obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
Please keep the entries sorted alphabetically.
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644
index 000..3ea8d0e
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7.c
[snip]
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[]
__initdata = {
+ FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus0_pll_div4,
+ ffac_topc_bus0_pll_div2, 1, 2, 0),
Please use a consistent way of breaking long lines. Here you have 3
tabs, but further in the driver I can see 1 tab or 2 tabs. I'd recommend
making them all 1 tab.
Will use 1 tab across the file.
+ FFACTOR(0, ffac_topc_bus1_pll_div2, mout_bus1_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_cc_pll_div2, mout_cc_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_mfc_pll_div2, mout_mfc_pll_ctrl, 1, 2, 0),
+};
[snip]
+static void __init exynos7_clk_topc_init(struct device_node *np)
+{
+ struct exynos_cmu_info cmu = {0};
+
+ cmu.pll_clks = topc_pll_clks;
+ cmu.nr_pll_clks = ARRAY_SIZE(topc_pll_clks);
+ cmu.mux_clks = topc_mux_clks;
+ cmu.nr_mux_clks = ARRAY_SIZE(topc_mux_clks);
+ cmu.div_clks = topc_div_clks;
+ cmu.nr_div_clks = ARRAY_SIZE(topc_div_clks);
+ cmu.fixed_factor_clks = topc_fixed_factor_clks;
+ cmu.nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks);
+ cmu.clk_regs = topc_clk_regs;
+ cmu.nr_clk_regs = ARRAY_SIZE(topc_clk_regs);
I wonder if you couldn't simply make this struct statically initialized
and marked as __initdata.
Will change.
Otherwise looks good.
Best regards,
Tomasz
___
linux-arm-kernel mailing list
linux-arm-ker...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] i2c: exynos: add support for HSI2C module on Exynos7
On Tue, Sep 16, 2014 at 03:03:17PM +0530, Naveen Krishna Chatradhi wrote: The HSI2C module on Exynos7 differs in the transfer status bits. Transfer status bits were moved to INT_ENABLE and INT_STATUS registers This patch adds support for the HSI2C module on Exynos7. 1. Implementes a hw field in the variant struct to distinguish the hardware. 2. Updates the dt-new compatible in dt-binding documenation Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Wolfram Sang w...@the-dreams.de Applied to for-next, thanks! signature.asc Description: Digital signature
[PATCH 1/7] clk: samsung: exynos7: add clocks for I2C block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 24
include/dt-bindings/clock/exynos7-clk.h | 16 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C0, pclk_hsi2c0, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, pclk_hsi2c1, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, pclk_hsi2c4, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, pclk_hsi2c5, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, pclk_hsi2c9, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, pclk_hsi2c10, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, pclk_hsi2c11, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C2, pclk_hsi2c2, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, pclk_hsi2c3, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, pclk_hsi2c6, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, pclk_hsi2c7, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, pclk_hsi2c8, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, pclk_uart1, mout_aclk_peric1_66_user,
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, pclk_uart2, mout_aclk_peric1_66_user,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C03
+#define PCLK_HSI2C14
+#define PCLK_HSI2C45
+#define PCLK_HSI2C56
+#define PCLK_HSI2C97
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C27
+#define PCLK_HSI2C38
+#define PCLK_HSI2C69
+#define PCLK_HSI2C710
+#define PCLK_HSI2C811
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID1
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/7] arm64: exynos: Enable rtc and watchdog support for Exynos7
Enable rtc and watchdog support for exynos7 SoCs. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- arch/arm64/Kconfig |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 238acff..9bb4e02 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -158,6 +158,9 @@ config ARCH_EXYNOS7 select COMMON_CLK_SAMSUNG select PINCTRL select PINCTRL_EXYNOS + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/7] clk: samsung: exynos7: add clocks for I2C block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 24
include/dt-bindings/clock/exynos7-clk.h | 16 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C0, pclk_hsi2c0, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, pclk_hsi2c1, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, pclk_hsi2c4, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, pclk_hsi2c5, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, pclk_hsi2c9, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, pclk_hsi2c10, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, pclk_hsi2c11, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C2, pclk_hsi2c2, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, pclk_hsi2c3, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, pclk_hsi2c6, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, pclk_hsi2c7, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, pclk_hsi2c8, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, pclk_uart1, mout_aclk_peric1_66_user,
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, pclk_uart2, mout_aclk_peric1_66_user,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C03
+#define PCLK_HSI2C14
+#define PCLK_HSI2C45
+#define PCLK_HSI2C56
+#define PCLK_HSI2C97
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C27
+#define PCLK_HSI2C38
+#define PCLK_HSI2C69
+#define PCLK_HSI2C710
+#define PCLK_HSI2C811
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID1
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 7/7] arm64: exynos: Enable rtc and watchdog support for Exynos7
Enable rtc and watchdog support for exynos7 SoCs. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com --- arch/arm64/Kconfig |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 238acff..9bb4e02 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -158,6 +158,9 @@ config ARCH_EXYNOS7 select COMMON_CLK_SAMSUNG select PINCTRL select PINCTRL_EXYNOS + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/5] clk: samsung: exynos7: add clocks for I2C block
From: Naveen Krishna Ch naveenkrishna...@gmail.com
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos7.c | 24
include/dt-bindings/clock/exynos7-clk.h | 16 ++--
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 54206d4..c700f65 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C0, pclk_hsi2c0, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 8, 0, 0),
+ GATE(PCLK_HSI2C1, pclk_hsi2c1, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 9, 0, 0),
+ GATE(PCLK_HSI2C4, pclk_hsi2c4, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 10, 0, 0),
+ GATE(PCLK_HSI2C5, pclk_hsi2c5, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 11, 0, 0),
+ GATE(PCLK_HSI2C9, pclk_hsi2c9, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 12, 0, 0),
+ GATE(PCLK_HSI2C10, pclk_hsi2c10, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 13, 0, 0),
+ GATE(PCLK_HSI2C11, pclk_hsi2c11, mout_aclk_peric0_66_user,
+ ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, pclk_uart0, mout_aclk_peric0_66_user,
ENABLE_PCLK_PERIC0, 16, 0, 0),
@@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[]
__initdata = {
};
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+ GATE(PCLK_HSI2C2, pclk_hsi2c2, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 4, 0, 0),
+ GATE(PCLK_HSI2C3, pclk_hsi2c3, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 5, 0, 0),
+ GATE(PCLK_HSI2C6, pclk_hsi2c6, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 6, 0, 0),
+ GATE(PCLK_HSI2C7, pclk_hsi2c7, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 7, 0, 0),
+ GATE(PCLK_HSI2C8, pclk_hsi2c8, mout_aclk_peric1_66_user,
+ ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, pclk_uart1, mout_aclk_peric1_66_user,
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, pclk_uart2, mout_aclk_peric1_66_user,
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de..6d07b6f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C03
+#define PCLK_HSI2C14
+#define PCLK_HSI2C45
+#define PCLK_HSI2C56
+#define PCLK_HSI2C97
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C27
+#define PCLK_HSI2C38
+#define PCLK_HSI2C69
+#define PCLK_HSI2C710
+#define PCLK_HSI2C811
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID1
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] arm64: dts: Add PDMA and SPI device tree node for exynos7
Add PDMA0,PDMA1 and 5 SPI dt nodes for Exynos7.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 113 +++
1 files changed, 113 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index eeaa9b8d..db7058a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -28,6 +28,9 @@
pinctrl7 = pinctrl_fsys1;
pinctrl8 = pinctrl_bus1;
pinctrl9 = pinctrl_aud;
+ spi0 = spi_0;
+ spi1 = spi_1;
+ spi2 = spi_2;
};
cpus {
@@ -573,6 +576,116 @@
samsung,pmu-syscon = pmu_system_controller;
#phy-cells = 1;
};
+
+ amba {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = arm,amba-bus;
+ interrupt-parent = gic;
+ ranges;
+
+ pdma1: pdma1@10EB {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x10EB 0x1000;
+ interrupts = 0 226 0;
+ clocks = clock_fsys0 ACLK_PDMA1;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma0: pdma0@10E1 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x10E1 0x1000;
+ interrupts = 0 225 0;
+ clocks = clock_fsys0 ACLK_PDMA0;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+ };
+
+ spi_0: spi@14d2 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d2 0x100;
+ interrupts = 0 464 0;
+ dmas = pdma0 7
+ pdma0 6;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI0, clock_peric1
SCLK_SPI0;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi0_bus;
+ status = disabled;
+ };
+
+ spi_1: spi@14d3 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d3 0x100;
+ interrupts = 0 465 0;
+ dmas = pdma0 9
+ pdma0 8;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI1, clock_peric1
SCLK_SPI1;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi1_bus;
+ status = disabled;
+ };
+
+ spi_2: spi@14d4 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d4 0x100;
+ interrupts = 0 466 0;
+ dmas = pdma0 11
+ pdma0 10;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI2, clock_peric1
SCLK_SPI2;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi2_bus;
+ status = disabled;
+ };
+
+ spi_3: spi@14d5 {
+ compatible = samsung,exynos7-spi;
+ reg = 0x14d5 0x100;
+ interrupts = 0 467 0;
+ dmas = pdma0 13
+ pdma0 12;
+ dma-names = tx, rx;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = clock_peric1 PCLK_SPI3, clock_peric1
SCLK_SPI3;
+ clock-names = spi, spi_busclk0;
+ pinctrl-names = default;
+ pinctrl-0 = spi3_bus;
+ status = disabled;
+ };
+
+ spi_4
Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
Hi, On 19/12/14 14:23, Padmavathi Venna wrote: Add required clk support for I2S,PCM amd SPDIF There is a non-trivial conflict with the MSCL CMU patch, could you please resend rebased onto my exynos7 branch: git://linuxtv.org/snawrocki/samsung.git for-v3.20/clk/exynos7 ? Is exynos7420 documentation applicable to this ? Would be nice to have someone else who has access to the SoC documentation replied with a Reviewed-by tag. -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] thermal: exynos: Fix NULL pointer error and bug of PD_DET_EN of Exynos7
This patch-set fix NULL pointer error during kernel booting and the bug of PD_DET_EN bit field of Exynos7 TMU. And the clean-up the exynos compatible table by making oneline entry. Chanwoo Choi (3): thermal: exynos: Fix NULL pointer exception during kernel booting thermal: exynos: Fix wrong control of power down detection mode for Exynos7 thermal: exynos: Clean-up code to use oneline entry for exynos compatible table drivers/thermal/samsung/exynos_tmu.c | 51 1 file changed, 17 insertions(+), 34 deletions(-) -- 1.8.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl block
On Sun, Mar 1, 2015 at 5:21 PM, Abhilash Kesavan a.kesa...@samsung.com wrote: The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: samsung-pinctrl 1058.pinctrl: irq number not available Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Patch applied with Tomasz ACK. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl block
Hi Abhilash, Linus, 2015-03-02 1:21 GMT+09:00 Abhilash Kesavan a.kesa...@samsung.com: The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: samsung-pinctrl 1058.pinctrl: irq number not available As long as external gpio interrupts refer to non-wake-up-capable GPIO interrupts I'm fine with this patch. Acked-by: Tomasz Figa tomasz.f...@gmail.com Thanks Linus for pinging and sorry for delay. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl block
On Sun, Mar 1, 2015 at 5:21 PM, Abhilash Kesavan a.kesa...@samsung.com wrote: The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: samsung-pinctrl 1058.pinctrl: irq number not available Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Tomasz, can you look at this patch? Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] arm64: dts: Add BUS1 instance pinctrl support
On 28.08.2015 20:25, Alim Akhtar wrote: This adds BUS1 instance pinctrl for exynos7 soc. Signed-off-by: Alim Akhtar alim.akh...@samsung.com --- arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 111 +++ arch/arm64/boot/dts/exynos/exynos7.dtsi |7 ++ 2 files changed, 118 insertions(+) The etc1 GPIO in my datasheet is not fully documented but the rest looks good: Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 06/11] clk: samsung: exynos7: Corrects CMU_PERIC1 clocks names
This patch rename CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
drivers/clk/samsung/clk-exynos7.c | 38 ---
include/dt-bindings/clock/exynos7-clk.h |3 ++-
2 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index 782943b..696489a 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -340,6 +340,8 @@ static struct samsung_div_clock top0_div_clks[] __initdata
= {
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
+ ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
@@ -662,15 +664,15 @@ CLK_OF_DECLARE(exynos7_clk_peric0,
"samsung,exynos7-clock-peric0",
exynos7_clk_peric0_init);
/* List of parent clocks for Muxes in CMU_PERIC1 */
-PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
-PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
-PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
-PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
-PNAME(mout_sclk_spi0_p)= { "fin_pll", "sclk_spi0" };
-PNAME(mout_sclk_spi1_p)= { "fin_pll", "sclk_spi1" };
-PNAME(mout_sclk_spi2_p)= { "fin_pll", "sclk_spi2" };
-PNAME(mout_sclk_spi3_p)= { "fin_pll", "sclk_spi3" };
-PNAME(mout_sclk_spi4_p)= { "fin_pll", "sclk_spi4" };
+PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
+PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
+PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
+PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
+PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
+PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
+PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
static unsigned long peric1_clk_regs[] __initdata = {
MUX_SEL_PERIC10,
@@ -681,24 +683,24 @@ static unsigned long peric1_clk_regs[] __initdata = {
};
static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
- MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
+ MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
MUX_SEL_PERIC10, 0, 1),
- MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
+ MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
+ MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
+ MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
+ MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
+ MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
- MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
+ MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
MUX_SEL_PERIC11, 20, 1),
- MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
+ MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
MUX_SEL_PERIC11, 24, 1),
- MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
+ MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
MUX_SEL_PERIC11, 28, 1),
};
diff --git a/include/dt-bi
[PATCH v2 07/12] clk: samsung: exynos7: Corrects CMU_PERIC1 clocks names
This patch renames CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
drivers/clk/samsung/clk-exynos7.c | 38 ---
include/dt-bindings/clock/exynos7-clk.h |3 ++-
2 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index b819fdd..7796712 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -343,6 +343,8 @@ static struct samsung_div_clock top0_div_clks[] __initdata
= {
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
+ ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
@@ -665,15 +667,15 @@ CLK_OF_DECLARE(exynos7_clk_peric0,
"samsung,exynos7-clock-peric0",
exynos7_clk_peric0_init);
/* List of parent clocks for Muxes in CMU_PERIC1 */
-PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
-PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
-PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
-PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
-PNAME(mout_sclk_spi0_p)= { "fin_pll", "sclk_spi0" };
-PNAME(mout_sclk_spi1_p)= { "fin_pll", "sclk_spi1" };
-PNAME(mout_sclk_spi2_p)= { "fin_pll", "sclk_spi2" };
-PNAME(mout_sclk_spi3_p)= { "fin_pll", "sclk_spi3" };
-PNAME(mout_sclk_spi4_p)= { "fin_pll", "sclk_spi4" };
+PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
+PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
+PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
+PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
+PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
+PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
+PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
static unsigned long peric1_clk_regs[] __initdata = {
MUX_SEL_PERIC10,
@@ -684,24 +686,24 @@ static unsigned long peric1_clk_regs[] __initdata = {
};
static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
- MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
+ MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
MUX_SEL_PERIC10, 0, 1),
- MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
+ MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
+ MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
+ MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
+ MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
- MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
+ MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
- MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
+ MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
MUX_SEL_PERIC11, 20, 1),
- MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
+ MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
MUX_SEL_PERIC11, 24, 1),
- MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
+ MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
Re: [PATCH v2 02/12] clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC
On 10.09.2015 17:44, Alim Akhtar wrote: > This adds some of the missing GATE clocks of CMU_TOPC block. > > Signed-off-by: Alim Akhtar <alim.akh...@samsung.com> > --- > drivers/clk/samsung/clk-exynos7.c | 27 +++ > include/dt-bindings/clock/exynos7-clk.h | 13 - > 2 files changed, 39 insertions(+), 1 deletion(-) Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/11] clk: samsung: exynos7: Corrects CMU_PERIC0 clocks names
On 04.09.2015 20:37, Alim Akhtar wrote: > This patch rename CMU_PERIC0 clocks names to match with user manual. > And also adds missing gate clock for aclk_peric0_66. > > Signed-off-by: Alim Akhtar <alim.akh...@samsung.com> > --- > drivers/clk/samsung/clk-exynos7.c | 12 > include/dt-bindings/clock/exynos7-clk.h |3 ++- > 2 files changed, 10 insertions(+), 5 deletions(-) > Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 09/11] clk: samsung: exynos7: Corrects CMU_FSYS1 clocks names
On 04.09.2015 20:37, Alim Akhtar wrote: > This patch rename CMU_FSYS1 clocks names to match with user manual. > And also adds missing gate clock for aclk_fsys1_200. > > Signed-off-by: Alim Akhtar <alim.akh...@samsung.com> > --- > drivers/clk/samsung/clk-exynos7.c | 16 ++-- > include/dt-bindings/clock/exynos7-clk.h |3 ++- > 2 files changed, 12 insertions(+), 7 deletions(-) Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 08/11] clk: samsung: exynos7: Corrects CMU_FSYS0 clocks names
On 04.09.2015 20:37, Alim Akhtar wrote: > This patch rename CMU_FSYS0 clocks names to match with user manual. > And also adds missing gate clock for aclk_fsys0_200. > > Signed-off-by: Alim Akhtar <alim.akh...@samsung.com> > --- > drivers/clk/samsung/clk-exynos7.c | 24 ++-- > include/dt-bindings/clock/exynos7-clk.h |3 ++- > 2 files changed, 16 insertions(+), 11 deletions(-) > Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/11] clk: samsung: exynos7: Corrects CMU_PERIS clocks names
On 04.09.2015 20:37, Alim Akhtar wrote: > This patch rename CMU_PERIS clocks names to match with user manual. > And also adds missing gate clock for aclk_peris_66. > > Signed-off-by: Alim Akhtar <alim.akh...@samsung.com> > --- > drivers/clk/samsung/clk-exynos7.c |7 +-- > include/dt-bindings/clock/exynos7-clk.h |3 ++- > 2 files changed, 7 insertions(+), 3 deletions(-) Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/11] clk: samsung: exynos7: Corrects CMU_PERIC1 clocks names
On 04.09.2015 20:37, Alim Akhtar wrote: > This patch rename CMU_PERIC1 clocks names to match with user manual. > And also adds missing gate clock for aclk_peric1_66. > > Signed-off-by: Alim Akhtar <alim.akh...@samsung.com> > --- > drivers/clk/samsung/clk-exynos7.c | 38 > --- > include/dt-bindings/clock/exynos7-clk.h |3 ++- > 2 files changed, 22 insertions(+), 19 deletions(-) Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] arm64: dts: Add BUS1 instance pinctrl support
Hi On 08/31/2015 11:12 AM, Krzysztof Kozlowski wrote: On 28.08.2015 20:25, Alim Akhtar wrote: This adds BUS1 instance pinctrl for exynos7 soc. Signed-off-by: Alim Akhtar <alim.akh...@samsung.com> --- arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 111 +++ arch/arm64/boot/dts/exynos/exynos7.dtsi |7 ++ 2 files changed, 118 insertions(+) The "etc1" GPIO in my datasheet is not fully documented but the rest looks good: Ok will send v2 and remove etc1 gpio node. Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com> Thanks!! Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 5/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, watchdog and adc
on Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45
arch/arm64/boot/dts/exynos/exynos7.dtsi | 276 +++
2 files changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..5424cc4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = serial_2;
+ mshc0 = mmc_0;
+ mshc2 = mmc_2;
};
chosen {
@@ -37,3 +39,46 @@
serial_2 {
status = okay;
};
+
+rtc {
+ status = okay;
+};
+
+watchdog {
+ status = okay;
+};
+
+adc {
+ status = okay;
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ cap-mmc-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_qrdy sd0_bus1 sd0_bus4 sd0_bus8;
+ bus-width = 8;
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ cap-sd-highspeed;
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+ bus-width = 4;
+ disable-wp;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 2bce3f3..cff0256 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
dout_sclk_mfc_pll;
};
+ clock_top1: clock-controller@105e {
+ compatible = samsung,exynos7-clock-top1;
+ reg = 0x105e 0xb000;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_SCLK_BUS0_PLL,
+clock_topc DOUT_SCLK_BUS1_PLL,
+clock_topc DOUT_SCLK_CC_PLL,
+clock_topc DOUT_SCLK_MFC_PLL;
+ clock-names = fin_pll, dout_sclk_bus0_pll,
+ dout_sclk_bus1_pll, dout_sclk_cc_pll,
+ dout_sclk_mfc_pll;
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = samsung,exynos7-clock-ccore;
+ reg = 0x105b 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_ACLK_CCORE_133;
+ clock-names = fin_pll, dout_aclk_ccore_133;
+ };
+
clock_peric0: clock-controller@1361 {
compatible = samsung,exynos7-clock-peric0;
reg = 0x1361 0xd00;
@@ -143,6 +164,27 @@
clock-names = fin_pll, dout_aclk_peris_66;
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = samsung,exynos7-clock-fsys0;
+ reg = 0x10e9 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS0_200,
+clock_top1 DOUT_SCLK_MMC2;
+ clock-names = fin_pll, dout_aclk_fsys0_200,
+ dout_sclk_mmc2;
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = samsung,exynos7-clock-fsys1;
+ reg = 0x156e 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS1_200,
+clock_top1 DOUT_SCLK_MMC0,
+clock_top1 DOUT_SCLK_MMC1;
+ clock-names = fin_pll, dout_aclk_fsys1_200,
+ dout_sclk_mmc0, dout_sclk_mmc1;
+ };
+
serial_0: serial@1363 {
compatible = samsung,exynos4210-uart;
reg = 0x1363 0x100;
@@ -236,6 +278,162 @@
interrupts = 0 203 0;
};
+ hsi2c_0: hsi2c@1364 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1364 0x1000;
+ interrupts = 0 441 0
[PATCH v7 5/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on Exynos7
Add nodes for 3 mmc channels, 12 i2c channels, rtc, watchdog and adc
on Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45
arch/arm64/boot/dts/exynos/exynos7.dtsi | 276
2 files changed, 321 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..5424cc4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = serial_2;
+ mshc0 = mmc_0;
+ mshc2 = mmc_2;
};
chosen {
@@ -37,3 +39,46 @@
serial_2 {
status = okay;
};
+
+rtc {
+ status = okay;
+};
+
+watchdog {
+ status = okay;
+};
+
+adc {
+ status = okay;
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ cap-mmc-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_qrdy sd0_bus1 sd0_bus4 sd0_bus8;
+ bus-width = 8;
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ cap-sd-highspeed;
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+ bus-width = 4;
+ disable-wp;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8aab9f9..d7a37c3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
dout_sclk_mfc_pll;
};
+ clock_top1: clock-controller@105e {
+ compatible = samsung,exynos7-clock-top1;
+ reg = 0x105e 0xb000;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_SCLK_BUS0_PLL,
+clock_topc DOUT_SCLK_BUS1_PLL,
+clock_topc DOUT_SCLK_CC_PLL,
+clock_topc DOUT_SCLK_MFC_PLL;
+ clock-names = fin_pll, dout_sclk_bus0_pll,
+ dout_sclk_bus1_pll, dout_sclk_cc_pll,
+ dout_sclk_mfc_pll;
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = samsung,exynos7-clock-ccore;
+ reg = 0x105b 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_ACLK_CCORE_133;
+ clock-names = fin_pll, dout_aclk_ccore_133;
+ };
+
clock_peric0: clock-controller@1361 {
compatible = samsung,exynos7-clock-peric0;
reg = 0x1361 0xd00;
@@ -143,6 +164,27 @@
clock-names = fin_pll, dout_aclk_peris_66;
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = samsung,exynos7-clock-fsys0;
+ reg = 0x10e9 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS0_200,
+clock_top1 DOUT_SCLK_MMC2;
+ clock-names = fin_pll, dout_aclk_fsys0_200,
+ dout_sclk_mmc2;
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = samsung,exynos7-clock-fsys1;
+ reg = 0x156e 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1 DOUT_ACLK_FSYS1_200,
+clock_top1 DOUT_SCLK_MMC0,
+clock_top1 DOUT_SCLK_MMC1;
+ clock-names = fin_pll, dout_aclk_fsys1_200,
+ dout_sclk_mmc0, dout_sclk_mmc1;
+ };
+
serial_0: serial@1363 {
compatible = samsung,exynos4210-uart;
reg = 0x1363 0x100;
@@ -236,6 +278,162 @@
interrupts = 0 203 0;
};
+ hsi2c_0: hsi2c@1364 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1364 0x1000;
+ interrupts = 0 441 0
Re: [PATCH v2 6/7] arm64: dts: Add nodes for mmc, i2c, rtc, watchdog on Exynos7
Hi Abhilash,
On Tue, Oct 21, 2014 at 11:13 AM, Abhilash Kesavan
a.kesa...@samsung.com wrote:
Add nodes for 3 mmc channels, 12 i2c channels, rtc, and watchdog
on Exynos7.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 41
arch/arm64/boot/dts/exynos/exynos7.dtsi | 256
+++
2 files changed, 297 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index e2c8283..d081c26 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -18,6 +18,8 @@
aliases {
serial0 = serial_2;
+ mshc0 = mmc_0;
+ mshc2 = mmc_2;
};
chosen {
@@ -37,3 +39,42 @@
serial_2 {
status = okay;
};
+
+rtc {
+ status = okay;
+};
+
+watchdog {
+ status = okay;
+};
+
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
Please use mmc_hs200-1_8v instead.
+ supports-highspeed;
As per synopsys-dw-mshc DT binding documentation, supports-highspeed
property is deprecated, so please use common DT binding for this,
which is cap-mmc-highspeed.
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_qrdy sd0_bus1 sd0_bus4
sd0_bus8;
+ bus-width = 8;
+};
+
+mmc_2 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
Here also common DT binding please cap-sd-highspeed
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+ bus-width = 4;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6db8c78..1300ded 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -113,6 +113,27 @@
dout_sclk_mfc_pll;
};
+ clock_top1: clock-controller@105e {
+ compatible = samsung,exynos7-clock-top1;
+ reg = 0x105e 0xb000;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc DOUT_SCLK_BUS0_PLL,
+clock_topc DOUT_SCLK_BUS1_PLL,
+clock_topc DOUT_SCLK_CC_PLL,
+clock_topc DOUT_SCLK_MFC_PLL;
+ clock-names = fin_pll, dout_sclk_bus0_pll,
+ dout_sclk_bus1_pll,
dout_sclk_cc_pll,
+ dout_sclk_mfc_pll;
+ };
+
+ clock_ccore: clock-controller@105b {
+ compatible = samsung,exynos7-clock-ccore;
+ reg = 0x105b 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_topc
DOUT_ACLK_CCORE_133;
+ clock-names = fin_pll, dout_aclk_ccore_133;
+ };
+
clock_peric0: clock-controller@1361 {
compatible = samsung,exynos7-clock-peric0;
reg = 0x1361 0xd00;
@@ -143,6 +164,27 @@
clock-names = fin_pll, dout_aclk_peris_66;
};
+ clock_fsys0: clock-controller@10e9 {
+ compatible = samsung,exynos7-clock-fsys0;
+ reg = 0x10e9 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1
DOUT_ACLK_FSYS0_200,
+clock_top1 DOUT_SCLK_MMC2;
+ clock-names = fin_pll, dout_aclk_fsys0_200,
+ dout_sclk_mmc2;
+ };
+
+ clock_fsys1: clock-controller@156e {
+ compatible = samsung,exynos7-clock-fsys1;
+ reg = 0x156e 0xd00;
+ #clock-cells = 1;
+ clocks = fin_pll, clock_top1
DOUT_ACLK_FSYS1_200,
+clock_top1 DOUT_SCLK_MMC0,
+clock_top1 DOUT_SCLK_MMC1;
+ clock-names = fin_pll, dout_aclk_fsys1_200,
+ dout_sclk_mmc0, dout_sclk_mmc1
[PATCH 05/14] pinctrl: exynos: Add driver data for Exynos7
This patch adds driver data for Exynos7
to pinctrl-exynos driver. Exynos7 includes 229 multi-functional
input/output ports. There are 40 general port groups.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: linus.wall...@linaro.org
Cc: Thomas Abraham thomas...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/Kconfig|2 +-
drivers/pinctrl/samsung/pinctrl-exynos.c | 145
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
5 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..2da258f 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- samsung,exynos5250-pinctrl: for Exynos5250 compatible pin-controller.
- samsung,exynos5260-pinctrl: for Exynos5260 compatible pin-controller.
- samsung,exynos5420-pinctrl: for Exynos5420 compatible pin-controller.
+ - samsung,exynos7-pinctrl: for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
index d0461cd..c660d31 100644
--- a/drivers/pinctrl/samsung/Kconfig
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -8,7 +8,7 @@ config PINCTRL_SAMSUNG
config PINCTRL_EXYNOS
bool Pinctrl driver data for Samsung EXYNOS SoCs other than 5440
- depends on OF GPIOLIB (ARCH_EXYNOS || ARCH_S5PV210)
+ depends on OF GPIOLIB (ARCH_EXYNOS || ARCH_S5PV210 ||
ARCH_EXYNOS7)
select PINCTRL_SAMSUNG
config PINCTRL_EXYNOS5440
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 003bfd8..8e9152b 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1121,3 +1121,148 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
.label = exynos5420-gpio-ctrl4,
},
};
+
+/* pin banks of exynos7 pin-controller 0 */
+static struct samsung_pin_bank exynos7_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, gpa3, 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller 1 (AUD) */
+static struct samsung_pin_bank exynos7_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/* pin banks of exynos7 pin-controller 2 (BUS0) */
+static struct samsung_pin_bank exynos7_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, gpb0, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpc0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, gpc1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, gpc2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, gpc3, 0x14),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, gpd0, 0x18),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, gpd1, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, gpd2, 0x20),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, gpd4, 0x24),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, gpd5, 0x28),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, gpd6, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, gpd7, 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, gpd8, 0x34),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, gpg0, 0x38),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, gpg3, 0x3c),
+};
+
+/* pin banks of exynos7 pin-controller 3 (BUS1) */
+static struct samsung_pin_bank exynos7_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpf0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpf1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, gpf2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, gpf3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpf4, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0c0, gpf5, 0x14),
+ EXYNOS_PIN_BANK_EINTG(5, 0x0e0, gpg1, 0x18),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, gpg2, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x120, gph1, 0x20),
+ EXYNOS_PIN_BANK_EINTG(3, 0x140, gpv6, 0x24),
+};
+
+/* pin banks of exynos7 pin-controller 4 (NFC) */
+static struct samsung_pin_bank exynos7_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj0, 0x00),
+};
+
+/* pin banks of exynos7 pin-controller 5 (TOUCH) */
+static struct samsung_pin_bank exynos7_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj1, 0x00),
+};
+
+/* pin banks of exynos7 pin-controller 6 (FF) */
+static struct samsung_pin_bank exynos7_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, gpg4, 0x00),
+};
+
+/* pin banks of exynos7 pin-controller 7 (ESE
[PATCH 1/4] clk: samsung: exynos7: add clocks for CPU block
Add clock support for the Atlas CPU block in Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 121
include/dt-bindings/clock/exynos7-clk.h| 20 +++-
3 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f8..0b4ba7f 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-atlas
- samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
@@ -61,6 +62,11 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for atlas clock controller:
+ - fin_pll
+ - fout_atlas_pll
+ - mout_sclk_bus0_pll_atlas
+
Input clocks for ccore clock controller:
- fin_pll
- dout_aclk_ccore_133
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index a79bf23..78f66b4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -35,6 +35,34 @@
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
+static const struct samsung_pll_rate_table pll1450x_24mhz_tbl[] = {
+ /* rate, m, p, s */
+ PLL_35XX_RATE(249600, 208, 2, 0),
+ PLL_35XX_RATE(24, 200, 2, 0),
+ PLL_35XX_RATE(230400, 288, 3, 0),
+ PLL_35XX_RATE(22, 275, 3, 0),
+ PLL_35XX_RATE(21, 175, 2, 0),
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(189600, 158, 2, 0),
+ PLL_35XX_RATE(18, 150, 2, 0),
+ PLL_35XX_RATE(170400, 142, 2, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 2, 1),
+ PLL_35XX_RATE(14, 350, 3, 1),
+ PLL_35XX_RATE(13, 325, 3, 1),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 350, 3, 2),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -50,6 +78,8 @@ PNAME(mout_bus1_pll_ctrl_p) = { fin_pll, fout_bus1_pll
};
PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
PNAME(mout_mfc_pll_ctrl_p) = { fin_pll, fout_mfc_pll };
+PNAME(mout_topc_group1)= { mout_bus0_pll_ctrl,
ffac_topc_bus0_pll_div2,
+mout_bus1_pll_ctrl, mout_cci_pll };
PNAME(mout_topc_group2) = { mout_sclk_bus0_pll_cmuc,
mout_sclk_bus1_pll_cmuc, mout_sclk_cc_pll_cmuc,
mout_sclk_mfc_pll_cmuc };
@@ -104,6 +134,8 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata
= {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(MOUT_SCLK_BUS0_PLL_ATLAS, mout_sclk_bus0_pll_atlas,
+ mout_topc_group1, MUX_SEL_TOPC1, 4, 2),
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -402,6 +434,95 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, samsung,exynos7-clock-top1,
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_ATLAS (0x1180) */
+#defineATLAS_PLL_LOCK 0x
+#defineATLAS_PLL_CON0 0x0100
+#defineMUX_SEL_ATLAS0 0x0200
+#defineMUX_SEL_ATLAS1 0x0204
+#defineMUX_SEL_ATLAS2 0x0208
+#defineDIV_ATLAS0 0x0600
+#defineDIV_ATLAS1 0x0604
+#defineENABLE_IP_ATLAS00x0B00
+
+/* List of parent clocks for Muxes in CMU_ATLAS */
+PNAME(mout_atlas_pll_ctrl_p) = { fin_pll, fout_atlas_pll };
+PNAME(mout_bus_pll_atlas_p) = { fin_pll, mout_sclk_bus0_pll_atlas };
+PNAME(mout_atlas_p) = { mout_atlas_pll_ctrl, mout_bus_pll_atlas };
+
+static unsigned long atlas_clk_regs[] __initdata = {
+ ATLAS_PLL_LOCK,
+ ATLAS_PLL_CON0,
+ MUX_SEL_ATLAS0,
+ MUX_SEL_ATLAS1,
+ MUX_SEL_ATLAS2
[PATCH v2 1/3] clk: samsung: exynos7: add clocks for CPU block
Add clock support for the Atlas CPU block in Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 121
include/dt-bindings/clock/exynos7-clk.h| 20 +++-
3 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6bf1e74..bcf274b5 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -28,6 +28,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-topc
- samsung,exynos7-clock-top0
- samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-atlas
- samsung,exynos7-clock-ccore
- samsung,exynos7-clock-peric0
- samsung,exynos7-clock-peric1
@@ -64,6 +65,11 @@ Input clocks for top1 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for atlas clock controller:
+ - fin_pll
+ - fout_atlas_pll
+ - mout_sclk_bus0_pll_atlas
+
Input clocks for ccore clock controller:
- fin_pll
- dout_aclk_ccore_133
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index b61724b..cec026c 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -36,6 +36,34 @@
#define DIV_TOPC3 0x060C
#define ENABLE_ACLK_TOPC1 0x0804
+static const struct samsung_pll_rate_table pll1450x_24mhz_tbl[] = {
+ /* rate, m, p, s */
+ PLL_35XX_RATE(249600, 208, 2, 0),
+ PLL_35XX_RATE(24, 200, 2, 0),
+ PLL_35XX_RATE(230400, 192, 2, 0),
+ PLL_35XX_RATE(22, 275, 3, 0),
+ PLL_35XX_RATE(21, 175, 2, 0),
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(189600, 158, 2, 0),
+ PLL_35XX_RATE(18, 150, 2, 0),
+ PLL_35XX_RATE(170400, 142, 2, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 2, 1),
+ PLL_35XX_RATE(14, 350, 3, 1),
+ PLL_35XX_RATE(13, 325, 3, 1),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 350, 3, 2),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
FFACTOR(0, ffac_topc_bus0_pll_div4,
@@ -57,6 +85,8 @@ PNAME(mout_bus1_pll_ctrl_p) = { fin_pll, fout_bus1_pll
};
PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
PNAME(mout_mfc_pll_ctrl_p) = { fin_pll, fout_mfc_pll };
+PNAME(mout_topc_group1)= { mout_bus0_pll_ctrl,
ffac_topc_bus0_pll_div2,
+mout_bus1_pll_ctrl, mout_cc_pll_ctrl };
PNAME(mout_topc_group2) = { mout_sclk_bus0_pll_cmuc,
mout_sclk_bus1_pll_cmuc, mout_sclk_cc_pll_cmuc,
mout_sclk_mfc_pll_cmuc };
@@ -111,6 +141,8 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata
= {
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(MOUT_SCLK_BUS0_PLL_ATLAS, mout_sclk_bus0_pll_atlas,
+ mout_topc_group1, MUX_SEL_TOPC1, 4, 2),
MUX(0, mout_aud_pll_ctrl, mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -504,6 +536,95 @@ static void __init exynos7_clk_top1_init(struct
device_node *np)
CLK_OF_DECLARE(exynos7_clk_top1, samsung,exynos7-clock-top1,
exynos7_clk_top1_init);
+/* Register Offset definitions for CMU_ATLAS (0x1180) */
+#defineATLAS_PLL_LOCK 0x
+#defineATLAS_PLL_CON0 0x0100
+#defineMUX_SEL_ATLAS0 0x0200
+#defineMUX_SEL_ATLAS1 0x0204
+#defineMUX_SEL_ATLAS2 0x0208
+#defineDIV_ATLAS0 0x0600
+#defineDIV_ATLAS1 0x0604
+#defineENABLE_SCLK_ATLAS 0x0A00
+
+/* List of parent clocks for Muxes in CMU_ATLAS */
+PNAME(mout_atlas_pll_ctrl_p) = { fin_pll, fout_atlas_pll };
+PNAME(mout_bus_pll_atlas_p) = { fin_pll, mout_sclk_bus0_pll_atlas };
+PNAME(mout_atlas_p) = { mout_atlas_pll_ctrl, mout_bus_pll_atlas };
+
+static unsigned long atlas_clk_regs[] __initdata = {
+ ATLAS_PLL_LOCK,
+ ATLAS_PLL_CON0
Re: [PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7
Hi Olof,
On 28 August 2014 09:26, Olof Johansson o...@lixom.net wrote:
Hi,
On Wed, Aug 27, 2014 at 03:14:18PM +0530, Naveen Krishna Chatradhi wrote:
Add initial device tree nodes for EXYNOS7 SoC.
Also, includes the dt-binding definitions for clock ids.
Uh, no -- it just adds the dtsi.
Ok. Will fix.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/exynos7.dtsi | 553
++
1 file changed, 553 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/exynos7.dtsi
b/arch/arm64/boot/dts/exynos7.dtsi
new file mode 100644
index 000..6b9eaf4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos7.dtsi
Let's not make the same mistake as on 32-bit, and go with a directory
hierarchy here from day one.
So, please create a exynos subdirectory for this file. You also need
a Makefile when you add a board dts.
Ok. Will fix.
@@ -0,0 +1,553 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS7 SoC device nodes are listed in this file.
+ * EXYNOS7 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 1;
+ #size-cells = 1;
You should probably use address-cells/size-cells 2/2 on a 64-bit platform.
Ok.
+ aliases {
+ pinctrl0 = pinctrl_0;
+ pinctrl1 = pinctrl_1;
+ pinctrl2 = pinctrl_2;
+ pinctrl3 = pinctrl_3;
+ pinctrl4 = pinctrl_4;
+ pinctrl5 = pinctrl_5;
+ pinctrl6 = pinctrl_6;
+ pinctrl7 = pinctrl_7;
+ pinctrl8 = pinctrl_8;
+ pinctrl9 = pinctrl_9;
+ mshc0 = mmc_0;
+ mshc2 = mmc_2;
+ };
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
Why size-cells=2? Can you not fit a cpuid in 32 bits?
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x0 0x0;
+ };
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ };
+
+ hsi2c_0: hsi2c@1364 {
+ compatible = samsung,exynos7-hsi2c;
Is the i2c controller here completely new?
It is almost the same as in Exynos5 but few register bits have been
changed. So we have added a new compatible string.
Also, please use 'i2c' for node name on these nodes.
Ok.
+ reg = 0x1364 0x1000;
+ interrupts = 0 441 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = hs_i2c0_bus;
+ clocks = clock_peric0 PCLK_HSI2C0;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_1: hsi2c@1365 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1365 0x1000;
+ interrupts = 0 442 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = hs_i2c1_bus;
+ clocks = clock_peric0 PCLK_HSI2C1;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_2: hsi2c@14E6 {
I much prefer lowercase hex in unit addresses (and reg entries) below. I
know 32-bit uses uppercase, but let's switch going forward here.
Ok. Will fix.
+ mct@101C {
+ compatible = samsung,exynos4210-mct;
Please just do away with MCT here, and use architected timers going
forward. There really shouldn't be a need to keep supporting MCT any
more -- it's a construct from before arch timers on Cortex-A9.
Ok.
+ mmc_0: mmc@1574
[PATCH v2 5/5] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch naveenkrishna...@gmail.com Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com Cc: Tomasz Figa tomasz.f...@gmail.com Cc: Linus Walleij linus.wall...@linaro.org Cc: Thomas Abraham thomas...@samsung.com --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1874e1a..4ee1250 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -146,6 +146,8 @@ config ARCH_EXYNOS7 bool ARMv8 based Samsung Exynos7 select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 6/6] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch naveenkrishna...@gmail.com Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com Cc: Tomasz Figa tomasz.f...@gmail.com Cc: Linus Walleij linus.wall...@linaro.org --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1874e1a..4ee1250 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -146,6 +146,8 @@ config ARCH_EXYNOS7 bool ARMv8 based Samsung Exynos7 select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 6/6] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch naveenkrishna...@gmail.com Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com Acked-by: Tomasz Figa tomasz.f...@gmail.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com Cc: Linus Walleij linus.wall...@linaro.org --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 5285f9c..e8ddd84 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -145,6 +145,8 @@ config ARCH_EXYNOS7 bool ARMv8 based Samsung Exynos7 select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 6/6] arm64: exynos: Enable pinctrl support for Exynos7
From: Naveen Krishna Ch naveenkrishna...@gmail.com Enable pinctrl support for exynos7 SoCs. Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com Acked-by: Tomasz Figa tomasz.f...@gmail.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com Cc: Linus Walleij linus.wall...@linaro.org --- arch/arm64/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 56e5b7c..f9c42fa 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -155,6 +155,8 @@ config ARCH_EXYNOS7 bool ARMv8 based Samsung Exynos7 select ARCH_EXYNOS select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS help This enables support for Samsung Exynos7 SoC family -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/4] dwc3: exynos: Add support for SCLK present on Exynos7
Hi,
On Mon, Oct 13, 2014 at 01:54:59PM +0900, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk is not enough.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-
exynos.c
index 3951a65..7dc6a98 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -35,6 +35,7 @@ struct dwc3_exynos {
struct device *dev;
struct clk *clk;
The clock clk in Exynos5 just gated all that above 7 clocks, which
we should control separately now in Exynos7.
should I drop this patch for now ?
--
balbi
signature.asc
Description: Digital signature
Re: [PATCH v2 1/4] dwc3: exynos: Add support for SCLK present on Exynos7
Hi Anton, On 13.10.2014 06:54, Anton Tikhomirov wrote: Hi Vivek, Exynos7 also has a separate special gate clock going to the IP apart from the usual AHB clock. So add support for the same. As we discussed before, Exynos7 SoCs have 7 clocks to be controlled by the driver. Adding only sclk is not enough. I'm quite interested in this discussion. Has it happened on mailing lists? In general, previous SoCs also gave the possibility of controlling all the bus clocks separately, in addition to bulk gates, but there was no real advantage in using those, while burdening the clock tree with numerous clocks. Isn't Exynos7 similar in this aspect? Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL 2/4] Samsung serial updates for v3.19
Hi Arnd, Olof, Kevin Please pull this branch for exynos7 SoC into arm-soc. Note Greg agreed to upstream via arm-soc tree. Thanks, Kukjin The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1: Linux 3.18-rc1 (2014-10-19 18:08:38 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-driver for you to fetch changes up to edeeec85f7145fe8f2a5ffe250a8ee6b1fe4ab28: serial: samsung: Fix serial config dependencies for exynos7 (2014-11-22 00:09:25 +0900) Samsung driver update for v3.19 - Change samsung serial dependencies for exynos7 (ARMv8) Pankaj Dubey (1): serial: samsung: Fix serial config dependencies for exynos7 drivers/tty/serial/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
Hi Sylwester, On 12/22/14, Sylwester Nawrocki s.nawro...@samsung.com wrote: Hi, On 19/12/14 14:23, Padmavathi Venna wrote: Add required clk support for I2S,PCM amd SPDIF There is a non-trivial conflict with the MSCL CMU patch, could you please resend rebased onto my exynos7 branch: Ok. I willl rebase the patch on your tree. git://linuxtv.org/snawrocki/samsung.git for-v3.20/clk/exynos7 ? Is exynos7420 documentation applicable to this ? This is applicable only for exynos7. Would be nice to have someone else who has access to the SoC documentation replied with a Reviewed-by tag. -- Thanks, Sylwester Thanks Padma -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 12/14] arm64: dts: add Exynos7 based Espresso board dts file
This patch adds initial dts file for the Espresso board
based on Exynos7 from Samsung.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/exynos7-espresso.dts | 69 ++
2 files changed, 70 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos7-espresso.dts
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..d160de1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
targets += dtbs
targets += $(dtb-y)
diff --git a/arch/arm64/boot/dts/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos7-espresso.dts
new file mode 100644
index 000..e35e83c
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos7-espresso.dts
@@ -0,0 +1,69 @@
+/*
+ * SAMSUNG Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+#include exynos7.dtsi
+
+/ {
+ model = Samsung ESPRESSO board based on EXYNOS7;
+ compatible = samsung,espresso, samsung,exynos7;
+
+ chosen {
+ bootargs = console=ttySAC2,115200n8 root=/dev/ram0
ramdisk=16384 initrd=0x4200,16M init=/linuxrc;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x4000 0xC000;
+ };
+
+ mmc@1574 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
+ supports-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_rdqs sd0_bus1 sd0_bus4
sd0_bus8;
+ bus-width = 8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1556 {
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+ bus-width = 4;
+
+ slot@0 {
+ reg = 0;
+ disable-wp;
+ bus-width = 4;
+ };
+ };
+};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 12/14] arm64: dts: add Exynos7 based Espresso board dts file
Hi,
On Wed, Aug 27, 2014 at 03:14:19PM +0530, Naveen Krishna Chatradhi wrote:
This patch adds initial dts file for the Espresso board
based on Exynos7 from Samsung.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/exynos7-espresso.dts | 69
++
2 files changed, 70 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos7-espresso.dts
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..d160de1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
As mentioned on the dtsi patch, please create a subdirectory.
targets += dtbs
targets += $(dtb-y)
diff --git a/arch/arm64/boot/dts/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos7-espresso.dts
new file mode 100644
index 000..e35e83c
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos7-espresso.dts
@@ -0,0 +1,69 @@
+/*
+ * SAMSUNG Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+#include exynos7.dtsi
+
+/ {
+ model = Samsung ESPRESSO board based on EXYNOS7;
+ compatible = samsung,espresso, samsung,exynos7;
+
+ chosen {
+ bootargs = console=ttySAC2,115200n8 root=/dev/ram0
ramdisk=16384 initrd=0x4200,16M init=/linuxrc;
Having ramdisk bootargs like these in the upstream dts doesn't make much
sense. Configure your bootloader to pass them in instead.
You might want to specify the console through chosen instead, there's
been recent support added for that.
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x4000 0xC000;
+ };
+
+ mmc@1574 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
+ supports-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_rdqs sd0_bus1 sd0_bus4
sd0_bus8;
+ bus-width = 8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
I thought the use of slot was deprecated. Why do you have it here?
Also, as mentioned by others elsewhere, please use references instead
of duplicating the structure here.
-Olof
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Abhilash, Linus, On 09.10.2014 15:54, Abhilash Kesavan wrote: Changes since v4: - Rebased over Tomasz Figa's pinctrl clean-up patches[1] Changes since v3: - Changed variable name from exynos_wkup_irq_chip to irq_chip - Added acked-by tag from Tomasz Figa Changes since v2: - Added a .irq_chip field to the samsung_pin_bank struct - Consolidated the wakeup and gpio irqd_ops Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham This series has been tested on linux-next (20141008) https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ with the following dependencies and [1]. a) Samsung Serial symbol clean-up for exynos7 serial driver enablement (v2) http://www.spinics.net/lists/arm-kernel/msg366947.html http://www.spinics.net/lists/arm-kernel/msg366948.html b) dts, kbuild: Implement support for dtb vendor subdirs patchset - rebased http://comments.gmane.org/gmane.linux.kbuild.devel/12131 c) arch: arm64: enable support for Samsung Exynos7 SoC patchset (v5) - rebased http://www.spinics.net/lists/arm-kernel/msg364014.html [1] https://lkml.org/lkml/2014/10/2/476 Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 188 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 791 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi No further comments from me. Thanks Abhilash for addressing all of them. Linus, feel free to apply this series with my ACK (which seems to be already present in all patches). Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 0/6] Add initial support for pinctrl on Exynos7
Hi Linus, On Sun, Oct 12, 2014 at 12:27 AM, Tomasz Figa tomasz.f...@gmail.com wrote: Abhilash, Linus, On 09.10.2014 15:54, Abhilash Kesavan wrote: Changes since v4: - Rebased over Tomasz Figa's pinctrl clean-up patches[1] Changes since v3: - Changed variable name from exynos_wkup_irq_chip to irq_chip - Added acked-by tag from Tomasz Figa Changes since v2: - Added a .irq_chip field to the samsung_pin_bank struct - Consolidated the wakeup and gpio irqd_ops Changes since v1: - Marked the newly created irq_chip instances as __initdata - Used kmemdup to keep a copy of the irq_chip - Change the pinctrl name from sd0_rdqs to sd0_ds as per UM - Moved the pinctrl enablement for exynos7 into a separate patch - Added tested-by and reviewed-by tags from Thomas Abraham This series has been tested on linux-next (20141008) https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/ with the following dependencies and [1]. a) Samsung Serial symbol clean-up for exynos7 serial driver enablement (v2) http://www.spinics.net/lists/arm-kernel/msg366947.html http://www.spinics.net/lists/arm-kernel/msg366948.html b) dts, kbuild: Implement support for dtb vendor subdirs patchset - rebased http://comments.gmane.org/gmane.linux.kbuild.devel/12131 c) arch: arm64: enable support for Samsung Exynos7 SoC patchset (v5) - rebased http://www.spinics.net/lists/arm-kernel/msg364014.html [1] https://lkml.org/lkml/2014/10/2/476 Abhilash Kesavan (3): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Ch (3): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 arm64: exynos: Enable pinctrl support for Exynos7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 188 +-- drivers/pinctrl/samsung/pinctrl-exynos.h |3 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |3 + 8 files changed, 791 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi No further comments from me. Thanks Abhilash for addressing all of them. Linus, feel free to apply this series with my ACK (which seems to be already present in all patches). Can you please pick this series up. Thanks, Abhilash Best regards, Tomasz ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 02/12] clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC
This adds some of the missing GATE clocks of CMU_TOPC block.
Signed-off-by: Alim Akhtar <alim.akh...@samsung.com>
---
drivers/clk/samsung/clk-exynos7.c | 27 +++
include/dt-bindings/clock/exynos7-clk.h | 13 -
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
index df061ce..e11449b 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -34,7 +34,9 @@
#define DIV_TOPC0 0x0600
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
+#define ENABLE_ACLK_TOPC0 0x0800
#define ENABLE_ACLK_TOPC1 0x0804
+#define ENABLE_SCLK_TOPC1 0x0A04
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
@@ -145,8 +147,33 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[]
__initdata = {
};
static struct samsung_gate_clock topc_gate_clks[] __initdata = {
+ GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
+ ENABLE_ACLK_TOPC0, 4, 0, 0),
+
GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
ENABLE_ACLK_TOPC1, 20, 0, 0),
+
+ GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
+ ENABLE_ACLK_TOPC1, 24, 0, 0),
+
+ GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
+ ENABLE_SCLK_TOPC1, 20, 0, 0),
+ GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
+ ENABLE_SCLK_TOPC1, 17, 0, 0),
+ GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
+ ENABLE_SCLK_TOPC1, 16, 0, 0),
+ GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
+ ENABLE_SCLK_TOPC1, 13, 0, 0),
+ GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
+ ENABLE_SCLK_TOPC1, 12, 0, 0),
+ GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
+ ENABLE_SCLK_TOPC1, 5, 0, 0),
+ GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
+ ENABLE_SCLK_TOPC1, 4, 0, 0),
+ GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
+ ENABLE_SCLK_TOPC1, 1, 0, 0),
+ GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
+ ENABLE_SCLK_TOPC1, 0, 0, 0),
};
static struct samsung_pll_clock topc_pll_clks[] __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h
b/include/dt-bindings/clock/exynos7-clk.h
index e33c75a..d26fe0f 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -21,7 +21,18 @@
#define ACLK_MSCL_532 8
#define DOUT_SCLK_AUD_PLL 9
#define FOUT_AUD_PLL 10
-#define TOPC_NR_CLK11
+#define SCLK_AUD_PLL 11
+#define SCLK_MFC_PLL_B 12
+#define SCLK_MFC_PLL_A 13
+#define SCLK_BUS1_PLL_B14
+#define SCLK_BUS1_PLL_A15
+#define SCLK_BUS0_PLL_B16
+#define SCLK_BUS0_PLL_A17
+#define SCLK_CC_PLL_B 18
+#define SCLK_CC_PLL_A 19
+#define ACLK_CCORE_133 20
+#define ACLK_PERIS_66 21
+#define TOPC_NR_CLK22
/* TOP0 */
#define DOUT_ACLK_PERIC1 1
--
1.7.10.4
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
On 04/10/2014 06:40 PM, Arnd Bergmann wrote: On Thursday 10 April 2014 18:28:23 Chanwoo Choi wrote: +* while Exynos5 is A15/Exynos7 is A7; check the CPU part Exynos7 - Exynos3 ? You're right. I'll fix it. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/4] Add initial support for pinctrl on Exynos7
On Sat, Sep 13, 2014 at 2:20 PM, Abhilash Kesavan a.kesa...@samsung.com wrote: The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next Following patches are required for this series: 1- tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg36208.html 2- dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3- arch: arm64: enable support for Samsung Exynos7 SoC patchset http://www.spinics.net/lists/linux-samsung-soc/msg36728.html Abhilash Kesavan (2): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Chatradhi (2): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 161 +- drivers/pinctrl/samsung/pinctrl-exynos.h |4 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |1 + 8 files changed, 788 insertions(+), 11 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi Tested GPIO and Wakeup interrupts. After fixing comments for patches in this series, this series Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/4] dwc3: exynos: Add support for SCLK present on Exynos7
On Tue, Oct 07, 2014 at 03:49:33PM +0530, Vivek Gautam wrote: Exynos7 also has a separate special gate clock going to the IP apart from the usual AHB clock. So add support for the same. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com I'll take this one once -rc1 is tagged. The others have no direct dependency on this so I'll leave them to Kishon. -- balbi signature.asc Description: Digital signature
Re: [PATCH] arm64: dts: exynos7: add support for cpuidle core power down
On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
Exynos7 has core power down state where cores can be powered off
independently.
This patch adds support for this state.
Please tell us more about the idle-state values you are adding, in particular
entry, exit latencies and min-residency values.
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
- [PATCH v9 0/8] ARM generic idle states
http://permalink.gmane.org/gmane.linux.power-management.general/49224
Series above was merged, so dependency is stale.
arch/arm64/boot/dts/exynos/exynos7.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..8e0a034 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -36,6 +36,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
I would add cpu-idle-states phandle after the reg property, as defined
in the idle states bindings.
reg = 0x0;
};
@@ -43,6 +44,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
reg = 0x1;
};
@@ -50,6 +52,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
reg = 0x2;
};
@@ -57,8 +60,23 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
reg = 0x3;
};
+
+ idle-states {
+ entry-method = arm,psci;
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = arm,idle-state;
+ local-timer-stop;
+ arm,psci-suspend-param = 0x001;
+ entry-latency-us = 20;
+ exit-latency-us = 150;
+ min-residency-us = 2100;
+ status = enabled;
status ? This is not a documented property. If you need it please explain
why, define its bindings and we can see how to accommodate it.
Thank you,
Lorenzo
+ };
+ };
};
psci {
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4] arm64: dts: exynos7: add support for cpuidle core power down
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.
Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in the set of 10 cpuidle transactions,
with varying load.
Exit latency and target residency are supplied as per HW team
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.
Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.
arch/arm64/boot/dts/exynos/exynos7.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x0;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x1;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x2;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x3;
+ cpu-idle-states = CPU_SLEEP;
+ };
+
+ idle-states {
+ entry-method = arm,psci;
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = arm,idle-state;
+ local-timer-stop;
+ arm,psci-suspend-param = 0x001;
+ entry-latency-us = 34;
+ exit-latency-us = 150;
+ min-residency-us = 2100;
+ };
};
};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5] arm64: dts: exynos7: add support for cpuidle core power down
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.
This patch adds support for core power down idle state.
Entry latency for core power down idle state is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in a set of 10 cpuidle transactions,
with varying load.
Exit latency and min residency values are supplied as per HW team.
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
www.spinics.net/lists/arm-kernel/msg375961.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.
Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.
Changes in v5:
- Commit message modified
arch/arm64/boot/dts/exynos/exynos7.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..891eef4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x0;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x1;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x2;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
};
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x3;
enable-method = psci;
+ cpu-idle-states = CPU_SLEEP;
+ };
+
+ idle-states {
+ entry-method = arm,psci;
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = arm,idle-state;
+ local-timer-stop;
+ arm,psci-suspend-param = 0x001;
+ entry-latency-us = 34;
+ exit-latency-us = 150;
+ min-residency-us = 2100;
+ };
};
};
--
1.9.1
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
