Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Thierry Reding and Heiko suggest, leave sclk_edp_24m to rockchip
dp
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
collect the phy clocks and power control.
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt| 26 +++
drivers/phy/Kconfig
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property value directly, but we can take those as hardware limite.
For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
- Fix compile failed dut to phy_pd_addr variable misspell error
Yakir Yang (14):
drm: exynos/dp: fix code style
drm: exynos/dp: convert to drm bridge mode
drm: bridge: analogix_dp: split exynos dp driver to bridge dir
drm: bridge/analogix_dp: dynamic parse sync_pol interlace
After run checkpatch.pl -f --subjective command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid
-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Thierry Reding suggest, dynamic parse video timing info from
struct drm_display_mode and struct drm_display_info.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 50 --
drivers/gpu/drm/exynos/analogix_dp
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
analogix,need-force-hpd to indicate this sutiation.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Add
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- move dp hpd detect to connector detect function.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Add edid modes parse support
Changes in v2
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2: None
Hi Dave,
On 08/19/2015 06:54 PM, Dave Airlie wrote:
On 20 August 2015 at 00:48, Yakir Yang y...@rock-chips.com wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Hi Jingoo,
On 08/20/2015 02:22 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:50, Yakir Yang y...@rock-chips.com wrote:
link_rate and lane_count already configed in analogix_dp_set_link_train(),
s/configed/configured
Also, the commit name such as fix ... bug is not good.
How about following
Hi Jingoo,
在 08/24/2015 03:40 PM, Jingoo Han 写道:
On 2015. 8. 24., at AM 9:43, Krzysztof Kozlowski k.kozlow...@samsung.com
wrote:
2015-08-24 8:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
Analogix dp driver is split
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote
Hi Jingoo,
On 08/20/2015 01:55 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 3:23, Yakir Yang y...@rock-chips.com wrote:
Hi Jingoo Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja arch...@codeaurora.org wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir
Hi Jingoo,
On 08/20/2015 02:49 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang y...@rock-chips.com wrote:
What is the reason to make this patch?
Please make commit message including the reason.
Okay, I think the below words would be okay :)
This change just make a little
Hi Jingoo,
On 08/20/2015 01:11 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang y...@rock-chips.com wrote:
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works
Hi Jingoo Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja arch...@codeaurora.org wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot
Hi Ravi,
I'm wondering is your e-mail come from eDP thread ? cause I see lots of
cc guys some as eDP emails :)
And for your question, I am not sure I understand rightly. Do you mean
that your .ko module not in
the same directory with driver source code?
If it's your question, I think you
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt
Hi Rob,
在 08/23/2015 06:23 PM, Rob Herring 写道:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file
Daniel,
在 2015/8/7 19:25, Daniel Vetter 写道:
On Thu, Aug 06, 2015 at 10:29:29PM +0800, Yakir Yang wrote:
Hi Jingoo,
在 2015/8/6 22:19, Jingoo Han 写道:
On Thursday, August 06, 2015 11:07 PM, Yakir Yang wrote:
In order to move exynos dp code to bridge directory,
we need to convert driver drm
compile failed dut to phy_pd_addr variable misspell error
Yakir Yang (8):
drm: exynos/dp: fix code style
drm: exynos/dp: convert to drm bridge mode
drm: bridge: analogix_dp: split exynos dp driver to bridge dir
drm: rockchip/dp: add rockchip platform dp driver
drm: bridge/analogix_dp: add
After run checkpatch.pl -f --subjective command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid using some uncommon
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2: None
drivers/gpu/drm
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2:
- Take Jingoo Han
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
Besides TRM indicate that if HPD_STATUS(RO) is 0, AUX CH will not
work, so we need to give a force hpd action to set HPD_STATUS manually.
Signed-off-by: Yakir Yang y...@rock-chips.com
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
Hi Thierry,
在 2015/8/10 21:17, Thierry Reding 写道:
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = 0;
vsync-active-high = 0;
interlaced = 0;
These look like they should
Hi Heiko,
在 2015/8/10 20:08, Heiko Stübner 写道:
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp-dev;
+ struct device_node *np = dev-of_node;
+ int ret;
+
+ dp-grf
still trying to integrate this into my development-tree.
Am Freitag, 7. August 2015, 05:46:20 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang y
Signed-off-by: Yakir Yang y...@rock-chips.com
---
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 6 ++
3 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/exynos
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
Besides TRM indicate that if HPD_STATUS(RO) is 0, AUX CH will not
work, so we need to give a force hpd action to set HPD_STATUS manually.
Signed-off-by: Yakir Yang y...@rock-chips.com
.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
register).
My series patches can be divider into two parts: One for spliting the
analogix_dp code from exynos dp driver. Another are trying to add rk3288
dp driver support.
Best regards,
- Yakir
Yakir Yang (8):
drm
make checkpatch.pl script happy
Signed-off-by: Yakir Yang y...@rock-chips.com
---
drivers/gpu/drm/exynos/exynos_dp_core.c | 224
drivers/gpu/drm/exynos/exynos_dp_core.h | 53
drivers/gpu/drm/exynos/exynos_dp_reg.c | 100 +++---
3 files
make checkpatch.pl script happy
Signed-off-by: Yakir Yang y...@rock-chips.com
---
drivers/gpu/drm/exynos/exynos_dp_core.c | 224
drivers/gpu/drm/exynos/exynos_dp_core.h | 53
drivers/gpu/drm/exynos/exynos_dp_reg.c | 100 +++---
3 files changed
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
drivers/gpu/drm/bridge/analogix_dp_reg.h | 12 +
2 files
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
drivers/gpu/drm/exynos
Hi Jingoo,
在 2015/8/6 22:19, Jingoo Han 写道:
On Thursday, August 06, 2015 11:07 PM, Yakir Yang wrote:
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
drivers/gpu/drm/bridge
Jingoo,
在 2015/8/6 22:33, Jingoo Han 写道:
On Thursday, August 06, 2015 11:19 PM, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.
Signed-off-by: Yakir Yang y...@rock
Jingoo,
在 2015/8/6 22:41, Jingoo Han 写道:
On Thursday, August 06, 2015 10:49 PM, Yakir Yang wrote:
Hi all,
Samsung exynos and Rockchip rk3288 almost share same dp controller,
so I split the common code out, then rk3288 and exynos can re-used the
same dp core driver. Cause I can't find
Joe,
在 2015/8/6 23:05, Joe Perches 写道:
On Thu, 2015-08-06 at 09:04 -0500, Yakir Yang wrote:
make checkpatch.pl script happy
That should not be the primary reason to submit a patch.
Making it easier for human code reader to understand
what the code does should be though.
Thanks for your reply
在 2015/8/24 22:48, Rob Herring 写道:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
+ -analogix,color-depth
Hi Heiko,
在 2015/8/24 21:03, Heiko Stuebner 写道:
Hi Yakir,
Am Montag, 24. August 2015, 20:48:01 schrieb Yakir Yang:
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00
Hi Krzysztof,
在 2015/8/25 7:49, Krzysztof Kozlowski 写道:
On 24.08.2015 21:48, Yakir Yang wrote:
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob
Hi Thierry,
在 2015/8/25 22:16, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 09:48:01PM +0800, Yakir Yang wrote:
Hi Thierry Rob,
在 2015/8/25 21:27, Rob Herring 写道:
On Tue, Aug 25, 2015 at 4:15 AM, Thierry Reding tred...@nvidia.com wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring
Hi Thierry,
在 2015/8/25 17:58, Thierry Reding 写道:
On Wed, Aug 19, 2015 at 09:50:34AM -0500, Yakir Yang wrote:
[...]
+ -analogix,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
I don't think DT
Hi Thierry,
在 2015/8/25 18:06, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 05:41:19PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
li
ng some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(..);
- Get panel node with remote-endpoint method, and create devicetree binding
for driver. (Heik
, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
C
-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-h
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yaki
Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indica
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6:
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile fail
m>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
Changes in v2: No
Add dt binding documentation for rockchip display port PHY.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (R
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6:
- Simply the co
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes
com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gp
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7:
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8:
- Correct the right document path of display-timing.txt (Heiko)
- Correct the misspell of 'from' to 'frm'. (Heiko)
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and prov
-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of
e new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+
, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the o
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8:
- Fix the mixed spacers on macro definitions. (Hei
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yaki
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8:
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8:
- Modify the commit subject
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit mess
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v9:
- Removed the unused the variable "res" in
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v8: None
Changes in v7:
hout new changes but rebased on the latest kernel again and
again. If you thought those patches is fine, it would be very grateful to
give some ACKs to those changes.
Thanks,
- Yakir
On 10/28/2015 04:15 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controlle
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v10:
- Fix the wrong
Hi Brian,
Thank you for debugging, and fell sorry for the delay reply
On 11/06/2015 07:45 AM, Brian Norris wrote:
Hi,
A few updates:
On Tue, Nov 03, 2015 at 05:13:48PM -0800, Brian Norris wrote:
On Wed, Nov 04, 2015 at 08:48:38AM +0800, Yakir Yang wrote:
On 11/03/2015 12:38 PM, Brian
On 11/01/2015 02:37 AM, Rob Herring wrote:
On Sat, Oct 31, 2015 at 1:42 AM, Yakir Yang <y...@rock-chips.com> wrote:
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebn
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.
On 10/31/2015 12:42 AM, Rob Herring wrote:
On Wed, Oct 28, 2015 at 3:31 AM, Yakir Yang <y...@rock-chips.com> wrote:
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Ack
On 10/31/2015 02:30 PM, Yakir Yang wrote:
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com&
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