[PATCH 32/69] clocksource/drivers/exynos_mct: Fix Kconfig and add COMPILE_TEST option

[Daniel Lezcano]

Let the platform's Kconfig to select the clock instead of having a reverse
dependency from the driver to the platform options.

Add the COMPILE_TEST option for the compilation test coverage. Due to the
non portable 'delay' code, this driver is only compilable on ARM.

Signed-off-by: Daniel Lezcano <daniel.lezc...@linaro.org>
Tested-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
 arch/arm/mach-exynos/Kconfig | 1 +
 drivers/clocksource/Kconfig  | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 3a10f1a..ff10539 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -27,6 +27,7 @@ menuconfig ARCH_EXYNOS
select SRAM
select THERMAL
select MFD_SYSCON
+   select CLKSRC_EXYNOS_MCT
help
  Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
 
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e3ba5b4..2062783 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -231,8 +231,8 @@ config CLKSRC_METAG_GENERIC
  This option enables support for the Meta per-thread timers.
 
 config CLKSRC_EXYNOS_MCT
-   def_bool y if ARCH_EXYNOS
-   depends on !ARM64
+   bool "Exynos multi core timer driver" if COMPILE_TEST
+   depends on ARM
help
  Support for Multi Core Timer controller on Exynos SoCs.
 
-- 
1.9.1

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Re: [PATCH 0/3] cpuidle: avoid module usage in non-modular code

[Daniel Lezcano]

On 12/14/2015 12:57 AM, Paul Gortmaker wrote:

This series of commits is a part of a larger project to ensure
people don't reference modular support functions in non-modular
code.  Overall there was roughly 5k lines of dead code in the
kernel due to this.  So far we've fixed several areas, like tty,
x86, net, ... and we continue to work on other areas.

There are several reasons to not use module support for code that
can never be built as a module, but the big ones are:

  (1) it is easy to accidentally code up unused module_exit and remove code
  (2) it can be misleading when reading the source, thinking it can be
   modular when the Makefile and/or Kconfig prohibit it
  (3) it requires the include of the module.h header file which in turn
  includes nearly everything else.

Fortunately for cpuidle, the changes are largely trivial and change
zero runtime.  All the changes here just remap the modular functions
onto the non-modular ones that they would be remapped onto anyway.

Changes are against linux-next and compile tested on ARM allmodconfig.
I've Cc'd ARM list because all of these are used on ARM, but I'm
thinking these probably can go in via the PM tree.


Acked-by: Daniel Lezcano <daniel.lezc...@linaro.org>


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Re: [PATCH 20/22] clocksource/drivers/exynos_mct: Fix Kconfig and add COMPILE_TEST option

[Daniel Lezcano]

On 11/03/2015 01:59 AM, Krzysztof Kozlowski wrote:

On 03.11.2015 09:30, Krzysztof Kozlowski wrote:

On 02.11.2015 21:56, Daniel Lezcano wrote:

Let the platform's Kconfig to select the clock instead of having a reverse
dependency from the driver to the platform options.


Selecting user-visible symbols is rather discouraged so why not
something like this:

-   def_bool y if ARCH_EXYNOS
-   depends on !ARM64
+   bool "Exynos multi core timer driver"
+   depends on ARCH_EXYNOS || (COMPILE_TEST && ARM)


Nope, that was wrong as we loose auto-select on Exynos. Instead:
-   def_bool y if ARCH_EXYNOS
-   depends on !ARM64
+   bool "Exynos multi core timer driver" if ARM
+   depends on ARCH_EXYNOS || COMPILE_TEST
+   default y if ARCH_EXYNOS

This way we avoid select (which is a reverse dependency for the driver),
have it auto-selectable and compile tested on arm.


I think you misunderstood the patch I sent.

It does two things:

1. Follow the thumb of rule of the current Kconfig format

   - The timer driver is selected by the platform (exynos in this case)
   - User can't select the driver in the menuconfig
   - There is no dependency on the platform except for compilation test

2. Add the COMPILE_TEST

   - User can select the driver for compilation testing. This is for 
allyesconfig when doing compilation test coverage (exynos timer could be 
compiled on other platform). As the delay code is not portable, we have 
to restrict the compilation on the ARM platform, this is why there is 
the dependency on ARM.


I am currently looking at splitting the delay code in order to prevent 
this restriction on this driver and some others drivers.




Add the COMPILE_TEST option for the compilation test coverage. Due to the
non portable 'delay' code, this driver is only compilable on ARM.

Signed-off-by: Daniel Lezcano <daniel.lezc...@linaro.org>
---
  arch/arm/mach-exynos/Kconfig | 1 +
  drivers/clocksource/Kconfig  | 4 ++--
  2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 3a10f1a..ff10539 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -27,6 +27,7 @@ menuconfig ARCH_EXYNOS
select SRAM
select THERMAL
select MFD_SYSCON
+   select CLKSRC_EXYNOS_MCT
help
  Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 916c36d..d829cbe 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -213,8 +213,8 @@ config CLKSRC_METAG_GENERIC
  This option enables support for the Meta per-thread timers.

  config CLKSRC_EXYNOS_MCT
-   def_bool y if ARCH_EXYNOS
-   depends on !ARM64
+   bool "Exynos multi core timer driver" if COMPILE_TEST
+   depends on ARM
help
  Support for Multi Core Timer controller on Exynos SoCs.










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Re: [PATCH 20/22] clocksource/drivers/exynos_mct: Fix Kconfig and add COMPILE_TEST option

[Daniel Lezcano]

On 11/03/2015 11:02 AM, Arnd Bergmann wrote:

On Tuesday 03 November 2015 09:40:02 Daniel Lezcano wrote:

On 11/03/2015 01:59 AM, Krzysztof Kozlowski wrote:

On 03.11.2015 09:30, Krzysztof Kozlowski wrote:

On 02.11.2015 21:56, Daniel Lezcano wrote:

Let the platform's Kconfig to select the clock instead of having a reverse
dependency from the driver to the platform options.


Selecting user-visible symbols is rather discouraged so why not
something like this:

-   def_bool y if ARCH_EXYNOS
-   depends on !ARM64
+   bool "Exynos multi core timer driver"
+   depends on ARCH_EXYNOS || (COMPILE_TEST && ARM)


Nope, that was wrong as we loose auto-select on Exynos. Instead:
-   def_bool y if ARCH_EXYNOS
-   depends on !ARM64
+   bool "Exynos multi core timer driver" if ARM
+   depends on ARCH_EXYNOS || COMPILE_TEST
+   default y if ARCH_EXYNOS

This way we avoid select (which is a reverse dependency for the driver),
have it auto-selectable and compile tested on arm.


I think you misunderstood the patch I sent.

It does two things:

1. Follow the thumb of rule of the current Kconfig format

 - The timer driver is selected by the platform (exynos in this case)
 - User can't select the driver in the menuconfig
 - There is no dependency on the platform except for compilation test

2. Add the COMPILE_TEST

 - User can select the driver for compilation testing. This is for
allyesconfig when doing compilation test coverage (exynos timer could be
compiled on other platform). As the delay code is not portable, we have
to restrict the compilation on the ARM platform, this is why there is
the dependency on ARM.

I am currently looking at splitting the delay code in order to prevent
this restriction on this driver and some others drivers.


I suspect this will come up again in the future. The problem is
really that drivers/clocksource has different rules from almost
everything else, by requiring the platform to 'select' the driver.

The second version that Krzysztof posted is how we handle this in
other driver subsystems, and I would generally prefer it to do this
consistently for everything, but John Stultz has in the past argued
strongly for using 'select' in all clocksource drivers. The reason
is that for each platform we know in advance which driver we want,
and there is never a need for the user to have to select the right
one.


Yes, and I second John in this.



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Re: [PATCH 20/22] clocksource/drivers/exynos_mct: Fix Kconfig and add COMPILE_TEST option

[Daniel Lezcano]

On 11/03/2015 01:01 PM, Krzysztof Kozlowski wrote:

Anyway the patch worked fine and with explanation I can only confirm:


Great ! Thanks Krzysztof for testing.

  -- Daniel

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[PATCH 20/22] clocksource/drivers/exynos_mct: Fix Kconfig and add COMPILE_TEST option

[Daniel Lezcano]

Let the platform's Kconfig to select the clock instead of having a reverse
dependency from the driver to the platform options.

Add the COMPILE_TEST option for the compilation test coverage. Due to the
non portable 'delay' code, this driver is only compilable on ARM.

Signed-off-by: Daniel Lezcano <daniel.lezc...@linaro.org>
---
 arch/arm/mach-exynos/Kconfig | 1 +
 drivers/clocksource/Kconfig  | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 3a10f1a..ff10539 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -27,6 +27,7 @@ menuconfig ARCH_EXYNOS
select SRAM
select THERMAL
select MFD_SYSCON
+   select CLKSRC_EXYNOS_MCT
help
  Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
 
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 916c36d..d829cbe 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -213,8 +213,8 @@ config CLKSRC_METAG_GENERIC
  This option enables support for the Meta per-thread timers.
 
 config CLKSRC_EXYNOS_MCT
-   def_bool y if ARCH_EXYNOS
-   depends on !ARM64
+   bool "Exynos multi core timer driver" if COMPILE_TEST
+   depends on ARM
help
  Support for Multi Core Timer controller on Exynos SoCs.
 
-- 
1.9.1

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[PATCH 6/9] clocksource/drivers/exynos_mct: Use container_of() instead of this_cpu_ptr()

[Daniel Lezcano]

From: Alexey Klimov <alexey.kli...@linaro.org>

Since evt structure is embedded in per-CPU mevt structure it's
definitely faster to use container_of() to get access to mevt
if we have evt (for example as incoming function argument) instead
of more expensive approach with this_cpu_ptr(_mct_tick).
this_cpu_ptr() on per-CPU mevt structure leads to access to cp15
to get cpu id and arithmetic operations.
Container_of() is cheaper since it's just one asm instruction.
This should work if used evt pointer is correct and owned by
local mevt structure.

For example, before this patch set_state_shutdown() looks like:

 4a4:   e92d4010push{r4, lr}
 4a8:   e3004000movwr4, #0
 4ac:   ebfebl  0 
 4b0:   e3003000movwr3, #0
 4b4:   e3404000movtr4, #0
 4b8:   e3403000movtr3, #0
 4bc:   e7933100ldr r3, [r3, r0, lsl #2]
 4c0:   e0844003add r4, r4, r3
 4c4:   e59400c0ldr r0, [r4, #192]  ; 0xc0
 4c8:   ebd4bl  420 
 4cc:   e3a0mov r0, #0
 4d0:   e8bd8010pop {r4, pc}

With this patch:

 4a4:   e92d4010push{r4, lr}
 4a8:   e59000c0ldr r0, [r0, #192]  ; 0xc0
 4ac:   ebdbbl  420 
 4b0:   e3a0mov r0, #0
 4b4:   e8bd8010pop {r4, pc}

Also, for me size of exynos_mct.o decreased from 84588 bytes
to 83956.

Signed-off-by: Alexey Klimov <alexey.kli...@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezc...@linaro.org>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
---
 drivers/clocksource/exynos_mct.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 029f96a..ff44082 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -382,24 +382,28 @@ static void exynos4_mct_tick_start(unsigned long cycles,
 static int exynos4_tick_set_next_event(unsigned long cycles,
   struct clock_event_device *evt)
 {
-   struct mct_clock_event_device *mevt = this_cpu_ptr(_mct_tick);
+   struct mct_clock_event_device *mevt;
 
+   mevt = container_of(evt, struct mct_clock_event_device, evt);
exynos4_mct_tick_start(cycles, mevt);
-
return 0;
 }
 
 static int set_state_shutdown(struct clock_event_device *evt)
 {
-   exynos4_mct_tick_stop(this_cpu_ptr(_mct_tick));
+   struct mct_clock_event_device *mevt;
+
+   mevt = container_of(evt, struct mct_clock_event_device, evt);
+   exynos4_mct_tick_stop(mevt);
return 0;
 }
 
 static int set_state_periodic(struct clock_event_device *evt)
 {
-   struct mct_clock_event_device *mevt = this_cpu_ptr(_mct_tick);
+   struct mct_clock_event_device *mevt;
unsigned long cycles_per_jiffy;
 
+   mevt = container_of(evt, struct mct_clock_event_device, evt);
cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
>> evt->shift);
exynos4_mct_tick_stop(mevt);
-- 
1.9.1

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Re: [RFC PATCH] clocksource: exynos_mct: use container_of() instead of this_cpu_ptr()

[Daniel Lezcano]

On 09/04/2015 01:49 AM, Alexey Klimov wrote:

Since evt structure is embedded in per-CPU mevt structure it's
definitely faster to use container_of() to get access to mevt
if we have evt (for example as incoming function argument) instead
of more expensive approach with this_cpu_ptr(_mct_tick).
this_cpu_ptr() on per-CPU mevt structure leads to access to cp15
to get cpu id and arithmetic operations.
Container_of() is cheaper since it's just one asm instruction.
This should work if used evt pointer is correct and owned by
local mevt structure.

For example, before this patch set_state_shutdown() looks like:

  4a4:  e92d4010push{r4, lr}
  4a8:  e3004000movwr4, #0
  4ac:  ebfebl  0 
  4b0:  e3003000movwr3, #0
  4b4:  e3404000movtr4, #0
  4b8:  e3403000movtr3, #0
  4bc:  e7933100ldr r3, [r3, r0, lsl #2]
  4c0:  e0844003add r4, r4, r3
  4c4:  e59400c0ldr r0, [r4, #192]  ; 0xc0
  4c8:  ebd4bl  420 
  4cc:  e3a0mov r0, #0
  4d0:  e8bd8010pop {r4, pc}

With this patch:

  4a4:  e92d4010push{r4, lr}
  4a8:  e59000c0ldr r0, [r0, #192]  ; 0xc0
  4ac:  ebdbbl  420 
  4b0:  e3a0mov r0, #0
  4b4:  e8bd8010pop {r4, pc}

Also, for me size of exynos_mct.o decreased from 84588 bytes
to 83956.

Signed-off-by: Alexey Klimov 
---


Despite the RFC I applied the patch as it seems simple enough and it has 
been reviewed by Krzysztof.


  -- Daniel


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Re: CPUIdle for Exynos5422 Odroid-XU3/XU4 boards.

[Daniel Lezcano]

On 08/20/2015 08:15 PM, Anand Moon wrote:

Hi Daniel,

On 20 August 2015 at 21:40, Daniel Lezcano daniel.lezc...@free.fr wrote:

On 08/20/2015 12:54 PM, Anand Moon wrote:


Hello Krzysztof/Kukjim,

CPUIdle seen to be not working for Exynos5422 Odroid boards.

Is their any way this feature will be implemented in the future.



Yeah a good willing to fix the bl1. More than one year asking for that !
nooo way !!

Your answer is at the end of
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html




Thanks for the explanation.

I was just referring following the source code.

https://github.com/hardkernel/linux/blob/odroidxu3-3.10.y/arch/arm/mach-exynos/cpuidle-exynos5422.c


Ah, thanks for the pointer. So for my information, is that driver not 
working with the exynos5422 ?



It seem that cpufreq and cpuidle go hand in hand.


At the first glance, there is a dependency with the cluster power state. 
It is not allowed to enter the cluster power down if another subsystem 
deny it. The driver itself is a pack of hacks based on cpuidle legacy 
code and wildly backported from older kernels with arbitrary latency and 
residency values.



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Re: CPUIdle for Exynos5422 Odroid-XU3/XU4 boards.

[Daniel Lezcano]

On 08/20/2015 12:54 PM, Anand Moon wrote:

Hello Krzysztof/Kukjim,

CPUIdle seen to be not working for Exynos5422 Odroid boards.

Is their any way this feature will be implemented in the future.


Yeah a good willing to fix the bl1. More than one year asking for that ! 
nooo way !!


Your answer is at the end of 
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html



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[PATCH 51/74] clockevents/drivers/exynos_mct: Migrate to new 'set-state' interface

[Daniel Lezcano]

From: Viresh Kumar viresh.ku...@linaro.org

Migrate exynos_mct driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.

This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.

Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Viresh Kumar viresh.ku...@linaro.org
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 drivers/clocksource/exynos_mct.c | 85 +++-
 1 file changed, 40 insertions(+), 45 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 4d2330a..029f96a 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -257,15 +257,14 @@ static void exynos4_mct_comp0_stop(void)
exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
 }
 
-static void exynos4_mct_comp0_start(enum clock_event_mode mode,
-   unsigned long cycles)
+static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
 {
unsigned int tcon;
cycle_t comp_cycle;
 
tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
 
-   if (mode == CLOCK_EVT_MODE_PERIODIC) {
+   if (periodic) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
}
@@ -283,38 +282,38 @@ static void exynos4_mct_comp0_start(enum clock_event_mode 
mode,
 static int exynos4_comp_set_next_event(unsigned long cycles,
   struct clock_event_device *evt)
 {
-   exynos4_mct_comp0_start(evt-mode, cycles);
+   exynos4_mct_comp0_start(false, cycles);
 
return 0;
 }
 
-static void exynos4_comp_set_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
+static int mct_set_state_shutdown(struct clock_event_device *evt)
 {
-   unsigned long cycles_per_jiffy;
exynos4_mct_comp0_stop();
+   return 0;
+}
 
-   switch (mode) {
-   case CLOCK_EVT_MODE_PERIODIC:
-   cycles_per_jiffy =
-   (((unsigned long long) NSEC_PER_SEC / HZ * evt-mult) 
 evt-shift);
-   exynos4_mct_comp0_start(mode, cycles_per_jiffy);
-   break;
+static int mct_set_state_periodic(struct clock_event_device *evt)
+{
+   unsigned long cycles_per_jiffy;
 
-   case CLOCK_EVT_MODE_ONESHOT:
-   case CLOCK_EVT_MODE_UNUSED:
-   case CLOCK_EVT_MODE_SHUTDOWN:
-   case CLOCK_EVT_MODE_RESUME:
-   break;
-   }
+   cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt-mult)
+evt-shift);
+   exynos4_mct_comp0_stop();
+   exynos4_mct_comp0_start(true, cycles_per_jiffy);
+   return 0;
 }
 
 static struct clock_event_device mct_comp_device = {
-   .name   = mct-comp,
-   .features   = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-   .rating = 250,
-   .set_next_event = exynos4_comp_set_next_event,
-   .set_mode   = exynos4_comp_set_mode,
+   .name   = mct-comp,
+   .features   = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT,
+   .rating = 250,
+   .set_next_event = exynos4_comp_set_next_event,
+   .set_state_periodic = mct_set_state_periodic,
+   .set_state_shutdown = mct_set_state_shutdown,
+   .set_state_oneshot  = mct_set_state_shutdown,
+   .tick_resume= mct_set_state_shutdown,
 };
 
 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
@@ -390,39 +389,32 @@ static int exynos4_tick_set_next_event(unsigned long 
cycles,
return 0;
 }
 
-static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
-struct clock_event_device *evt)
+static int set_state_shutdown(struct clock_event_device *evt)
+{
+   exynos4_mct_tick_stop(this_cpu_ptr(percpu_mct_tick));
+   return 0;
+}
+
+static int set_state_periodic(struct clock_event_device *evt)
 {
struct mct_clock_event_device *mevt = this_cpu_ptr(percpu_mct_tick);
unsigned long cycles_per_jiffy;
 
+   cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt-mult)
+evt-shift);
exynos4_mct_tick_stop(mevt);
-
-   switch (mode) {
-   case CLOCK_EVT_MODE_PERIODIC:
-   cycles_per_jiffy =
-   (((unsigned long long) NSEC_PER_SEC / HZ * evt-mult) 
 evt-shift);
-   exynos4_mct_tick_start(cycles_per_jiffy, mevt);
-   break;
-
-   case CLOCK_EVT_MODE_ONESHOT:
-   case CLOCK_EVT_MODE_UNUSED:
-   case CLOCK_EVT_MODE_SHUTDOWN:
-   case CLOCK_EVT_MODE_RESUME:
-   break;
-   }
+   exynos4_mct_tick_start(cycles_per_jiffy, mevt

[PATCH 08/74] clockevents/drivers/exynos_mct: Remove unneeded container_of()

[Daniel Lezcano]

From: Alexey Klimov klimov.li...@gmail.com

Patch removes unneeded container_of() macro in exynos4_local_timer_setup().
Instead let's pass mevt pointer to setup and stop functions from
exynos4_mct_cpu_notify() and let them get evt pointer.

Tested on odroid-xu3.

Signed-off-by: Alexey Klimov klimov.li...@gmail.com
Acked-by: Stephen Boyd sb...@codeaurora.org
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
 drivers/clocksource/exynos_mct.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9064ff7..4d2330a 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -442,13 +442,11 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void 
*dev_id)
return IRQ_HANDLED;
 }
 
-static int exynos4_local_timer_setup(struct clock_event_device *evt)
+static int exynos4_local_timer_setup(struct mct_clock_event_device *mevt)
 {
-   struct mct_clock_event_device *mevt;
+   struct clock_event_device *evt = mevt-evt;
unsigned int cpu = smp_processor_id();
 
-   mevt = container_of(evt, struct mct_clock_event_device, evt);
-
mevt-base = EXYNOS4_MCT_L_BASE(cpu);
snprintf(mevt-name, sizeof(mevt-name), mct_tick%d, cpu);
 
@@ -477,8 +475,10 @@ static int exynos4_local_timer_setup(struct 
clock_event_device *evt)
return 0;
 }
 
-static void exynos4_local_timer_stop(struct clock_event_device *evt)
+static void exynos4_local_timer_stop(struct mct_clock_event_device *mevt)
 {
+   struct clock_event_device *evt = mevt-evt;
+
evt-set_mode(CLOCK_EVT_MODE_UNUSED, evt);
if (mct_int_type == MCT_INT_SPI) {
if (evt-irq != -1)
@@ -500,11 +500,11 @@ static int exynos4_mct_cpu_notify(struct notifier_block 
*self,
switch (action  ~CPU_TASKS_FROZEN) {
case CPU_STARTING:
mevt = this_cpu_ptr(percpu_mct_tick);
-   exynos4_local_timer_setup(mevt-evt);
+   exynos4_local_timer_setup(mevt);
break;
case CPU_DYING:
mevt = this_cpu_ptr(percpu_mct_tick);
-   exynos4_local_timer_stop(mevt-evt);
+   exynos4_local_timer_stop(mevt);
break;
}
 
@@ -570,7 +570,7 @@ static void __init exynos4_timer_resources(struct 
device_node *np, void __iomem
goto out_irq;
 
/* Immediately configure the timer on the boot CPU */
-   exynos4_local_timer_setup(mevt-evt);
+   exynos4_local_timer_setup(mevt);
return;
 
 out_irq:
-- 
1.9.1

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Re: [RESEND PATCH v3] clocksource: exynos_mct: fix for sleeping in atomic ctx handling cpu hotplug notif.

[Daniel Lezcano]

On 06/29/2015 11:24 AM, Thomas Gleixner wrote:

On Mon, 29 Jun 2015, Daniel Lezcano wrote:


On 06/26/2015 03:23 PM, Damian Eppel wrote:

This is to fix an issue of sleeping in atomic context when processing
hotplug notifications in Exynos MCT(Multi-Core Timer).
The issue was reproducible on Exynos 3250 (Rinato board) and Exynos 5420
(Arndale Octa board).

Whilst testing cpu hotplug events on kernel configured with DEBUG_PREEMPT
and DEBUG_ATOMIC_SLEEP we get following BUG message, caused by calling
request_irq() and free_irq() in the context of hotplug notification
(which is in this case atomic context).


Applied as a 4.2 fix.

Should it be tagged stable@ ?


I have that one queued in tip/timers/urgent already. Please check my
branches before picking up stuff.


Mmmh, yep. I thought I refreshed my branch. Now I see it.

Thanks for the heads up.

  -- Daniel

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Re: [RESEND PATCH v3] clocksource: exynos_mct: fix for sleeping in atomic ctx handling cpu hotplug notif.

[Daniel Lezcano]

On 06/26/2015 03:23 PM, Damian Eppel wrote:

This is to fix an issue of sleeping in atomic context when processing
hotplug notifications in Exynos MCT(Multi-Core Timer).
The issue was reproducible on Exynos 3250 (Rinato board) and Exynos 5420
(Arndale Octa board).

Whilst testing cpu hotplug events on kernel configured with DEBUG_PREEMPT
and DEBUG_ATOMIC_SLEEP we get following BUG message, caused by calling
request_irq() and free_irq() in the context of hotplug notification
(which is in this case atomic context).


Applied as a 4.2 fix.

Should it be tagged stable@ ?



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Re: [PATCH] clocksource: exynos_mct: remove unneeded container_of()

[Daniel Lezcano]

On 06/21/2015 10:41 PM, Alexey Klimov wrote:

Patch removes unneeded container_of() macro
in exynos4_local_timer_setup(). Instead let's pass mevt pointer
to setup and stop functions from exynos4_mct_cpu_notify()
and let them get evt pointer.

Tested on odroid-xu3.

Signed-off-by: Alexey Klimov klimov.li...@gmail.com
Acked-by: Stephen Boyd sb...@codeaurora.org
---


Applied to my tree for 4.3.

Thanks !

  -- Daniel

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[PATCH 02/11] clocksource/drivers/exynos_mct: Change exynos4_mct_tick_clear return type to void

[Daniel Lezcano]

From: Krzysztof Kozlowski k.kozlow...@samsung.com

Return value of exynos4_mct_tick_clear() was never checked so it can
be safely changed to void.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 drivers/clocksource/exynos_mct.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 83564c9..87c2e55 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -413,7 +413,7 @@ static inline void exynos4_tick_set_mode(enum 
clock_event_mode mode,
}
 }
 
-static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
+static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 {
struct clock_event_device *evt = mevt-evt;
 
@@ -426,12 +426,8 @@ static int exynos4_mct_tick_clear(struct 
mct_clock_event_device *mevt)
exynos4_mct_tick_stop(mevt);
 
/* Clear the MCT tick interrupt */
-   if (readl_relaxed(reg_base + mevt-base + MCT_L_INT_CSTAT_OFFSET)  1) {
+   if (readl_relaxed(reg_base + mevt-base + MCT_L_INT_CSTAT_OFFSET)  1)
exynos4_mct_write(0x1, mevt-base + MCT_L_INT_CSTAT_OFFSET);
-   return 1;
-   } else {
-   return 0;
-   }
 }
 
 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
-- 
1.9.1

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[PATCH 04/11] clocksource/drivers/exynos_mct: Remove old platform mct_init()

[Daniel Lezcano]

From: Krzysztof Kozlowski k.kozlow...@samsung.com

Since commit 228e3023eb04 (Merge tag 'mct-exynos-for-v3.10' of ...) the
mct_init() was superseded by mct_init_dt() and is not referenced
anywhere. Remove it.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 drivers/clocksource/exynos_mct.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 8b2a9fc..935b059 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -560,18 +560,6 @@ out_irq:
free_percpu_irq(mct_irqs[MCT_L0_IRQ], percpu_mct_tick);
 }
 
-void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
-{
-   mct_irqs[MCT_G0_IRQ] = irq_g0;
-   mct_irqs[MCT_L0_IRQ] = irq_l0;
-   mct_irqs[MCT_L1_IRQ] = irq_l1;
-   mct_int_type = MCT_INT_SPI;
-
-   exynos4_timer_resources(NULL, base);
-   exynos4_clocksource_init();
-   exynos4_clockevent_init();
-}
-
 static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
 {
u32 nr_irqs, i;
-- 
1.9.1

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[PATCH 03/11] clocksource/drivers/exynos_mct: Staticize struct clocksource

[Daniel Lezcano]

From: Krzysztof Kozlowski k.kozlow...@samsung.com

The struct clocksource 'mct_frc' is not exported and used outside so
make it static.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 drivers/clocksource/exynos_mct.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 87c2e55..8b2a9fc 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -209,7 +209,7 @@ static void exynos4_frc_resume(struct clocksource *cs)
exynos4_mct_frc_start();
 }
 
-struct clocksource mct_frc = {
+static struct clocksource mct_frc = {
.name   = mct-frc,
.rating = 400,
.read   = exynos4_frc_read,
-- 
1.9.1

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Re: [PATCH v2] clocksource: exynos_mct: fix for sleeping in atomic ctx handling cpu hotplug notif.

[Daniel Lezcano]

On 05/25/2015 05:24 PM, Damian Eppel wrote:

On Mon, 2015-05-11 at 13:18 +0200, Daniel Lezcano wrote:


[ ... ]


The code sounds very complex for what it is supposed to do.

Perhaps I am missing something but you have more or less the same
functionality than the smp_twd timers and these ones don't look so complex.

Could you please look at the smp_twd.c implementation ?


Hi Daniel,

exynos_mct.c driver looks more complex as it supports two types of timer
interrupts - private and shared peripheral interrupts (for exynos4412
and exynos4210 accordingly). In smp_twd.c driver I can see only PPI type
of irqs supported. SPI and PPI irqs differs slightly in setup - thus two
different code paths appears in the driver in initialization and
handling of CPU notifications. The fix is addressing issue that appears
only for hardware using SPI irqs so it is hard to compare it to
smp_twd.c.
BTW, If we remove support for SPI irqs in exynos_mct.c it would look
almost the same as smp_twd.c.


Ok, thanks.

I will have a deeper look this afternoon.

  -- Daniel


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Re: PROBLEM: BUG appearing when trying to allocate interrupt on Exynos MCT after CPU hotplug

[Daniel Lezcano]

On 01/31/2015 02:08 AM, Stephen Boyd wrote:

Kept meaning to get back to this thread. Have you resolved it?

On 10/29/14 03:38, Marcin Jabrzyk wrote:

So I've tried this patch, it resolves one problem but introduces also
new ones. As expected the BUG warning is not showing after applying
this patch but there are some interesting side effects.


Well that's half good news.


I was looking on /proc/interrupts output. IRQ for CPU0 have MCT name
and IRQ for CPU1 has unexpectedly no name at all.


This is pretty confusing. I don't see how the patch could cause this to
happen.


After making hotplug cycle of CPU1 I've observed that IRQs attached
originally for that CPU are generating on really low count and not in
order with IRQ for CPU0.
What's more the interrupt for CPU1 is showing to me as being counted
for both CPUs, so it's probably not being attached to CPU1.



yeah. Can you give the output of /proc/timer_list in addition to
/proc/interrupts? It may give some hints on what's going on. It may also
be interesting to see if irq_force_affinity() is failing. Please check
the return value and print an error


Hi Stephen, Marcin,

can you have a look if the patch [1] fixes this issue ?

 -- Daniel

[1] https://lkml.org/lkml/2015/1/30/423



diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 1800053b4644..3c4538e26731 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -450,6 +450,7 @@ static int exynos4_local_timer_setup(struct 
clock_event_device *evt)
  {
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
+   int ret;

mevt = container_of(evt, struct mct_clock_event_device, evt);

@@ -468,7 +469,9 @@ static int exynos4_local_timer_setup(struct 
clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
evt-irq = mct_irqs[MCT_L0_IRQ + cpu];
enable_irq(evt-irq);
-   irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
+   ret = irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], 
cpumask_of(cpu));
+   if (ret)
+   pr_err(force failed %d\n, ret);
} else {
enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}




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Re: [RESEND PATCH v3] clocksource: exynos_mct: Add the support for Exynos 64bit SoC

[Daniel Lezcano]

On 01/14/2015 04:51 PM, Kukjin Kim wrote:

On 01/14/15 14:33, Chanwoo Choi wrote:

Hi,

+ Doug, Olof


This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for Exynos 32bit SoC.


Yes, the Exynos MCT(Multi-Core Timer) is 64bit timer and it is available
on 64bit exynos SoC such as exynos7. But basically ARMv8 architecture is
including ARM ARCH timer (ARM Generic Timer) and exynos7 also has
implemented it and additionally its access is faster than using memory
mapped register called SFR for MCT...so Doug submitted patch to use MCT
on 32bit exynos SoCs before.

I know using MCT on 64bit exynos is usefulness for Power Management and
I need to talk to relevant guys in office again. If anything, I'll let
you know.


I will wait for your answer before digging more the patch.

Thanks
  -- Daniel


Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
This patch set is tested on 64-bit Exynos SoC. I send only this patch from
following patchst[1].
[1] https://lkml.org/lkml/2014/12/2/134

Changes from v2:
- None
Changes from v1:
- Use CONFIG_ARM instead of CONFIG_ARM64

  drivers/clocksource/Kconfig  | 1 -
  drivers/clocksource/exynos_mct.c | 4 
  2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index fc01ec2..be38119 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -135,7 +135,6 @@ config CLKSRC_METAG_GENERIC

  config CLKSRC_EXYNOS_MCT
def_bool y if ARCH_EXYNOS
-   depends on !ARM64
help
  Support for Multi Core Timer controller on Exynos SoCs.

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9403061..b840ea1 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
return exynos4_read_count_32();
  }

+#if defined(CONFIG_ARM)
  static struct delay_timer exynos4_delay_timer;

  static cycles_t exynos4_read_current_timer(void)
@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
 cycles_t needs to move to 32-bit for ARM64 usage);
return exynos4_read_count_32();
  }
+#endif

  static void __init exynos4_clocksource_init(void)
  {
exynos4_mct_frc_start();

+#if defined(CONFIG_ARM)
exynos4_delay_timer.read_current_timer = exynos4_read_current_timer;
exynos4_delay_timer.freq = clk_rate;
register_current_timer_delay(exynos4_delay_timer);
+#endif

if (clocksource_register_hz(mct_frc, clk_rate))
panic(%s: can't register clocksource\n, mct_frc.name);



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Re: [PATCH] cpuidle: add MAINTAINERS entry for ARM Exynos cpuidle driver

[Daniel Lezcano]

On 12/03/2014 01:08 AM, Rafael J. Wysocki wrote:

On Tuesday, December 02, 2014 04:41:35 PM Bartlomiej Zolnierkiewicz wrote:

Since there has been quite a lot of development going on for
ARM Exynos cpuidle driver recently I would like to add separate
MAINTAINERS entry for it and add myself as the primary maintainer.

The merging process would remain (almost) unchanged with patches
going (with my Ack) through Daniel's or Kukjin's tree.

Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com


Daniel, do you want me to apply this, or are you going to do that?


Please apply it.

Thanks !
 -- Daniel


---
  MAINTAINERS |   10 ++
  1 file changed, 10 insertions(+)

Index: b/MAINTAINERS
===
--- a/MAINTAINERS   2014-11-27 18:02:51.988225868 +0100
+++ b/MAINTAINERS   2014-12-02 15:56:52.792997513 +0100
@@ -2701,6 +2701,16 @@ T:   git git://git.kernel.org/pub/scm/linu
  S:Maintained
  F:drivers/cpuidle/cpuidle-big_little.c

+CPUIDLE DRIVER - ARM EXYNOS
+M: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
+M: Daniel Lezcano daniel.lezc...@linaro.org
+M: Kukjin Kim kg...@kernel.org
+L: linux...@vger.kernel.org
+L: linux-samsung-soc@vger.kernel.org
+S: Supported
+F: drivers/cpuidle/cpuidle-exynos.c
+F: arch/arm/mach-exynos/pm.c
+
  CPUIDLE DRIVERS
  M:Rafael J. Wysocki r...@rjwysocki.net
  M:Daniel Lezcano daniel.lezc...@linaro.org

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Re: [PATCH] clocksource: exynos_mct: fix exynos4_mct_write

[Daniel Lezcano]

On 11/29/2014 11:18 PM, Kukjin Kim wrote:

Tobias Jakobi wrote:


EXYNOS4_MCT_L_MASK is defined as 0xff00, so applying this bitmask
produces a number outside the range 0x00 to 0xff, which always results
in execution of the default switch statement.

Obviously this is wrong and git history shows that the bitmask inversion
was incorrectly set during a refactoring of the MCT code.

Fix this by putting the inversion at the correct position again.

Reported-by: GP Orcullo kinsama...@gmail.com
Signed-off-by: Tobias Jakobi tjak...@math.uni-bielefeld.de


+ Daniel, Thomas,

adding Doug's review tag from previous his reply.

Reviewed-by: Doug Anderson diand...@chromium.org

And

Acked-by: Kukjin Kim kgene@samsung.com

Daniel,

Since this is obvious fix, can you please pick into your tree?
If any problem, please kindly let me know.


Hi Kukjin,

the patch is my tree for a 3.18 fix.

Added the stable@ also in the Cc list.

Thanks
 -- Daniel


---
  drivers/clocksource/exynos_mct.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9403061..83564c9 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -97,8 +97,8 @@ static void exynos4_mct_write(unsigned int value, unsigned 
long offset)
writel_relaxed(value, reg_base + offset);

if (likely(offset = EXYNOS4_MCT_L_BASE(0))) {
-   stat_addr = (offset  ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
-   switch (offset  EXYNOS4_MCT_L_MASK) {
+   stat_addr = (offset  EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+   switch (offset  ~EXYNOS4_MCT_L_MASK) {
case MCT_L_TCON_OFFSET:
mask = 1  3;/* L_TCON write status */
break;
--
2.0.4





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Re: [PATCH 2/2] cpuidle: exynos: add coupled cpuidle support for Exynos4210

[Daniel Lezcano]

On 11/12/2014 04:13 PM, Bartlomiej Zolnierkiewicz wrote:




Hi Bartlomiej,

[ cut ]


- using arch_send_wakeup_ipi_mask() instead of dsb_sev()
(this matches CPU hotplug code in arch/arm/mach-exynos/platsmp.c)


I am curious. You experienced very rare hangs after running the tests a
few hours, right ? Is the SEV replaced by the IPI solving the issue ? If
yes, how did you catch it ?


Rare hangs showed up after about 30-40 minutes of testing with the attached
app and script (running of ./cpuidle_state1_test.sh script 2 500 has never
completed on the umodified driver).

The problem turned out to be in the following loop waiting for CPU1 to get
stuck in the BOOT ROM:

/*
 * Wait for cpu1 to get stuck in the boot rom
 */
while ((__raw_readl(BOOT_VECTOR) != 0) 
   !atomic_read(cpu1_wakeup))
cpu_relax();

[ Removal of the loop fixed the problem. ]


Just for my personal information, do you know why ?


Using the SEV instead of the IPI was not a issue but it was changed to
match the existing Exynos platform code (exynos_boot_secondary() in
arch/arm/mach-exynos/platsmp.c) and as preparation for Exynos4412 (quad
core) support.


Ah, ok. Thanks for the info.

[ cut ]


+#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
+   if (of_machine_is_compatible(samsung,exynos4210))
+   exynos_cpuidle.dev.platform_data = cpuidle_coupled_exynos_data;
+#endif


You should not add those #ifdef.


Without those #ifdef I get:

   LD  init/built-in.o
arch/arm/mach-exynos/built-in.o: In function `exynos_dt_machine_init':
/home/bzolnier/sam/linux-sprc/arch/arm/mach-exynos/exynos.c:334: undefined 
reference to `cpuidle_coupled_exynos_data'
make: *** [vmlinux] Error 1

when CONFIG_EXYNOS_CPU_SUSPEND is disabled.


Here, we are introducing some dependencies I tried to drop in the 
different drivers.


I looked more closely at the code and especially the 
'cpuidle_coupled_exynos_data'. I don't think it is worth to have it 
because it adds more complexity and you have to define this structure to 
be visible from the drivers/cpuidle files.


I suggest you create an simple function in pm.c

int exynos_coupled_aftr(int cpu)
{
pre_enter...

if (!cpu)
cpu0_enter_aftr()
else
cpu1_powerdown()

post_enter...
}

and in the cpuidle driver itself, you just use the already existing 
anonymous callback 'exynos_enter_aftr' (and mutate it to conform the 
parameters).


You won't have to share any structure between the arch code and the 
cpuidle driver.




if (of_machine_is_compatible(samsung,exynos4210) ||
of_machine_is_compatible(samsung,exynos4212) ||
(of_machine_is_compatible(samsung,exynos4412) 
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c


[ cut ]


-   exynos_enter_aftr = (void *)(pdev-dev.platform_data);
+   if (of_machine_is_compatible(samsung,exynos4210)) {
+   exynos_cpuidle_pdata = pdev-dev.platform_data;
+
+   exynos_idle_driver.states[1].enter =
+   exynos_enter_coupled_lowpower;
+   exynos_idle_driver.states[1].exit_latency = 5000;
+   exynos_idle_driver.states[1].target_residency = 1;
+   exynos_idle_driver.states[1].flags |= CPUIDLE_FLAG_COUPLED |
+ CPUIDLE_FLAG_TIMER_STOP;


I tried to remove those dynamic state allocation everywhere in the
different drivers. I would prefer to have another cpuidle_driver to be
registered with its states instead of overwriting the existing idle state.

struct cpuidle_driver exynos4210_idle_driver = {
.name = exynos4210_idle,
.owner = THIS_MODULE,
.states = {
[0] = ARM_CPUIDLE_WFI_STATE,
  [1] = {
  .enter = exynos_enter_coupled_lowpower,
  .exit_latency = 5000,
  .target_residency = 1,
.flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_COUPLED |
CPUIDLE_FLAG_TIMER_STOP,
  .name = C1,
  .desc = ARM power down,
  },
}
};


and then:

if (of_machine_is_compatible(samsung,exynos4210)) {
...
ret = cpuidle_register(exynos4210_idle_driver,
cpu_online_mask);
...
}
...


OK, I will fix it but (if you are OK with it) I will make the code use
exynos_coupled naming instead of exynos4210 one to not have to change
it later.


If we can reuse this mechanism, which I believe it is possible to, for
4420 and 5250. Then we will be able to refactor this out again.


Ok, sounds good.


I plan to add support for Exynos3250 next as it should be the simplest
(it is also dual core) 

Re: [PATCH 2/2] cpuidle: exynos: add coupled cpuidle support for Exynos4210

[Daniel Lezcano]

On 11/07/2014 07:00 PM, Bartlomiej Zolnierkiewicz wrote:

The following patch adds coupled cpuidle support for Exynos4210 to
an existing cpuidle-exynos driver.  As a result it enables AFTR mode
to be used by default on Exynos4210 without the need to hot unplug
CPU1 first.

The patch is heavily based on earlier cpuidle-exynos4210 driver from
Daniel Lezcano:

http://www.spinics.net/lists/linux-samsung-soc/msg28134.html

Changes from Daniel's code include:
- porting code to current kernels
- fixing it to work on my setup (by using S5P_INFORM register
   instead of S5P_VA_SYSRAM one on Revison 1.1 and retrying poking
   CPU1 out of the BOOT ROM if necessary)
- fixing rare lockup caused by waiting for CPU1 to get stuck in
   the BOOT ROM (CPU hotplug code in arch/arm/mach-exynos/platsmp.c
   doesn't require this and works fine)
- moving Exynos specific code to arch/arm/mach-exynos/pm.c
- using cpu_boot_reg_base() helper instead of BOOT_VECTOR macro
- using exynos_cpu_*() helpers instead of accessing registers
   directly
- using arch_send_wakeup_ipi_mask() instead of dsb_sev()
   (this matches CPU hotplug code in arch/arm/mach-exynos/platsmp.c)


I am curious. You experienced very rare hangs after running the tests a 
few hours, right ? Is the SEV replaced by the IPI solving the issue ? If 
yes, how did you catch it ?



- integrating separate exynos4210-cpuidle driver into existing
   exynos-cpuidle one

Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Colin Cross ccr...@google.com
Cc: Kukjin Kim kgene@samsung.com
Cc: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com


Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org

A few comments below:


Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
  arch/arm/mach-exynos/common.h|   4 +
  arch/arm/mach-exynos/exynos.c|   4 +
  arch/arm/mach-exynos/platsmp.c   |   2 +-
  arch/arm/mach-exynos/pm.c| 122 +++
  drivers/cpuidle/Kconfig.arm  |   1 +
  drivers/cpuidle/cpuidle-exynos.c |  62 --
  include/linux/platform_data/cpuidle-exynos.h |  20 +
  7 files changed, 209 insertions(+), 6 deletions(-)
  create mode 100644 include/linux/platform_data/cpuidle-exynos.h

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index d4d09bc..f208a60 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -14,6 +14,7 @@

  #include linux/reboot.h
  #include linux/of.h
+#include linux/platform_data/cpuidle-exynos.h

  #define EXYNOS3250_SOC_ID 0xE3472000
  #define EXYNOS3_SOC_MASK  0xF000
@@ -168,8 +169,11 @@ extern void exynos_pm_central_suspend(void);
  extern int exynos_pm_central_resume(void);
  extern void exynos_enter_aftr(void);

+extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
+
  extern void s5p_init_cpu(void __iomem *cpuid_addr);
  extern unsigned int samsung_rev(void);
+extern void __iomem *cpu_boot_reg_base(void);

  static inline void pmu_raw_writel(u32 val, u32 offset)
  {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index a487e59..4f4eb9e 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -317,6 +317,10 @@ static void __init exynos_dt_machine_init(void)
if (!IS_ENABLED(CONFIG_SMP))
exynos_sysram_init();

+#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
+   if (of_machine_is_compatible(samsung,exynos4210))
+   exynos_cpuidle.dev.platform_data = cpuidle_coupled_exynos_data;
+#endif


You should not add those #ifdef.


if (of_machine_is_compatible(samsung,exynos4210) ||
of_machine_is_compatible(samsung,exynos4212) ||
(of_machine_is_compatible(samsung,exynos4412) 
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index adb36a8..0e3ffc9 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -182,7 +182,7 @@ int exynos_cluster_power_state(int cluster)
S5P_CORE_LOCAL_PWR_EN);
  }

-static inline void __iomem *cpu_boot_reg_base(void)
+void __iomem *cpu_boot_reg_base(void)
  {
if (soc_is_exynos4210()  samsung_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM5;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 4b36ab5..44cc08a 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -178,3 +178,125 @@ void exynos_enter_aftr(void)

cpu_pm_exit();
  }
+
+static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
+
+static int exynos_cpu0_enter_aftr(void)
+{
+   int ret = -1;
+
+   /*
+* If the other cpu is powered on, we have to power it off, because
+* the AFTR state won't work otherwise
+*/
+   if (cpu_online(1)) {
+   /*
+* We reach a sync point

Re: [PATCH v3] ARM: dts: add CPU nodes for Exynos4 SoCs

[Daniel Lezcano]

On 09/25/2014 10:17 AM, Lorenzo Pieralisi wrote:

[CC'ed Daniel to make him aware this patch goes through your tree]


Thanks for the head up. I was about to send the PR to Rafael.

[ ... ]


That's great, now my Exynos CPUidle DT patch should be rebased on top
of this patch so that thanks to the testing carried out by Bart it can be
merged too.


Ok, I am getting confused. How can I rebase the latest patch of your 
series with a patch no yet available in my tree ?


I propose just to drop the last patch and wait for the next merge to 
reintegrate it into the cpuidle tree. Does it make sense ?


Thanks
  -- Daniel


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Re: [PATCH v3] ARM: dts: add CPU nodes for Exynos4 SoCs

[Daniel Lezcano]

On 09/25/2014 11:36 AM, Lorenzo Pieralisi wrote:

On Thu, Sep 25, 2014 at 10:02:05AM +0100, Daniel Lezcano wrote:

On 09/25/2014 10:17 AM, Lorenzo Pieralisi wrote:

[CC'ed Daniel to make him aware this patch goes through your tree]


Thanks for the head up. I was about to send the PR to Rafael.

[ ... ]


That's great, now my Exynos CPUidle DT patch should be rebased on top
of this patch so that thanks to the testing carried out by Bart it can be
merged too.


Ok, I am getting confused. How can I rebase the latest patch of your
series with a patch no yet available in my tree ?


I just wanted to say that the Exynos CPUidle DT patch depends on this
patch, that is now going through Samsung tree, to make sure we are on
the same page and prevent issues, it was not clear, sorry.


Ah, ok.


I propose just to drop the last patch and wait for the next merge to
reintegrate it into the cpuidle tree. Does it make sense ?


I agree, drop the Exynos CPUidle DT patch, we will reintegrate it in the
CPUidle tree when the merge window closes and dependencies are sorted out.


Perfect. I sent the PR to Rafael.

Thanks

  -- Daniel


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Re: [PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

[Daniel Lezcano]

On 08/14/2014 12:55 PM, Bartlomiej Zolnierkiewicz wrote:


Hi,

On Monday, July 21, 2014 01:06:32 PM Daniel Lezcano wrote:

On 07/16/2014 07:34 PM, Bartlomiej Zolnierkiewicz wrote:


Hi,

On Friday, May 30, 2014 03:53:09 PM Bartlomiej Zolnierkiewicz wrote:


Hi,

On Friday, May 30, 2014 01:34:45 PM Tomasz Figa wrote:

Hi Daniel,

On 30.05.2014 11:30, Daniel Lezcano wrote:

On 04/24/2014 07:42 PM, Tomasz Figa wrote:

Hi Daniel,

Please see my comments inline.

Btw. Please fix your e-mail composer to properly wrap your messages
around 7xth column, as otherwise they're hard to read.

On 04.04.2014 11:48, Daniel Lezcano wrote:

The following driver is for exynos4210. I did not yet finished the
other boards, so
I created a specific driver for 4210 which could be merged later.

The driver is based on Colin Cross's driver found at:

https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9a4dfa3b393a010%5E%5E!/



This one was based on a 3.4 kernel and an old API.

It has been refreshed, simplified and based on the recent code cleanup
I sent
today.

The AFTR could be entered when all the cpus (except cpu0) are down. In
order to
reach this situation, the couple idle states are used.

There is a sync barrier at the entry and the exit of the low power
function. So
all cpus will enter and exit the function at the same time.

At this point, CPU0 knows the other cpu will power down itself. CPU0
waits for
the CPU1 to be powered down and then initiate the AFTR power down
sequence.

No interrupts are handled by CPU1, this is why we switch to the timer
broadcast
even if the local timer is not impacted by the idle state.

When CPU0 wakes up, it powers up CPU1 and waits for it to boot. Then
they both
exit the idle function.

This driver allows the exynos4210 to have the same power consumption
at idle
time than the one when we have to unplug CPU1 in order to let CPU0 to
reach
the AFTR state.

This patch is a RFC because, we have to find a way to remove the macros
definitions and cpu powerdown function without pulling the arch
dependent
headers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
arch/arm/mach-exynos/common.c|   11 +-
drivers/cpuidle/Kconfig.arm  |8 ++
drivers/cpuidle/Makefile |1 +
drivers/cpuidle/cpuidle-exynos4210.c |  226
++


[ ... ]



Otherwise, I quite like the whole idea. I need to play a bit with CPU
hotplug and PMU to verify that things couldn't really be simplified a
bit, but in general this looks reasonably.


Hi Tomasz,

did you have time to look at this simplification ?


Unfortunately I got preempted with other things to do and now I'm on
vacation. I worked a bit with Bart (added on CC) on this and generally
the conclusion was that all the things are necessary. He was also
working to extend the driver to support Exynos4x12.

Bart, has anything interesting showed up since we talked about this last
time?


Since we last looked into this I have fixed the standard AFTR support
for Exynos3250 and started to work on adding Exynos3250 support to this
driver (as Exynos3250 support has bigger priority than Exynos4x12 one).
Unfortunately I also got preempted with other things so it is still
unfinished and doesn't work yet.  Moreover I had no possibility to test
the new driver on Exynos4210 based Origen yet (I hope to do this next
week).


I have tested this patch on Origen board (Exynos4210 rev 1.1) and it
causes system lockup (it seems that the code gets stuck on waiting for
CPU1 to wake up).

The kernels I have tried:
* current -next + this patch + few fixes to bring it up to date
* commit cd245f5 + this patch + some fixes
* next-20140403 + your Exynos cpuidle patch series + this patch

I have also tried with S5P_VA_SYSRAM replaced by S5P_INFORM5 to
match Exynos 4210 rev 1.1 but it didn't help.

U-Boot version used is:
U-Boot 2012.07 (Sep 22 2012 - 05:12:41) for ORIGEN

Could you please tell me which hardware/bootloader/kernel exactly
have you used to test this patch?


When I used it, it was on top of 3.15-rc1:

https://git.linaro.org/people/daniel.lezcano/linux.git/shortlog/refs/heads/cpuidle/samsung-next

The hardware was a exynos-4210 origen board ver A.


I need the following patch to make this driver work on my hardware.


Thanks for the patch !


[ Unfortunately even with this patch the driver doesn't work reliably.
   After 30-40 minutes of stress testing it lockups the system (I can
   send you testing app+script if needed). ]


Yes, please. I will try to reproduce it.


Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics


From: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Subject: [PATCH] cpuidle: Exynos4210: make coupled driver work on Revision 1.1

* Add static inline helper cpu_boot_reg_base() and use it instead of
   BOOT_VECTOR macro.

* Use S5P_INFORM register instead of S5P_VA_SYSRAM one on Revison 1.1
   (this matches platform

Re: [PATCH v2 1/3] ARM: EXYNOS: Fix build with PM_SLEEP=n and ARM_EXYNOS_CPUIDLE=n

[Daniel Lezcano]

On 08/12/2014 05:11 PM, Bartlomiej Zolnierkiewicz wrote:

Fix building of exynos_defconfig with disabled CONFIG_PM_SLEEP by
adding checking whether Exynos cpuidle support is enabled before
accessing exynos_enter_aftr.

The build error message:
arch/arm/mach-exynos/built-in.o:(.data+0x74): undefined reference to 
`exynos_enter_aftr'
make: *** [vmlinux] Error 1



This patch has been tested on Exynos4210 based Origen board.

Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
  arch/arm/mach-exynos/exynos.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6a24e11..d57f136 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -161,7 +161,9 @@ static void exynos_restart(enum reboot_mode mode, const 
char *cmd)

  static struct platform_device exynos_cpuidle = {
.name  = exynos_cpuidle,
+#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
.dev.platform_data = exynos_enter_aftr,
+#endif
.id= -1,
  };


This patch does not address the real issue of the compilation error. The 
cpuidle driver needs the exynos_enter_aftr function in order to work 
correctly. Hence the Makefile should be fixed in order to compile pm.o 
if cpuidle or pm_sleep are set.



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Re: [PATCH v3 0/4] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled

[Daniel Lezcano]

On 08/05/2014 02:04 PM, Bartlomiej Zolnierkiewicz wrote:


Hi Daniel,

On Monday, July 28, 2014 09:43:02 AM Daniel Lezcano wrote:

On 07/09/2014 07:17 PM, Bartlomiej Zolnierkiewicz wrote:

Hi,

This patch series adds support for AFTR idle mode on boards with
secure firmware enabled and allows EXYNOS cpuidle driver usage on
Exynos4x12 SoCs.

It has been tested on Trats2 board (using Exynos4412 SoC with secure
firmware enabled) on which AFTR mode reduces power consumption by ~12%
when EXYNOS cpuidle driver is enabled (in both cases the default
exynos_defconfig config is used and CPU1-3 are offlined).



Hi Bartlomiej,

what is the status of this patchset ? Is it supposed to land for 3.17 ?


I posted v4 yesterday:
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35197.html

When it comes to merging the patchset for 3.17 it is up to Kukjin.


Ok, thanks for the sync up.

  -- Daniel


Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics


Thanks

-- Daniel


v3:
- rebased on top of next-20140708 +
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html
(with rejects fixed)
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32808.html
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32991.html
(with rejects fixed in patch #2)
- addressed review comments from Tomasz Figa and Daniel Lezcano

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics


Bartlomiej Zolnierkiewicz (4):
ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines
ARM: EXYNOS: add AFTR mode support to firmware do_idle method
ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code
ARM: EXYNOS: cpuidle: allow driver usage on Exynos4x12 SoCs

   arch/arm/include/asm/firmware.h  |  2 +-
   arch/arm/mach-exynos/common.h|  7 ++-
   arch/arm/mach-exynos/exynos.c|  3 ++-
   arch/arm/mach-exynos/firmware.c  | 36 ++--
   arch/arm/mach-exynos/pm.c| 39 +--
   drivers/cpuidle/cpuidle-exynos.c |  6 +++---
   6 files changed, 67 insertions(+), 26 deletions(-)





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Re: [PATCH v5 0/5] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled

[Daniel Lezcano]

On 08/05/2014 03:34 PM, Bartlomiej Zolnierkiewicz wrote:

Hi,

This patch series adds support for AFTR idle mode on boards with
secure firmware enabled and allows EXYNOS cpuidle driver usage on
Exynos4x12 SoCs.

It has been tested on Trats2 board (using Exynos4412 SoC with secure
firmware enabled) on which AFTR mode reduces power consumption by ~12%
when EXYNOS cpuidle driver is enabled (in both cases the default
exynos_defconfig config is used and CPU1-3 are offlined).


Hi Bartlomiej,

I tested your patchset on an odroid-u2. When the cpuidle driver is 
enabled and the cpu1-3 are offlined, the kernel hangs.


If I disable the AFTR state on cpuidle, and offline the 1-3, it works as 
expected. So there is something wrong with the AFTR on the odroid board.



Depends on:
- next-20140804 branch of linux-next kernel tree
- [PATCH v5][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35262.html)
- [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html)

Changes since v4:
- rebased on top of next-20140804 +
   [PATCH v5][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35262.html)
   [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html)
- call exynos_save_cp15() only on A9 type core (this is needed for the future
   Exynos3250 SoC support)

Changes since v3:
- rebased on top of next-20140804 +
   [PATCH v4][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35192.html)
   [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html)
- (re-)added patch fixing S5P_CENTRAL_SEQ_OPTION register setup

Changes since v2:
- rebased on top of next-20140708 +
   [PATCH 5/6] ARM: EXYNOS: Fix suspend/resume sequencies
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html)
   [with rejects fixed]
   [PATCH 6/6] ARM: EXYNOS: Register cpuidle device only on Exynos4210 and 5250
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32808.html)
   [PATCH 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32991.html)
   [with rejects fixed in patch #2]
- addressed review comments from Tomasz Figa and Daniel Lezcano

Changes since v1:
- synced against next-20140602
- added missing Acked-by-s

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics


Bartlomiej Zolnierkiewicz (5):
   ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines
   ARM: EXYNOS: add AFTR mode support to firmware do_idle method
   ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code
   ARM: EXYNOS: PM: fix register setup for AFTR mode code
   ARM: EXYNOS: cpuidle: allow driver usage on Exynos4x12 SoCs

  arch/arm/include/asm/firmware.h |  2 +-
  arch/arm/mach-exynos/common.h   |  5 
  arch/arm/mach-exynos/exynos.c   |  4 ++-
  arch/arm/mach-exynos/firmware.c | 34 ---
  arch/arm/mach-exynos/pm.c   | 60 -
  5 files changed, 70 insertions(+), 35 deletions(-)




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Re: [PATCH v5 0/5] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled

[Daniel Lezcano]

On 08/05/2014 03:34 PM, Bartlomiej Zolnierkiewicz wrote:

Hi,

This patch series adds support for AFTR idle mode on boards with
secure firmware enabled and allows EXYNOS cpuidle driver usage on
Exynos4x12 SoCs.

It has been tested on Trats2 board (using Exynos4412 SoC with secure
firmware enabled) on which AFTR mode reduces power consumption by ~12%
when EXYNOS cpuidle driver is enabled (in both cases the default
exynos_defconfig config is used and CPU1-3 are offlined).


As a sidenote:

On my odroid-U2:
 * 4 cpus online - 130 mA
 * 3 cpus online - 164 mA
 * 2 cpus online - 160 mA
 * 1 cpu online  - 157 mA

So were are consuming more when there are unplugged cpu ... any ideas ?

Thanks !

  -- Daniel


Depends on:
- next-20140804 branch of linux-next kernel tree
- [PATCH v5][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35262.html)
- [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html)

Changes since v4:
- rebased on top of next-20140804 +
   [PATCH v5][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35262.html)
   [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html)
- call exynos_save_cp15() only on A9 type core (this is needed for the future
   Exynos3250 SoC support)

Changes since v3:
- rebased on top of next-20140804 +
   [PATCH v4][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35192.html)
   [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html)
- (re-)added patch fixing S5P_CENTRAL_SEQ_OPTION register setup

Changes since v2:
- rebased on top of next-20140708 +
   [PATCH 5/6] ARM: EXYNOS: Fix suspend/resume sequencies
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html)
   [with rejects fixed]
   [PATCH 6/6] ARM: EXYNOS: Register cpuidle device only on Exynos4210 and 5250
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32808.html)
   [PATCH 0/2] Firmware-assisted suspend/resume of Exynos SoCs
   (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32991.html)
   [with rejects fixed in patch #2]
- addressed review comments from Tomasz Figa and Daniel Lezcano

Changes since v1:
- synced against next-20140602
- added missing Acked-by-s

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics


Bartlomiej Zolnierkiewicz (5):
   ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines
   ARM: EXYNOS: add AFTR mode support to firmware do_idle method
   ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code
   ARM: EXYNOS: PM: fix register setup for AFTR mode code
   ARM: EXYNOS: cpuidle: allow driver usage on Exynos4x12 SoCs

  arch/arm/include/asm/firmware.h |  2 +-
  arch/arm/mach-exynos/common.h   |  5 
  arch/arm/mach-exynos/exynos.c   |  4 ++-
  arch/arm/mach-exynos/firmware.c | 34 ---
  arch/arm/mach-exynos/pm.c   | 60 -
  5 files changed, 70 insertions(+), 35 deletions(-)




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Re: [PATCH v5 1/3] ARM: EXYNOS: Move code from hotplug.c to platsmp.c

[Daniel Lezcano]

On 08/05/2014 12:43 PM, Krzysztof Kozlowski wrote:

Cleanup a little the SMP/hotplug code for Exynos by:
1. Moving completely all functions from hotplug.c into the platsmp.c;
2. Deleting the hotplug.c file.

After recent cleanups (e.g. 75ad2ab28f0f ARM: EXYNOS: use
v7_exit_coherency_flush macro for cache disabling) there was only CPU
power down related code in hotplug.c file. Keeping this file does not
give any benefits.

The commit only moves code around with one additional observable change:
the hotplug.c was compiled with custom CFLAGS (-march=armv7-a). These
CFLAGS are not necessary any more.


What is the benefit of moving this code around ?

Usually the cpu hotplug code is located in hotplug.c for most of the 
platforms, so why moving pm code inside platsmp ?



Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com

---
Changes since v4:
1. Rebase on linux-next-20140804.
2. Add Reviewed-by Tomasz Figa.
---
  arch/arm/mach-exynos/Makefile  |  3 --
  arch/arm/mach-exynos/common.h  |  2 -
  arch/arm/mach-exynos/hotplug.c | 91 --
  arch/arm/mach-exynos/platsmp.c | 74 ++
  4 files changed, 74 insertions(+), 96 deletions(-)
  delete mode 100644 arch/arm/mach-exynos/hotplug.c

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 788f26d21141..0095de99d703 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -21,9 +21,6 @@ obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o

  obj-$(CONFIG_SMP) += platsmp.o headsmp.o

-obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
-CFLAGS_hotplug.o   += -march=armv7-a
-
  plus_sec := $(call as-instr,.arch_extension sec,+sec)
  AFLAGS_exynos-smc.o   :=-Wa,-march=armv7-a$(plus_sec)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 47b904b3b973..3d3e6af9d015 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -130,8 +130,6 @@ extern void exynos_cpu_resume(void);

  extern struct smp_operations exynos_smp_ops;

-extern void exynos_cpu_die(unsigned int cpu);
-
  /* PMU(Power Management Unit) support */

  #define PMU_TABLE_END (-1U)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
deleted file mode 100644
index 4d86961a7957..
--- a/arch/arm/mach-exynos/hotplug.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *  Cloned from linux/arch/arm/mach-realview/hotplug.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/kernel.h
-#include linux/errno.h
-#include linux/smp.h
-#include linux/io.h
-
-#include asm/cacheflush.h
-#include asm/cp15.h
-#include asm/smp_plat.h
-
-#include common.h
-#include regs-pmu.h
-
-static inline void cpu_leave_lowpower(void)
-{
-   unsigned int v;
-
-   asm volatile(
-   mrc   p15, 0, %0, c1, c0, 0\n
- orr %0, %0, %1\n
- mcr p15, 0, %0, c1, c0, 0\n
- mrc p15, 0, %0, c1, c0, 1\n
- orr %0, %0, %2\n
- mcr p15, 0, %0, c1, c0, 1\n
- : =r (v)
- : Ir (CR_C), Ir (0x40)
- : cc);
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-   u32 mpidr = cpu_logical_map(cpu);
-   u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-
-   for (;;) {
-
-   /* Turn the CPU off on next WFI instruction. */
-   exynos_cpu_power_down(core_id);
-
-   wfi();
-
-   if (pen_release == core_id) {
-   /*
-* OK, proper wakeup, we're done
-*/
-   break;
-   }
-
-   /*
-* Getting here, means that we have come out of WFI without
-* having been woken up - this shouldn't happen
-*
-* Just note it happening - when we're woken, we can report
-* its occurrence.
-*/
-   (*spurious)++;
-   }
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void __ref exynos_cpu_die(unsigned int cpu)
-{
-   int spurious = 0;
-
-   v7_exit_coherency_flush(louis);
-
-   platform_do_lowpower(cpu, spurious);
-
-   /*
-* bring this CPU back into the world of cache
-* coherency, and then restore interrupts
-*/
-   cpu_leave_lowpower();
-
-   if (spurious)
-   pr_warn(CPU%u: %u spurious wakeup calls\n, cpu, spurious);
-}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a9f1cf759949..a809f76c8160 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ 

Re: [PATCH v5 0/5] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled

[Daniel Lezcano]

On 08/05/2014 04:26 PM, Krzysztof Kozlowski wrote:

On 05.08.2014 16:03, Daniel Lezcano wrote:

On 08/05/2014 03:34 PM, Bartlomiej Zolnierkiewicz wrote:

Hi,

This patch series adds support for AFTR idle mode on boards with
secure firmware enabled and allows EXYNOS cpuidle driver usage on
Exynos4x12 SoCs.

It has been tested on Trats2 board (using Exynos4412 SoC with secure
firmware enabled) on which AFTR mode reduces power consumption by ~12%
when EXYNOS cpuidle driver is enabled (in both cases the default
exynos_defconfig config is used and CPU1-3 are offlined).


As a sidenote:

On my odroid-U2:
  * 4 cpus online - 130 mA
  * 3 cpus online - 164 mA
  * 2 cpus online - 160 mA
  * 1 cpu online  - 157 mA

So were are consuming more when there are unplugged cpu ... any ideas ?


On which tree are you testing? Current next has ARMCLK down feature
enabled. ARMCLK down may stop working after hotunplugging CPU:
http://www.spinics.net/lists/arm-kernel/msg352890.html

That was observed especially on Exynos4212 where ARMCLK down stops
working permanently. On Trats2 (Exynos4412) the clock down stopped only
a for short period after disabling CPU.


Hi Krzysztof,

I tested the patches you mentioned above on top of this patchset.

You are right this is directly related to the ARMCLK but the behavior 
may be not as you expect I think.


When I boot:

4 cpus online = 131 mA

Then I unplug one by one the cpus:

3 cpus online = 127 mA
2 cpus online = 123 mA
1 cpu online  = 120 mA

This is consistent.

But now, I online the cpus:

2 cpus online = 162 mA
3 cpus online = 165 mA
4 cpus online = 131 mA


-- side note --

Please note, I did not disable the cpuidle neither the AFTR state and 
the kernel did not hang but I don't see the noticeable power saving we 
should be observing when there is one cpu remaining entering the AFTR 
state (cpuidle stats show we enter AFTR). So there is definitively 
something wrong with this state.



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Re: [PATCH v3 0/4] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled

[Daniel Lezcano]

Hi Bartlomiej,

I tried to apply this patchset on top of next-20140708 but it does not 
apply.


Do you have a more recent version ?

Thanks in advance

  -- Daniel

On 07/09/2014 07:17 PM, Bartlomiej Zolnierkiewicz wrote:

Hi,

This patch series adds support for AFTR idle mode on boards with
secure firmware enabled and allows EXYNOS cpuidle driver usage on
Exynos4x12 SoCs.

It has been tested on Trats2 board (using Exynos4412 SoC with secure
firmware enabled) on which AFTR mode reduces power consumption by ~12%
when EXYNOS cpuidle driver is enabled (in both cases the default
exynos_defconfig config is used and CPU1-3 are offlined).

v3:
- rebased on top of next-20140708 +
   http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html
   (with rejects fixed)
   http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32808.html
   http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32991.html
   (with rejects fixed in patch #2)
- addressed review comments from Tomasz Figa and Daniel Lezcano

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics


Bartlomiej Zolnierkiewicz (4):
   ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines
   ARM: EXYNOS: add AFTR mode support to firmware do_idle method
   ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code
   ARM: EXYNOS: cpuidle: allow driver usage on Exynos4x12 SoCs

  arch/arm/include/asm/firmware.h  |  2 +-
  arch/arm/mach-exynos/common.h|  7 ++-
  arch/arm/mach-exynos/exynos.c|  3 ++-
  arch/arm/mach-exynos/firmware.c  | 36 ++--
  arch/arm/mach-exynos/pm.c| 39 +--
  drivers/cpuidle/cpuidle-exynos.c |  6 +++---
  6 files changed, 67 insertions(+), 26 deletions(-)




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Re: [PATCH v3 0/4] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled

[Daniel Lezcano]

On 07/09/2014 07:17 PM, Bartlomiej Zolnierkiewicz wrote:

Hi,

This patch series adds support for AFTR idle mode on boards with
secure firmware enabled and allows EXYNOS cpuidle driver usage on
Exynos4x12 SoCs.

It has been tested on Trats2 board (using Exynos4412 SoC with secure
firmware enabled) on which AFTR mode reduces power consumption by ~12%
when EXYNOS cpuidle driver is enabled (in both cases the default
exynos_defconfig config is used and CPU1-3 are offlined).



Hi Bartlomiej,

what is the status of this patchset ? Is it supposed to land for 3.17 ?

Thanks

  -- Daniel


v3:
- rebased on top of next-20140708 +
   http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html
   (with rejects fixed)
   http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32808.html
   http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32991.html
   (with rejects fixed in patch #2)
- addressed review comments from Tomasz Figa and Daniel Lezcano

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics


Bartlomiej Zolnierkiewicz (4):
   ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines
   ARM: EXYNOS: add AFTR mode support to firmware do_idle method
   ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code
   ARM: EXYNOS: cpuidle: allow driver usage on Exynos4x12 SoCs

  arch/arm/include/asm/firmware.h  |  2 +-
  arch/arm/mach-exynos/common.h|  7 ++-
  arch/arm/mach-exynos/exynos.c|  3 ++-
  arch/arm/mach-exynos/firmware.c  | 36 ++--
  arch/arm/mach-exynos/pm.c| 39 +--
  drivers/cpuidle/cpuidle-exynos.c |  6 +++---
  6 files changed, 67 insertions(+), 26 deletions(-)




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Re: [GIT PULL 4/5] Samsung exynos_mct update for v3.17

[Daniel Lezcano]

On 07/23/2014 01:33 AM, Kukjin Kim wrote:

On 07/23/14 02:32, Daniel Lezcano wrote:

On 07/22/2014 12:59 PM, Kukjin Kim wrote:

Daniel Lezcano wrote:


On 07/20/2014 12:06 AM, Olof Johansson wrote:

On Sat, Jul 19, 2014 at 09:52:52AM +0900, Kukjin Kim wrote:

Note that this is also based on 3.16-rc5 because of dependency with
previous samsung fixes including exynos_mct already merged in
mainline during -rc.

The following changes since commit
1795cd9b3a91d4b5473c97f491d63892442212ab:

Linux 3.16-rc5 (2014-07-13 14:04:33 -0700)

are available in the git repository at:




git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/exynos-mct

for you to fetch changes up to
1a631118c1d085fe162f3b6d44f710c72206ef2d:

clocksource: exynos_mct: Only use 32-bits where possible
(2014-07-19 03:07:52 +0900)


exynos_mct update for v3.17
- only use 32-bit access for performance benefits on exynos
32-bit system and this means ARCH timer should be supported
on exynos 64-bit system instead of current MCT.
- use readl_relaxed/writel_relaxed to consistently use the
proper functions in exynos_mct.


There's no reason for these to go through arm-soc, is there? They
should
go through the clocksource tree (Daniel Lezcano / Thomas Gleixner).
They
also lack acks from them if they for some reason need to go through
arm-soc.



Olof, you're right. The branch has no dependency with arm-soc so I
agreed.


Yes, that's right. Furthermore I have been discussing with Doug about
these patches before.

Kukjin, is there any dependency on these patches ?


Yeah, Daniel, it should be handled in the clocksource tree so how
should I do
for it?


I can pull your branch v3.17-next/mct-exynos and you drop the merge from
this branch in your master ?


Yes please and I did drop the merge in my -next just now.


Ok, thanks.

The patches are applied in my branch for 3.17.

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Re: [GIT PULL 4/5] Samsung exynos_mct update for v3.17

[Daniel Lezcano]

On 07/22/2014 12:59 PM, Kukjin Kim wrote:

Daniel Lezcano wrote:


On 07/20/2014 12:06 AM, Olof Johansson wrote:

On Sat, Jul 19, 2014 at 09:52:52AM +0900, Kukjin Kim wrote:

Note that this is also based on 3.16-rc5 because of dependency with
previous samsung fixes including exynos_mct already merged in
mainline during -rc.

The following changes since commit 1795cd9b3a91d4b5473c97f491d63892442212ab:

Linux 3.16-rc5 (2014-07-13 14:04:33 -0700)

are available in the git repository at:




git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/exynos-mct

for you to fetch changes up to 1a631118c1d085fe162f3b6d44f710c72206ef2d:

clocksource: exynos_mct: Only use 32-bits where possible
(2014-07-19 03:07:52 +0900)


exynos_mct update for v3.17
- only use 32-bit access for performance benefits on exynos
32-bit system and this means ARCH timer should be supported
on exynos 64-bit system instead of current MCT.
- use readl_relaxed/writel_relaxed to consistently use the
proper functions in exynos_mct.


There's no reason for these to go through arm-soc, is there? They should
go through the clocksource tree (Daniel Lezcano / Thomas Gleixner). They
also lack acks from them if they for some reason need to go through arm-soc.



Olof, you're right. The branch has no dependency with arm-soc so I agreed.


Yes, that's right. Furthermore I have been discussing with Doug about
these patches before.

Kukjin, is there any dependency on these patches ?


Yeah, Daniel, it should be handled in the clocksource tree so how should I do
for it?


I can pull your branch v3.17-next/mct-exynos and you drop the merge from 
this branch in your master ?




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Re: [GIT PULL 4/5] Samsung exynos_mct update for v3.17

[Daniel Lezcano]

On 07/20/2014 12:06 AM, Olof Johansson wrote:

On Sat, Jul 19, 2014 at 09:52:52AM +0900, Kukjin Kim wrote:

Note that this is also based on 3.16-rc5 because of dependency with
previous samsung fixes including exynos_mct already merged in
mainline during -rc.

The following changes since commit 1795cd9b3a91d4b5473c97f491d63892442212ab:

   Linux 3.16-rc5 (2014-07-13 14:04:33 -0700)

are available in the git repository at:




git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
tags/exynos-mct

for you to fetch changes up to 1a631118c1d085fe162f3b6d44f710c72206ef2d:

   clocksource: exynos_mct: Only use 32-bits where possible
(2014-07-19 03:07:52 +0900)


exynos_mct update for v3.17
- only use 32-bit access for performance benefits on exynos
   32-bit system and this means ARCH timer should be supported
   on exynos 64-bit system instead of current MCT.
- use readl_relaxed/writel_relaxed to consistently use the
   proper functions in exynos_mct.


There's no reason for these to go through arm-soc, is there? They should
go through the clocksource tree (Daniel Lezcano / Thomas Gleixner). They
also lack acks from them if they for some reason need to go through arm-soc.


Yes, that's right. Furthermore I have been discussing with Doug about 
these patches before.


Kukjin, is there any dependency on these patches ?

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Re: [PATCH 1/3] cpuidle: exynos: Allow to use the driver without AFTR

[Daniel Lezcano]

On 07/21/2014 10:36 AM, Krzysztof Kozlowski wrote:

Allow the driver to be used when AFTR enter function is not provided
(device platform data is NULL).

This actually does not give any special energy-saving benefits but
allows to track the idle time of each core. Additionally it is a safe
way to validate supplied platform data.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com


I think we already talk about this in the mailing list several times.
It does not make sense to enable the cpuidle driver for WFI just for the 
sake of tracking via sysfs some idle timings.


Using the cpuidle driver means using the underlying cpuidle 
infrastructure with all the stats computation in the governor.


If there is a *real* need of a WFI cpuidle driver, then a generic WFI 
cpuidle driver could be implemented to supersede this one.


It took a while to cleanup this driver and remove all the hacks around 
this AFTR state... :)





---
  drivers/cpuidle/cpuidle-exynos.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c
index 7c0151263828..5325a394be7e 100644
--- a/drivers/cpuidle/cpuidle-exynos.c
+++ b/drivers/cpuidle/cpuidle-exynos.c
@@ -77,7 +77,10 @@ static int exynos_cpuidle_probe(struct platform_device *pdev)
  {
int ret;

+   /* If NULL enter only WFI */
exynos_enter_aftr = (void *)(pdev-dev.platform_data);
+   if (!exynos_enter_aftr)
+   exynos_idle_driver.state_count = 1;

ret = cpuidle_register(exynos_idle_driver, NULL);
if (ret) {




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Re: [PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

[Daniel Lezcano]

On 07/16/2014 07:34 PM, Bartlomiej Zolnierkiewicz wrote:


Hi,

On Friday, May 30, 2014 03:53:09 PM Bartlomiej Zolnierkiewicz wrote:


Hi,

On Friday, May 30, 2014 01:34:45 PM Tomasz Figa wrote:

Hi Daniel,

On 30.05.2014 11:30, Daniel Lezcano wrote:

On 04/24/2014 07:42 PM, Tomasz Figa wrote:

Hi Daniel,

Please see my comments inline.

Btw. Please fix your e-mail composer to properly wrap your messages
around 7xth column, as otherwise they're hard to read.

On 04.04.2014 11:48, Daniel Lezcano wrote:

The following driver is for exynos4210. I did not yet finished the
other boards, so
I created a specific driver for 4210 which could be merged later.

The driver is based on Colin Cross's driver found at:

https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9a4dfa3b393a010%5E%5E!/



This one was based on a 3.4 kernel and an old API.

It has been refreshed, simplified and based on the recent code cleanup
I sent
today.

The AFTR could be entered when all the cpus (except cpu0) are down. In
order to
reach this situation, the couple idle states are used.

There is a sync barrier at the entry and the exit of the low power
function. So
all cpus will enter and exit the function at the same time.

At this point, CPU0 knows the other cpu will power down itself. CPU0
waits for
the CPU1 to be powered down and then initiate the AFTR power down
sequence.

No interrupts are handled by CPU1, this is why we switch to the timer
broadcast
even if the local timer is not impacted by the idle state.

When CPU0 wakes up, it powers up CPU1 and waits for it to boot. Then
they both
exit the idle function.

This driver allows the exynos4210 to have the same power consumption
at idle
time than the one when we have to unplug CPU1 in order to let CPU0 to
reach
the AFTR state.

This patch is a RFC because, we have to find a way to remove the macros
definitions and cpu powerdown function without pulling the arch
dependent
headers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
   arch/arm/mach-exynos/common.c|   11 +-
   drivers/cpuidle/Kconfig.arm  |8 ++
   drivers/cpuidle/Makefile |1 +
   drivers/cpuidle/cpuidle-exynos4210.c |  226
++


[ ... ]



Otherwise, I quite like the whole idea. I need to play a bit with CPU
hotplug and PMU to verify that things couldn't really be simplified a
bit, but in general this looks reasonably.


Hi Tomasz,

did you have time to look at this simplification ?


Unfortunately I got preempted with other things to do and now I'm on
vacation. I worked a bit with Bart (added on CC) on this and generally
the conclusion was that all the things are necessary. He was also
working to extend the driver to support Exynos4x12.

Bart, has anything interesting showed up since we talked about this last
time?


Since we last looked into this I have fixed the standard AFTR support
for Exynos3250 and started to work on adding Exynos3250 support to this
driver (as Exynos3250 support has bigger priority than Exynos4x12 one).
Unfortunately I also got preempted with other things so it is still
unfinished and doesn't work yet.  Moreover I had no possibility to test
the new driver on Exynos4210 based Origen yet (I hope to do this next
week).


I have tested this patch on Origen board (Exynos4210 rev 1.1) and it
causes system lockup (it seems that the code gets stuck on waiting for
CPU1 to wake up).

The kernels I have tried:
* current -next + this patch + few fixes to bring it up to date
* commit cd245f5 + this patch + some fixes
* next-20140403 + your Exynos cpuidle patch series + this patch

I have also tried with S5P_VA_SYSRAM replaced by S5P_INFORM5 to
match Exynos 4210 rev 1.1 but it didn't help.

U-Boot version used is:
U-Boot 2012.07 (Sep 22 2012 - 05:12:41) for ORIGEN

Could you please tell me which hardware/bootloader/kernel exactly
have you used to test this patch?


When I used it, it was on top of 3.15-rc1:

https://git.linaro.org/people/daniel.lezcano/linux.git/shortlog/refs/heads/cpuidle/samsung-next

The hardware was a exynos-4210 origen board ver A.


Also could you please port/retest your patch over the current -next?


Will do that in my free time after unstacking my emails after 2 weeks of 
vacations :)




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Re: [PATCH] cpuidle: big.LITTLE: add MCPM dependency

[Daniel Lezcano]

On 07/14/2014 01:23 PM, Arnd Bergmann wrote:

662322fcb6d (cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config)
made it possible for the big-little cpuidle driver to run on exynos,
which may or may not include MCPM support at compile time, so we
run into a link error when it is disabled:

drivers/built-in.o: In function `bl_enter_powerdown':
:(.text+0x1889a0): undefined reference to `mcpm_cpu_powered_up'
drivers/built-in.o: In function `bl_powerdown_finisher':
:(.text+0x1889e8): undefined reference to `mcpm_set_entry_vector'
:(.text+0x1889ec): undefined reference to `mcpm_cpu_suspend'

This adds an explicit dependency to CONFIG_MCPM to avoid that
case.

Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Chander Kashyap chander.kash...@linaro.org
Cc: Tomasz Figa t.f...@samsung.com
Cc: Daniel Lezcano daniel.lezc...@linaro.org
---
I believe the broken commit is only present in the samsung/for-next
tree (through v3.17-next/cpuidle-exynos), so it should be fixed there.

On a side note, I wonder if we should have platform dependencies at
all, or just the MCPM dependency by itself.
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 2f6b33ea6e08..459b7c91407a 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -10,6 +10,7 @@ config ARM_ARMADA_370_XP_CPUIDLE
  config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
+   depends on MCPM


Why do we want to depend on MCPM ? If I want to enable the cpuidle 
driver, the Kconfig should select the dependencies instead of letting 
the user to figure out what dependency is missing in order to enable the 
cpuidle option, no ?


+   select MCPM


select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help




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Re: Enabling 8 cores on 5420

[Daniel Lezcano]

On 06/22/2014 11:30 PM, Alim Akhtar wrote:

Hi
PTAL https://patchwork.kernel.org/patch/4315711/
I hope your tree already includes
http://www.gossamer-threads.com/lists/linux/kernel/1940123



Hi Alim,

I applied the patches above and set the configuration option for 
EXYNOS_MCPM but I have:


[7.769420] CPU1: failed to boot: -19
[7.778360] CPU2: failed to boot: -19
[7.806411] CPU4: failed to boot: -19
[7.811294] CPU3: failed to boot: -19
[7.815333] CPU7: failed to boot: -19
[7.826401] CPU6: failed to boot: -19
[7.829711] CPU5: failed to boot: -19

Is there something I missed ?

Thanks !

  -- Daniel


On Mon, Jun 23, 2014 at 2:32 AM, Andreas Färber afaer...@suse.de wrote:

Am 30.05.2014 11:25, schrieb Daniel Lezcano:


Hi all,

I am trying an upstream kernel + some patches to enable ethernet on
arndale octa.

Unfortunately, only 4 cores boot up. The other ones fail to boot.

[12.179453] CPU6: failed to come online
[13.189479] CPU7: failed to come online
[14.199479] CPU4: failed to come online
[15.209743] CPU5: failed to come online

What should I do to enable those 8 cores ? Is there a patchset somewhere
to do so ?


Ping? Confirmed still present on Arndale Octa with kgene's for-next +
patch to get 2-4 up.

Andreas

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Re: [PATCH v2] clocksource: exynos_mct: Fix ftrace

[Daniel Lezcano]

On 06/19/2014 07:08 PM, Doug Anderson wrote:

In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock.


Hi Thomas,

is it possible you update the tip/timers/core so I can get visibility on 
the above patch to apply this one ?


Thanks
  -- Daniel



We properly marked
exynos4_read_sched_clock() as notrace.  However, we then went and
called another function that _wasn't_ notrace.  That means if you do:

   cd /sys/kernel/debug/tracing/
   echo function_graph  current_tracer

You'll get a crash.

Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function.  It's important to keep other users of MCT
traceable because the MCT is actually quite slow to access and we want
exynos4_frc_read() to show up in ftrace profiles if it's the
bottleneck.

Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- Split out from other patches so this can go into 3.16.
- Better comment about why exynos4_frc_read() should be traceable.
- No more useless inline.

  drivers/clocksource/exynos_mct.c | 9 +++--
  1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index f71d55f..5ce99c0 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -162,7 +162,7 @@ static void exynos4_mct_frc_start(void)
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
  }

-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static cycle_t notrace _exynos4_frc_read(void)
  {
unsigned int lo, hi;
u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@@ -176,6 +176,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
return ((cycle_t)hi  32) | lo;
  }

+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+   return _exynos4_frc_read();
+}
+
  static void exynos4_frc_resume(struct clocksource *cs)
  {
exynos4_mct_frc_start();
@@ -192,7 +197,7 @@ struct clocksource mct_frc = {

  static u64 notrace exynos4_read_sched_clock(void)
  {
-   return exynos4_frc_read(mct_frc);
+   return _exynos4_frc_read();
  }

  static void __init exynos4_clocksource_init(void)




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Re: [PATCH] clocksource: exynos-mct: Register the timer for stable udelay

[Daniel Lezcano]

On 06/19/2014 01:17 AM, Doug Anderson wrote:

Amit,

Thanks for posting!

On Wed, Jun 18, 2014 at 4:31 AM, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:

This patch register the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for the
exynos platform and avoid using unnecessary calibrated jiffies. This change
have been tested on exynos5420 based board.

Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---

Patches from David Riley confirmed that udelay is broken in exynos5420.
Link to those patches are,
1) https://patchwork.kernel.org/patch/4344911/
2) https://patchwork.kernel.org/patch/4344881/

  drivers/clocksource/exynos_mct.c | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 8d64200..57cb3dc 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -198,10 +198,21 @@ static u64 notrace exynos4_read_sched_clock(void)
 return exynos4_frc_read(mct_frc);
  }

+static struct delay_timer exynos4_delay_timer;
+
+static unsigned long exynos4_read_current_timer(void)
+{
+   return exynos4_frc_read(mct_frc);


This is terribly inefficient to read all 64-bits and then cast back to
a 32-bit value.  Replace with:

return __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);



+}
+
  static void __init exynos4_clocksource_init(void)
  {
 exynos4_mct_frc_start(0, 0);


Please rebase atop (1d80415 clocksource: exynos_mct: Don't reset the
counter during boot and resume), which is in linuxnext among other
places.



+   exynos4_delay_timer.read_current_timer = exynos4_read_current_timer;
+   exynos4_delay_timer.freq = clk_rate;
+   register_current_timer_delay(exynos4_delay_timer);
+
 if (clocksource_register_hz(mct_frc, clk_rate))
 panic(%s: can't register clocksource\n, mct_frc.name);


It does seem to work for me though.  :)


Doug,

aren't you working on a 32 bits version ? So this patch could be 
simplified ?


Thanks
  -- Daniel


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Re: [PATCH v2] clocksource: exynos-mct: Register the timer for stable udelay

[Daniel Lezcano]

On 06/19/2014 10:39 AM, Amit Daniel Kachhap wrote:

This patch register the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for the
exynos platform and avoid using unnecessary calibrated jiffies. This change
has been tested on exynos5420 based board and udelay is very close to
expected.

Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
Changes in V2:
* Added #defines for ARM and ARM64 as pointed by Doug Anderson.

Patches from David Riley confirmed that udelay is broken in exynos5420.
Link to those patches are,
1) https://patchwork.kernel.org/patch/4344911/
2) https://patchwork.kernel.org/patch/4344881/

  drivers/clocksource/exynos_mct.c | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index f71d55f..02927e2 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -195,10 +195,25 @@ static u64 notrace exynos4_read_sched_clock(void)
return exynos4_frc_read(mct_frc);
  }

+static struct delay_timer exynos4_delay_timer;
+
+static unsigned long exynos4_read_current_timer(void)
+{
+#ifdef ARM
+   return __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
+#else /* ARM64, etc */
+   return exynos4_frc_read(mct_frc);
+#endif
+}
+


There isn't another solution than that ? macros definitions in C file 
are avoided as much as possible.



  static void __init exynos4_clocksource_init(void)
  {
exynos4_mct_frc_start();

+   exynos4_delay_timer.read_current_timer = exynos4_read_current_timer;


exynos4_read_current_timer ?


+   exynos4_delay_timer.freq = clk_rate;
+   register_current_timer_delay(exynos4_delay_timer);
+
if (clocksource_register_hz(mct_frc, clk_rate))
panic(%s: can't register clocksource\n, mct_frc.name);





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Re: [PATCH v2] clocksource: exynos-mct: Register the timer for stable udelay

[Daniel Lezcano]

On 06/19/2014 12:21 PM, amit daniel kachhap wrote:

On Thu, Jun 19, 2014 at 2:41 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:

On 06/19/2014 10:39 AM, Amit Daniel Kachhap wrote:


This patch register the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for the
exynos platform and avoid using unnecessary calibrated jiffies. This
change
has been tested on exynos5420 based board and udelay is very close to
expected.

Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
Changes in V2:
* Added #defines for ARM and ARM64 as pointed by Doug Anderson.

Patches from David Riley confirmed that udelay is broken in exynos5420.
Link to those patches are,
1) https://patchwork.kernel.org/patch/4344911/
2) https://patchwork.kernel.org/patch/4344881/

   drivers/clocksource/exynos_mct.c | 15 +++
   1 file changed, 15 insertions(+)

diff --git a/drivers/clocksource/exynos_mct.c
b/drivers/clocksource/exynos_mct.c
index f71d55f..02927e2 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -195,10 +195,25 @@ static u64 notrace exynos4_read_sched_clock(void)
 return exynos4_frc_read(mct_frc);
   }

+static struct delay_timer exynos4_delay_timer;
+
+static unsigned long exynos4_read_current_timer(void)
+{
+#ifdef ARM
+   return __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
+#else /* ARM64, etc */
+   return exynos4_frc_read(mct_frc);
+#endif
+}
+



There isn't another solution than that ? macros definitions in C file are
avoided as much as possible.

I also didn't want to use macros but used as a last option. you want
me to put more comments here?
Or something like below is also possible for checking the size of
(unsigned long) in runtime.

unsigned long x;
unsigned int size = (char *)(x + 1) - (char *)(x);
if (size == 4)
return __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
else
return exynos4_frc_read(mct_frc);

But this involves extra computation which should not be used for time
critical functions.
Any suggestion?


AFAIU, Doug may change the exynos4_frc_read to be 32 bits. So may not 
need those macros as 'exynos4_frc_read' could be used instead.


Doug may confirm this.


   static void __init exynos4_clocksource_init(void)
   {
 exynos4_mct_frc_start();

+   exynos4_delay_timer.read_current_timer =
exynos4_read_current_timer;



exynos4_read_current_timer ?

Any issue in the naming?


No problem with the naming. As Tomasz pointed also, you are passing '' 
for the function pointer.



+   exynos4_delay_timer.freq = clk_rate;
+   register_current_timer_delay(exynos4_delay_timer);
+
 if (clocksource_register_hz(mct_frc, clk_rate))
 panic(%s: can't register clocksource\n, mct_frc.name);





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Re: [PATCH] clocksource: exynos-mct: Register the timer for stable udelay

[Daniel Lezcano]

On 06/19/2014 05:49 PM, Doug Anderson wrote:

Daniel,

On Thu, Jun 19, 2014 at 2:07 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:

On 06/19/2014 01:17 AM, Doug Anderson wrote:


Amit,

Thanks for posting!

On Wed, Jun 18, 2014 at 4:31 AM, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:


This patch register the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for the
exynos platform and avoid using unnecessary calibrated jiffies. This
change
have been tested on exynos5420 based board.

Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---

Patches from David Riley confirmed that udelay is broken in exynos5420.
Link to those patches are,
1) https://patchwork.kernel.org/patch/4344911/
2) https://patchwork.kernel.org/patch/4344881/

   drivers/clocksource/exynos_mct.c | 11 +++
   1 file changed, 11 insertions(+)

diff --git a/drivers/clocksource/exynos_mct.c
b/drivers/clocksource/exynos_mct.c
index 8d64200..57cb3dc 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -198,10 +198,21 @@ static u64 notrace exynos4_read_sched_clock(void)
  return exynos4_frc_read(mct_frc);
   }

+static struct delay_timer exynos4_delay_timer;
+
+static unsigned long exynos4_read_current_timer(void)
+{
+   return exynos4_frc_read(mct_frc);



This is terribly inefficient to read all 64-bits and then cast back to
a 32-bit value.  Replace with:

return __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);



+}
+
   static void __init exynos4_clocksource_init(void)
   {
  exynos4_mct_frc_start(0, 0);



Please rebase atop (1d80415 clocksource: exynos_mct: Don't reset the
counter during boot and resume), which is in linuxnext among other
places.



+   exynos4_delay_timer.read_current_timer =
exynos4_read_current_timer;
+   exynos4_delay_timer.freq = clk_rate;
+   register_current_timer_delay(exynos4_delay_timer);
+
  if (clocksource_register_hz(mct_frc, clk_rate))
  panic(%s: can't register clocksource\n, mct_frc.name);



It does seem to work for me though.  :)



Doug,

aren't you working on a 32 bits version ? So this patch could be simplified


I could do that if someone told me that they'll land it.

My understanding of the current status is:
* I posed the 64-bit version that's almost as fast as the 32-bit version.
* I asked if people want the 32-bit version: no answer
* I asked if anyone is opposed to the 64-bit version: no answer


Yeah, that happens. I thought you were working on the 32 bits.


I know that you wanted me to clean up the description of the 64-bit
version so I was going to do that and repost.  If there's someone
willing to review / ack the 32-bit version I'd be happy to do that
instead.  Possibly I'll do both and a maintainer can choose which to
apply?


Please, resend me the patch 1/3 as it is urgent with the changelog changed.


In the case here I was suggesting using the 32-bit version just
because on ARM32 there's totally no reason to read 64-bits.  I hadn't
given a thought to ARM64.  More on that in response to the other
messages.


Is there a 64bits platform using exynos_mct ?


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Re: [PATCH 1/3] clocksource: exynos_mct: Fix ftrace

[Daniel Lezcano]

On 06/04/2014 07:30 PM, Doug Anderson wrote:

In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock.  We properly marked
exynos4_read_sched_clock() as notrace.  However, we then went and
called another function that _wasn't_ notrace.  That means if you do:

   cd /sys/kernel/debug/tracing/
   echo function_graph  current_tracer

You'll get a crash.

Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function.  It's important to keep other users of MCT
traceable because the MCT is actually quite slow.


Thanks for the explanation in the other email.

I think the last sentence is a bit confusing because you are implicitly 
saying you need these traces to investigate why the timer is slow which 
is referring to something not related to this fix.



Signed-off-by: Doug Anderson diand...@chromium.org
---
  drivers/clocksource/exynos_mct.c | 9 +++--
  1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 8d64200..ba3a683 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -165,7 +165,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
  }

-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static inline cycle_t notrace _exynos4_frc_read(void)


Why inline ?


  {
unsigned int lo, hi;
u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@@ -179,6 +179,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
return ((cycle_t)hi  32) | lo;
  }

+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+   return _exynos4_frc_read();
+}
+
  static void exynos4_frc_resume(struct clocksource *cs)
  {
exynos4_mct_frc_start(0, 0);
@@ -195,7 +200,7 @@ struct clocksource mct_frc = {

  static u64 notrace exynos4_read_sched_clock(void)
  {
-   return exynos4_frc_read(mct_frc);
+   return _exynos4_frc_read();
  }

  static void __init exynos4_clocksource_init(void)




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Re: [PATCH 1/3] clocksource: exynos_mct: Fix ftrace

[Daniel Lezcano]

On 06/16/2014 06:40 AM, Doug Anderson wrote:

Daniel,

On Sun, Jun 15, 2014 at 2:18 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:

On 06/04/2014 07:30 PM, Doug Anderson wrote:


In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock.  We properly marked
exynos4_read_sched_clock() as notrace.  However, we then went and
called another function that _wasn't_ notrace.  That means if you do:

cd /sys/kernel/debug/tracing/
echo function_graph  current_tracer

You'll get a crash.

Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function.  It's important to keep other users of MCT
traceable because the MCT is actually quite slow.




Hi Doug,

could you elaborate ? I don't get the 'because the MCT ... slow'


Sorry, I was trying to avoid duplication in the series and it's more
obvious when you look at parts 2 and 3 of the series.  ;)

Doing the math (please correct any miscalculations) using the numbers
from the other patches: You can see that the existing code takes
1323852 us for 100 gettimeofday in userspace.  The fastest
implementation (just shaving to a 32-bit timer) gets us as fast as
~100 us for 100 gettimeofday in userspace.

 From profiling, I believe that gettimeofday from userspace is about
50% overhead (system call, multiplication, copies, etc) and about 50%
MCT read.  That means that the fastest you can possibly do an MCT read
is in .5us or 500ns.

I believe an A15 has something like 1 or 2 cycles per instruction.  If
it were 2 cycles per instruction, it can execute a normal instruction
on a 2GHz machine in .5ns.  That means we can execute 1000 normal
instructions in the time it takes to do a since MCT access.

...so I guess that's what I'd call slow.  ;)  What do you think?  I
know that the MCT read shows up in whole system profiles of
gettimeofday.


Hi Dough,

thanks for the explanation. I still don't get why it is important to 
keep others users of mct traceable because it is quite slow ? May be it 
is what you explained here, but I miss the connection between 'the other 
users' - 'traceable' - 'because slow'.


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Re: [PATCH 1/3] clocksource: exynos_mct: Fix ftrace

[Daniel Lezcano]

On 06/04/2014 07:30 PM, Doug Anderson wrote:

In (93bfb76 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock.  We properly marked
exynos4_read_sched_clock() as notrace.  However, we then went and
called another function that _wasn't_ notrace.  That means if you do:

   cd /sys/kernel/debug/tracing/
   echo function_graph  current_tracer

You'll get a crash.

Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function.  It's important to keep other users of MCT
traceable because the MCT is actually quite slow.



Hi Doug,

could you elaborate ? I don't get the 'because the MCT ... slow'

Thanks

  -- Daniel


Signed-off-by: Doug Anderson diand...@chromium.org
---
  drivers/clocksource/exynos_mct.c | 9 +++--
  1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 8d64200..ba3a683 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -165,7 +165,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
  }

-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static inline cycle_t notrace _exynos4_frc_read(void)
  {
unsigned int lo, hi;
u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@@ -179,6 +179,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
return ((cycle_t)hi  32) | lo;
  }

+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+   return _exynos4_frc_read();
+}
+
  static void exynos4_frc_resume(struct clocksource *cs)
  {
exynos4_mct_frc_start(0, 0);
@@ -195,7 +200,7 @@ struct clocksource mct_frc = {

  static u64 notrace exynos4_read_sched_clock(void)
  {
-   return exynos4_frc_read(mct_frc);
+   return _exynos4_frc_read();
  }

  static void __init exynos4_clocksource_init(void)




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Re: [PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

[Daniel Lezcano]

On 06/11/2014 10:50 AM, Krzysztof Kozlowski wrote:

On pią, 2014-04-04 at 11:48 +0200, Daniel Lezcano wrote:

The following driver is for exynos4210. I did not yet finished the other 
boards, so
I created a specific driver for 4210 which could be merged later.

The driver is based on Colin Cross's driver found at:

https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9a4dfa3b393a010%5E%5E!/

This one was based on a 3.4 kernel and an old API.

It has been refreshed, simplified and based on the recent code cleanup I sent
today.

The AFTR could be entered when all the cpus (except cpu0) are down. In order to
reach this situation, the couple idle states are used.

There is a sync barrier at the entry and the exit of the low power function. So
all cpus will enter and exit the function at the same time.

At this point, CPU0 knows the other cpu will power down itself. CPU0 waits for
the CPU1 to be powered down and then initiate the AFTR power down sequence.

No interrupts are handled by CPU1, this is why we switch to the timer broadcast
even if the local timer is not impacted by the idle state.

When CPU0 wakes up, it powers up CPU1 and waits for it to boot. Then they both
exit the idle function.

This driver allows the exynos4210 to have the same power consumption at idle
time than the one when we have to unplug CPU1 in order to let CPU0 to reach
the AFTR state.

This patch is a RFC because, we have to find a way to remove the macros
definitions and cpu powerdown function without pulling the arch dependent
headers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
  arch/arm/mach-exynos/common.c|   11 +-
  drivers/cpuidle/Kconfig.arm  |8 ++
  drivers/cpuidle/Makefile |1 +
  drivers/cpuidle/cpuidle-exynos4210.c |  226 ++
  4 files changed, 245 insertions(+), 1 deletion(-)
  create mode 100644 drivers/cpuidle/cpuidle-exynos4210.c


(...)


diff --git a/drivers/cpuidle/cpuidle-exynos4210.c 
b/drivers/cpuidle/cpuidle-exynos4210.c
new file mode 100644
index 000..56f6d51
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-exynos4210.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Copyright (c) 2014 Linaro : Daniel Lezcano daniel.lezc...@linaro.org
+ * http://www.linaro.org
+ *
+ * Based on the work of Colin Cross ccr...@android.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/cpuidle.h
+#include linux/cpu_pm.h
+#include linux/io.h
+#include linux/platform_device.h
+
+#include asm/proc-fns.h
+#include asm/suspend.h
+#include asm/cpuidle.h
+
+#include plat/pm.h
+#include plat/cpu.h
+#include plat/map-base.h
+#include plat/map-s5p.h
+
+static atomic_t exynos_idle_barrier;


Hi,

Shouldn't the exynos_idle_barrier be initialized here?


As it is a static data it will be initialized to zero.


I know you sent the patch almost 2 months ago but I stomped on this
while testing it on Exynos3250.


No problem. And what results on exynos3250 ?

Thanks !

  -- Daniel


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Re: [PATCH 6/7] ARM: EXYNOS: PM: fix register setup on EXYNOS4x12 for AFTR mode code

[Daniel Lezcano]

On 06/02/2014 02:08 PM, Bartlomiej Zolnierkiewicz wrote:


Hi,

On Friday, May 16, 2014 11:03:11 AM Daniel Lezcano wrote:

On 05/05/2014 12:57 PM, Bartlomiej Zolnierkiewicz wrote:

Add S5P_CENTRAL_SEQ_OPTION register setup for EXYNOS4x12 to AFTR
mode code.  Without this setup AFTR mode doesn't show any benefit
over WFI one.  When this setup is applied AFTR mode reduces power
consumption by ~12% (as measured on Trats2 board).

This change is a preparation for adding secure firmware support to
EXYNOS cpuidle driver.

Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
   arch/arm/mach-exynos/pm.c | 4 
   1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 18f6bf8..3922968 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -391,6 +391,10 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
case CPU_PM_ENTER:
if (cpu == 0) {
exynos_pm_central_suspend();
+   if (soc_is_exynos4212() || soc_is_exynos4412())
+   __raw_writel(S5P_USE_STANDBY_WFI0 |
+S5P_USE_STANDBY_WFE0,
+S5P_CENTRAL_SEQ_OPTION);


Why not put this code in the exynos_enter_aftr() ?


I would prefer to keep this code close to exynos_pm_central_suspend()
because exynos_pm_suspend() (which calls exynos_pm_central_suspend()
too) also contains S5P_USE_STANDBY_WF[I,E]0 setting code (done for all
SoCs).  If possible I would like to make this code common for AFTR 
suspend in the future (once it is tested on Exynos4210 and Exynos5250)
by moving S5P_USE_STANDBY_WF[I,E]0 setting to exynos_pm_central_suspend()
and doing it for all SoCs.  Are you okay with this?


Yeah, no problem.



exynos_cpu_save_register();
}
break;


Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics




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Re: [PATCH v2 4/7] ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines

[Daniel Lezcano]

On 06/02/2014 02:35 PM, Bartlomiej Zolnierkiewicz wrote:

Replace EXYNOS_BOOT_VECTOR_ADDR and EXYNOS_BOOT_VECTOR_FLAG macros
by exynos_boot_vector_addr() and exynos_boot_vector_flag() static
inlines.

This patch shouldn't cause any functionality changes.

Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com


Acked-by: Daniel Lezcano daniel.lezc...@linaro.org


---
  arch/arm/mach-exynos/pm.c | 28 
  1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 87c0d34..cf09383 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -166,12 +166,23 @@ int exynos_cluster_power_state(int cluster)
S5P_CORE_LOCAL_PWR_EN);
  }

-#define EXYNOS_BOOT_VECTOR_ADDR(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-   S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (sysram_base_addr + 0x24) : S5P_INFORM0))
-#define EXYNOS_BOOT_VECTOR_FLAG(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-   S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (sysram_base_addr + 0x20) : S5P_INFORM1))
+static inline void __iomem *exynos_boot_vector_addr(void)
+{
+   if (samsung_rev() == EXYNOS4210_REV_1_1)
+   return S5P_INFORM7;
+   else if (samsung_rev() == EXYNOS4210_REV_1_0)
+   return sysram_base_addr + 0x24;
+   return S5P_INFORM0;
+}
+
+static inline void __iomem *exynos_boot_vector_flag(void)
+{
+   if (samsung_rev() == EXYNOS4210_REV_1_1)
+   return S5P_INFORM6;
+   else if (samsung_rev() == EXYNOS4210_REV_1_0)
+   return sysram_base_addr + 0x20;
+   return S5P_INFORM1;
+}

  #define S5P_CHECK_AFTR  0xFCBA0D10
  #define S5P_CHECK_SLEEP 0x0BAD
@@ -184,8 +195,9 @@ static void exynos_set_wakeupmask(long mask)

  static void exynos_cpu_set_boot_vector(long flags)
  {
-   __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
-   __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+   __raw_writel(virt_to_phys(exynos_cpu_resume),
+exynos_boot_vector_addr());
+   __raw_writel(flags, exynos_boot_vector_flag());
  }

  void exynos_enter_aftr(void)




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Re: [PATCH v2 7/7] ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code

[Daniel Lezcano]

On 06/02/2014 02:35 PM, Bartlomiej Zolnierkiewicz wrote:

* Use do_idle firmware method instead of cpu_do_idle() on boards with
   secure firmware enabled.

* Use sysram_ns_base_addr + 0x24 address for exynos_boot_vector_addr()
   and sysram_ns_base_addr + 0x20 one for exynos_boot_vector_flag() on
   boards with secure firmware enabled.

This patch fixes hang on an attempt to enter AFTR mode for TRATS2
board (which uses EXYNOS4412 SoC with secure firmware enabled).

This patch shouldn't cause any functionality changes on boards that
don't use secure firmware.

Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
  arch/arm/mach-exynos/pm.c| 8 ++--
  drivers/cpuidle/cpuidle-exynos.c | 7 ++-
  2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 0fb9a5a..62a0a5e 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -169,7 +169,9 @@ int exynos_cluster_power_state(int cluster)

  static inline void __iomem *exynos_boot_vector_addr(void)
  {
-   if (samsung_rev() == EXYNOS4210_REV_1_1)
+   if (firmware_run())
+   return sysram_ns_base_addr + 0x24;
+   else if (samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM7;
else if (samsung_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x24;
@@ -178,7 +180,9 @@ static inline void __iomem *exynos_boot_vector_addr(void)

  static inline void __iomem *exynos_boot_vector_flag(void)
  {
-   if (samsung_rev() == EXYNOS4210_REV_1_1)
+   if (firmware_run())
+   return sysram_ns_base_addr + 0x20;
+   else if (samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM6;
else if (samsung_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x20;
diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c
index 7c01512..f90a4a0 100644
--- a/drivers/cpuidle/cpuidle-exynos.c
+++ b/drivers/cpuidle/cpuidle-exynos.c
@@ -17,13 +17,18 @@
  #include asm/proc-fns.h
  #include asm/suspend.h
  #include asm/cpuidle.h
+#include asm/firmware.h

  static void (*exynos_enter_aftr)(void);

  static int idle_finisher(unsigned long flags)
  {
exynos_enter_aftr();
-   cpu_do_idle();
+   if (firmware_run())
+   /* no need to check the return value on EXYNOS SoCs */
+   call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
+   else
+   cpu_do_idle();


Why not move this code into the exynos_enter_aftr() function, so 
preventing more dependency ?




return 1;
  }




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Enabling 8 cores on 5420

[Daniel Lezcano]

Hi all,

I am trying an upstream kernel + some patches to enable ethernet on 
arndale octa.


Unfortunately, only 4 cores boot up. The other ones fail to boot.

[12.179453] CPU6: failed to come online
[13.189479] CPU7: failed to come online
[14.199479] CPU4: failed to come online
[15.209743] CPU5: failed to come online

What should I do to enable those 8 cores ? Is there a patchset somewhere 
to do so ?


Thanks

  -- Daniel


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Re: [PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

[Daniel Lezcano]

On 04/24/2014 07:42 PM, Tomasz Figa wrote:

Hi Daniel,

Please see my comments inline.

Btw. Please fix your e-mail composer to properly wrap your messages
around 7xth column, as otherwise they're hard to read.

On 04.04.2014 11:48, Daniel Lezcano wrote:

The following driver is for exynos4210. I did not yet finished the
other boards, so
I created a specific driver for 4210 which could be merged later.

The driver is based on Colin Cross's driver found at:

https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9a4dfa3b393a010%5E%5E!/


This one was based on a 3.4 kernel and an old API.

It has been refreshed, simplified and based on the recent code cleanup
I sent
today.

The AFTR could be entered when all the cpus (except cpu0) are down. In
order to
reach this situation, the couple idle states are used.

There is a sync barrier at the entry and the exit of the low power
function. So
all cpus will enter and exit the function at the same time.

At this point, CPU0 knows the other cpu will power down itself. CPU0
waits for
the CPU1 to be powered down and then initiate the AFTR power down
sequence.

No interrupts are handled by CPU1, this is why we switch to the timer
broadcast
even if the local timer is not impacted by the idle state.

When CPU0 wakes up, it powers up CPU1 and waits for it to boot. Then
they both
exit the idle function.

This driver allows the exynos4210 to have the same power consumption
at idle
time than the one when we have to unplug CPU1 in order to let CPU0 to
reach
the AFTR state.

This patch is a RFC because, we have to find a way to remove the macros
definitions and cpu powerdown function without pulling the arch dependent
headers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
  arch/arm/mach-exynos/common.c|   11 +-
  drivers/cpuidle/Kconfig.arm  |8 ++
  drivers/cpuidle/Makefile |1 +
  drivers/cpuidle/cpuidle-exynos4210.c |  226
++


[ ... ]



Otherwise, I quite like the whole idea. I need to play a bit with CPU
hotplug and PMU to verify that things couldn't really be simplified a
bit, but in general this looks reasonably.


Hi Tomasz,

did you have time to look at this simplification ?

Thanks
  -- Daniel

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Re: Enabling 8 cores on 5420

[Daniel Lezcano]

On 05/30/2014 03:33 PM, Andreas Färber wrote:

Hi,

Am 30.05.2014 11:25, schrieb Daniel Lezcano:


I am trying an upstream kernel + some patches to enable ethernet on
arndale octa.

Unfortunately, only 4 cores boot up. The other ones fail to boot.

[12.179453] CPU6: failed to come online
[13.189479] CPU7: failed to come online
[14.199479] CPU4: failed to come online
[15.209743] CPU5: failed to come online

What should I do to enable those 8 cores ? Is there a patchset somewhere
to do so ?


Yes, this is the reply I received just yesterday from Tushar Behera:

Can you check after applying following two patches for Arndale-Octa
([1],[2])? In other words, a patch similar to [2] might be required
for this board too if it is booting under secure mode.

[1] http://www.spinics.net/lists/linux-samsung-soc/msg31776.html

[PATCH v2 Resend 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode

[2] http://www.spinics.net/lists/linux-samsung-soc/msg31777.html

[PATCH v2 Resend 2/2] ARM: dts: Add secure firmware support for Arndale-octa


The first one I tested successfully on the 5410 already.


Hi Andreas,

thx for the pointers. I tested the patches but unfortunately they don't 
enable the cpus.



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Re: [PATCH v6 1/6] driver: cpuidle-big-little: add of_device_id structure

[Daniel Lezcano]

On 05/16/2014 10:03 AM, Chander Kashyap wrote:

This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com


Acked-by: Daniel Lezcano daniel.lezc...@linaro.org


---
  drivers/cpuidle/cpuidle-big_little.c |   11 ++-
  1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
  }

+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
  static int __init bl_idle_init(void)
  {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;

/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores




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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

[Daniel Lezcano]

On 05/28/2014 06:35 AM, Kukjin Kim wrote:

Chander Kashyap wrote:


On 26 May 2014 15:59, Tomasz Figa tomasz.f...@gmail.com wrote:

Hi Chander,

On 16.05.2014 10:03, Chander Kashyap wrote:

Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7

cores.


This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
   1. [PATCH 0/5] MCPM backend for Exynos5420
  http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36

++

  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)



For the whole series,

Reviewed-by: Tomasz Figa t.f...@samsung.com


Thanks Tomasz.

Dear Kukjin,
Can you take these patches.



When I looked at this series quickly, looks good to me but I need to get ack 
from cpuidle maintainer Rafael or Daniel.


Acked the different cpuidle bits.

Thanks
  -- Daniel


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Re: [PATCH v6 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

[Daniel Lezcano]

On 05/16/2014 10:03 AM, Chander Kashyap wrote:

Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com


Acked-by: Daniel Lezcano daniel.lezc...@linaro.org


---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
  drivers/cpuidle/Kconfig.arm |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@

  config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help




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[PATCH] ARM: exynos: Fix kernel panic when unplugging CPU1 on 4210

[Daniel Lezcano]

A look at the code reveals use of S5P_VA_SYSRAM macro, in case of certain SoC
revisions, which is not valid any longer, after SYSRAM started to be mapped
dynamically. The new dynamic mapping is stored in sysram_base_addr variable,
which is declared static in platsmp.c

This fix makes sysram_base_addr non-static, declared it in common.h and used
in pm.c instead of S5P_VA_SYSRAM.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Suggested-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/common.h  |1 +
 arch/arm/mach-exynos/platsmp.c |2 +-
 arch/arm/mach-exynos/pm.c  |4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index e2d0954..a012bc1 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -88,6 +88,7 @@ void mct_init(void __iomem *base, int irq_g0, int irq_l0, int 
irq_l1);
 
 struct map_desc;
 extern void __iomem *sysram_ns_base_addr;
+extern void __iomem *sysram_base_addr;
 void exynos_init_io(void);
 void exynos_restart(enum reboot_mode mode, const char *cmd);
 void exynos_cpuidle_init(void);
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 9c16da2..f2bea78 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,7 +32,7 @@
 
 extern void exynos4_secondary_startup(void);
 
-static void __iomem *sysram_base_addr;
+void __iomem *sysram_base_addr;
 void __iomem *sysram_ns_base_addr;
 
 static void __init exynos_smp_prepare_sysram(void)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index d10c351..87c0d34 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -168,10 +168,10 @@ int exynos_cluster_power_state(int cluster)
 
 #define EXYNOS_BOOT_VECTOR_ADDR(samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+   (sysram_base_addr + 0x24) : S5P_INFORM0))
 #define EXYNOS_BOOT_VECTOR_FLAG(samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+   (sysram_base_addr + 0x20) : S5P_INFORM1))
 
 #define S5P_CHECK_AFTR  0xFCBA0D10
 #define S5P_CHECK_SLEEP 0x0BAD
-- 
1.7.9.5

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Re: [PATCH] ARM: exynos: Fix kernel panic when unplugging CPU1 on 4210

[Daniel Lezcano]

On 05/24/2014 07:24 PM, Daniel Lezcano wrote:

A look at the code reveals use of S5P_VA_SYSRAM macro, in case of certain SoC
revisions, which is not valid any longer, after SYSRAM started to be mapped
dynamically. The new dynamic mapping is stored in sysram_base_addr variable,
which is declared static in platsmp.c

This fix makes sysram_base_addr non-static, declared it in common.h and used
in pm.c instead of S5P_VA_SYSRAM.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Suggested-by: Tomasz Figa t.f...@samsung.com


Hi Kukjin,

with this fix I confirm cpuidle is working well with the AFTR state on 
the exynos 4210.


Regards
  -- Daniel


---
  arch/arm/mach-exynos/common.h  |1 +
  arch/arm/mach-exynos/platsmp.c |2 +-
  arch/arm/mach-exynos/pm.c  |4 ++--
  3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index e2d0954..a012bc1 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -88,6 +88,7 @@ void mct_init(void __iomem *base, int irq_g0, int irq_l0, int 
irq_l1);

  struct map_desc;
  extern void __iomem *sysram_ns_base_addr;
+extern void __iomem *sysram_base_addr;
  void exynos_init_io(void);
  void exynos_restart(enum reboot_mode mode, const char *cmd);
  void exynos_cpuidle_init(void);
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 9c16da2..f2bea78 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,7 +32,7 @@

  extern void exynos4_secondary_startup(void);

-static void __iomem *sysram_base_addr;
+void __iomem *sysram_base_addr;
  void __iomem *sysram_ns_base_addr;

  static void __init exynos_smp_prepare_sysram(void)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index d10c351..87c0d34 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -168,10 +168,10 @@ int exynos_cluster_power_state(int cluster)

  #define EXYNOS_BOOT_VECTOR_ADDR   (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+   (sysram_base_addr + 0x24) : S5P_INFORM0))
  #define EXYNOS_BOOT_VECTOR_FLAG   (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+   (sysram_base_addr + 0x20) : S5P_INFORM1))

  #define S5P_CHECK_AFTR  0xFCBA0D10
  #define S5P_CHECK_SLEEP 0x0BAD




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Re: [PATCH V5 00/20] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle

[Daniel Lezcano]

On 05/22/2014 08:35 PM, Kukjin Kim wrote:

On 04/26/14 20:05, Kukjin Kim wrote:

Tomasz Figa wrote:


On 14.04.2014 11:01, Daniel Lezcano wrote:


Hi Kukjin,

I believe I addressed all the comments. Is it possible to take this
patchset for next ?



Sure ;-)


+1.

Also when applying you might add

Reviewed-by: Tomasz Figat.f...@samsung.com

to any patches that don't have it yet.


Tomasz, thanks for your review.

I will take this series, moving exynos-cpuidle into drivers/cpuidle
into samsung tree if Rafael is OK on that.


Daniel,

Can you please check/test the functionality your series with using my
for-next because there were merge conflicts with mcpm-exynos stuff...?


Hi Kukjin,

I tested the latest tree. Unfortunately it panics when unplugging cpu1:

[3.124189] Unable to handle kernel paging request at virtual address 
f8400024

[3.129950] pgd = c0004000
[3.132626] [f8400024] *pgd=6f7f7841, *pte=, *ppte=
[3.138877] Internal error: Oops: 827 [#1] PREEMPT SMP ARM
[3.192782] r3 : f8400024  r2 : f8180800  r1 : ee836e44  r0 : f8400024
[3.199293] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM 
Segment kernel

[3.206673] Control: 10c5387d  Table: 6e37c04a  DAC: 0015
[3.212398] Process swapper/0 (pid: 0, stack limit = 0xc0510240)
[3.218388] Stack: (0xc0511ef4 to 0xc0512000)
[3.222728] 1ee0: 0030 c02b20f8 ee836e40
[3.230894] 1f00: c001234c 6e88 c0511f34 40018a80  
  0015
[3.239053] 1f20: 4000404a 10c5387d 0041 00f0  
 c02b20e4 edc4a540
[3.247212] 1f40: c038dacc eefc5cf8 c050ecf0 c0543210  
c0012460 0001 c0543210
[3.255371] 1f60: eefc5cf8 c02b2148 b9f92927  c054326c 
c02b0968 b9f92927 
[3.263530] 1f80: c051 c0518480 c038dacc c051 c051 
c0518480 c038dacc eefc5cf8
[3.271689] 1fa0: c0543210 c004e990 c0511fb4 c03873b8  
c04f90c8  c04d4b18
[3.279848] 1fc0:   c04d457c   
c04f90c8  10c5387d
[3.288007] 1fe0: c0518410 c04f90c4 c051bd5c 4000406a  
40008074  
[3.296184] [c0019c5c] (exynos_enter_aftr) from [c02b20f8] 
(idle_finisher+0x14/0x20)
[3.304247] [c02b20f8] (idle_finisher) from [c001234c] 
(cpu_suspend_abort+0x0/0x14)

[3.312226] [c001234c] (cpu_suspend_abort) from [] (  (null))
[3.318994] Code: e34f3840 e3500010 11a2 01a3 (e5804000)
[3.325069] ---[ end trace fca911f75a18c040 ]---


After git bisecting I falls on this commit:

commit b3205dea8fbf6db9b1e46a0dad19a0712fdff44f
Author: Sachin Kamat sachin.ka...@linaro.org
Date:   Tue May 13 07:13:44 2014 +0900

ARM: EXYNOS: Map SYSRAM through generic DT bindings

Instead of hardcoding the SYSRAM details for each SoC,
pass this information through device tree (DT) and make
the code SoC agnostic. Generic DT SRAM bindings are
used for achieving this.

Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com


... which is before my series is applied.

So I am not able to tell yet if my series is correctly rebased or not.

And before someone asks me, yes I updated the dtb :)



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Re: [PATCH V5 00/20] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle

[Daniel Lezcano]

On 05/22/2014 08:35 PM, Kukjin Kim wrote:

On 04/26/14 20:05, Kukjin Kim wrote:

Tomasz Figa wrote:


On 14.04.2014 11:01, Daniel Lezcano wrote:


Hi Kukjin,

I believe I addressed all the comments. Is it possible to take this
patchset for next ?



Sure ;-)


+1.

Also when applying you might add

Reviewed-by: Tomasz Figat.f...@samsung.com

to any patches that don't have it yet.


Tomasz, thanks for your review.

I will take this series, moving exynos-cpuidle into drivers/cpuidle
into samsung tree if Rafael is OK on that.


Daniel,

Can you please check/test the functionality your series with using my
for-next because there were merge conflicts with mcpm-exynos stuff...?


Sure, will do that tomorrow.


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Re: [PATCH V5 18/20] ARM: exynos: cpuidle: Pass the AFTR callback to the platform_data

[Daniel Lezcano]

On 05/15/2014 10:40 PM, Kukjin Kim wrote:

[ ... ]


Exynos cpuidle is not a device on the SoC, so I don't think there is
any
way to represent it in DT. The only thing I could see this is matching
root node with a central SoC driver that instantiates specific
subdevices, such as cpufreq and cpuidle, but I don't see any available
infrastructure for this.


There is a RFC for defining generic idle states [1].

The idea behind using the platform driver framework is to unify the code
across the different drivers and separate the PM / cpuidle code.

By this way, we can move the different drivers to drivers/cpuidle and
store them in a single place. That make easier the tracking, the review
and the maintenance.

I am ok to by using platform_device_register_resndata() but I would
prefer to do that a bit later by converting the other drivers too. That
will be easier if we have them grouped in a single directory (this is
what does this patchset at the end).

As there are some more work based on this patchset and the link error
could be fixed as an independent patch, I would recommend to
re-integrate it in the tree as asked by Bartlomiej.


In general, it would be nice to have everything done properly, but I'd
consider Daniel's series as a huge improvement already and a nice
intermediate step towards further clean-up.

So based on the comments quoted above, instead of stalling the
development, I'd suggest to accept this series and then move forward.


I'm fine.

Arnd, how about you?

- Kukjin


Arnd ?


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Re: [PATCH V5 18/20] ARM: exynos: cpuidle: Pass the AFTR callback to the platform_data

[Daniel Lezcano]

On 05/21/2014 10:10 AM, Arnd Bergmann wrote:

On Wednesday 21 May 2014 09:15:34 Daniel Lezcano wrote:

On 05/15/2014 10:40 PM, Kukjin Kim wrote:

[ ... ]


Exynos cpuidle is not a device on the SoC, so I don't think there is
any
way to represent it in DT. The only thing I could see this is matching
root node with a central SoC driver that instantiates specific
subdevices, such as cpufreq and cpuidle, but I don't see any available
infrastructure for this.


There is a RFC for defining generic idle states [1].

The idea behind using the platform driver framework is to unify the code
across the different drivers and separate the PM / cpuidle code.

By this way, we can move the different drivers to drivers/cpuidle and
store them in a single place. That make easier the tracking, the review
and the maintenance.


Yes, that would be great. I only looked briefly at the series now, doesn't
that require the use of psci?


No, because PSCI is for some specific platform (eg. calxeda), all the 
other drivers are legacy and manually handling the PM via some low level 
callbacks. This is why all drivers were implemented all over the place 
making so difficult to maintain them. Little by little, we split the PM 
callbacks from the idle algorithm so reducing the platform dependency 
with the generic code.


The PSCI implements such PM callbacks in the firmware directly and are 
accessed through an API. PSCI is, let's say some kindof nextgen cpuidle. 
It is similar than mwait on Intel. But if a new platform does not have 
such firmware, then the cpuidle driver will have the legacy format.



That's not a bad idea of course, but it
doesn't solve the problem I raised here.


I am ok to by using platform_device_register_resndata() but I would
prefer to do that a bit later by converting the other drivers too. That
will be easier if we have them grouped in a single directory (this is
what does this patchset at the end).

As there are some more work based on this patchset and the link error
could be fixed as an independent patch, I would recommend to
re-integrate it in the tree as asked by Bartlomiej.


In general, it would be nice to have everything done properly, but I'd
consider Daniel's series as a huge improvement already and a nice
intermediate step towards further clean-up.

So based on the comments quoted above, instead of stalling the
development, I'd suggest to accept this series and then move forward.


I'm fine.

Arnd, how about you?

- Kukjin


Arnd ?


Sorry for the delay.


No problem.


Yes, let's do it this way once more, but please
come up with something better for the future that doesn't tie the
cpuidle method to the root compatible string as this does.


ok.

Thanks

  -- Daniel

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Re: [PATCH 4/7] ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines

[Daniel Lezcano]

On 05/05/2014 12:57 PM, Bartlomiej Zolnierkiewicz wrote:

Replace EXYNOS_BOOT_VECTOR_ADDR and EXYNOS_BOOT_VECTOR_FLAG macros
by exynos_boot_vector_addr() and exynos_boot_vector_flag() static
inlines.

This patch shouldn't cause any functionality changes.

Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com


Acked-by: Daniel Lezcano daniel.lezc...@linaro.org


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Re: [PATCH 6/7] ARM: EXYNOS: PM: fix register setup on EXYNOS4x12 for AFTR mode code

[Daniel Lezcano]

On 05/05/2014 12:57 PM, Bartlomiej Zolnierkiewicz wrote:

Add S5P_CENTRAL_SEQ_OPTION register setup for EXYNOS4x12 to AFTR
mode code.  Without this setup AFTR mode doesn't show any benefit
over WFI one.  When this setup is applied AFTR mode reduces power
consumption by ~12% (as measured on Trats2 board).

This change is a preparation for adding secure firmware support to
EXYNOS cpuidle driver.

Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
  arch/arm/mach-exynos/pm.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 18f6bf8..3922968 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -391,6 +391,10 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
case CPU_PM_ENTER:
if (cpu == 0) {
exynos_pm_central_suspend();
+   if (soc_is_exynos4212() || soc_is_exynos4412())
+   __raw_writel(S5P_USE_STANDBY_WFI0 |
+S5P_USE_STANDBY_WFE0,
+S5P_CENTRAL_SEQ_OPTION);


Why not put this code in the exynos_enter_aftr() ?


exynos_cpu_save_register();
}
break;




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Re: [PATCH v5 0/6] add cpuidle support for Exynos5420

[Daniel Lezcano]

On 05/14/2014 10:03 AM, Chander Kashyap wrote:

Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.


Hi Chander,

just a side question. I am not succeeding to have both cluster A7/A15 
with the upstream kernel.


How can I test your driver ?

Did I miss something ?

Thanks
  -- Daniel


Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/cpuidle.c   |3 +++
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 2 deletions(-)




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Re: [PATCH V5 18/20] ARM: exynos: cpuidle: Pass the AFTR callback to the platform_data

[Daniel Lezcano]

On 05/09/2014 02:02 PM, Tomasz Figa wrote:

Hi Arnd,

On 09.05.2014 12:56, Arnd Bergmann wrote:

On Friday 11 April 2014, Daniel Lezcano wrote:

No more dependency on the arch code. The platform_data field is used to set the
PM callback as the other cpuidle drivers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com


This has just shown up in linux-next and broken randconfig builds.


diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fe8dac8..d22f0e4 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -221,8 +221,9 @@ void exynos_restart(enum reboot_mode mode, const char *cmd)
  }

  static struct platform_device exynos_cpuidle = {
-   .name   = exynos_cpuidle,
-   .id = -1,
+   .name  = exynos_cpuidle,
+   .dev.platform_data = exynos_enter_aftr,
+   .id= -1,
  };



This is wrong on many levels, can we please do this properly?

* The exynos_enter_aftr function is compiled conditionally, so you can't just
   reference it from generic code, or you get a link error.


+1


That is true but still we have a link error without this patch. We 
shouldn't register and declare this structure if CONFIG_PM / 
CONFIG_CPU_IDLE are not set.



* 'static struct platform_device ...' has been deprecated for at least a decade,
   stop doing that. For any platform devices that get registered, there is
   platform_device_register_simple().


+0.5

The missing 0.5 is because you can't pass platform data using
platform_device_register_simple(). There is
platform_device_register_resndata(), though.


* There shouldn't need to be a platform_device to start with, this should all
   come from DT. We can't do this on arm64 anyway, so any code that may be
   shared between arm32 and arm64 should have proper abstractions.


-1

Exynos cpuidle is not a device on the SoC, so I don't think there is any
way to represent it in DT. The only thing I could see this is matching
root node with a central SoC driver that instantiates specific
subdevices, such as cpufreq and cpuidle, but I don't see any available
infrastructure for this.


There is a RFC for defining generic idle states [1].

The idea behind using the platform driver framework is to unify the code 
across the different drivers and separate the PM / cpuidle code.


By this way, we can move the different drivers to drivers/cpuidle and 
store them in a single place. That make easier the tracking, the review 
and the maintenance.


I am ok to by using platform_device_register_resndata() but I would 
prefer to do that a bit later by converting the other drivers too. That 
will be easier if we have them grouped in a single directory (this is 
what does this patchset at the end).


As there are some more work based on this patchset and the link error 
could be fixed as an independent patch, I would recommend to 
re-integrate it in the tree as asked by Bartlomiej.


Thanks
  -- Daniel


[1] http://www.spinics.net/lists/arm-kernel/msg328747.html


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Re: [PATCH] ARM: exynos: register sched_clock callback

[Daniel Lezcano]

On 04/24/2014 11:21 AM, Vincent Guittot wrote:

Use the clocksource mct-frc for sched_clock

Signed-off-by: Vincent Guittot vincent.guit...@linaro.org


Acked-by: Daniel Lezcano daniel.lezc...@linaro.org

[ ... ]

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Re: [PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

[Daniel Lezcano]

On 04/24/2014 07:42 PM, Tomasz Figa wrote:

Hi Daniel,

Please see my comments inline.


Hi Tomasz,


Btw. Please fix your e-mail composer to properly wrap your messages
around 7xth column, as otherwise they're hard to read.


Well it is already set to the 71th column.


On 04.04.2014 11:48, Daniel Lezcano wrote:

The following driver is for exynos4210. I did not yet finished the
other boards, so
I created a specific driver for 4210 which could be merged later.

The driver is based on Colin Cross's driver found at:

https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9a4dfa3b393a010%5E%5E!/


This one was based on a 3.4 kernel and an old API.

It has been refreshed, simplified and based on the recent code cleanup
I sent
today.

The AFTR could be entered when all the cpus (except cpu0) are down. In
order to
reach this situation, the couple idle states are used.

There is a sync barrier at the entry and the exit of the low power
function. So
all cpus will enter and exit the function at the same time.

At this point, CPU0 knows the other cpu will power down itself. CPU0
waits for
the CPU1 to be powered down and then initiate the AFTR power down
sequence.

No interrupts are handled by CPU1, this is why we switch to the timer
broadcast
even if the local timer is not impacted by the idle state.

When CPU0 wakes up, it powers up CPU1 and waits for it to boot. Then
they both
exit the idle function.

This driver allows the exynos4210 to have the same power consumption
at idle
time than the one when we have to unplug CPU1 in order to let CPU0 to
reach
the AFTR state.

This patch is a RFC because, we have to find a way to remove the macros
definitions and cpu powerdown function without pulling the arch dependent
headers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
  arch/arm/mach-exynos/common.c|   11 +-
  drivers/cpuidle/Kconfig.arm  |8 ++
  drivers/cpuidle/Makefile |1 +
  drivers/cpuidle/cpuidle-exynos4210.c |  226
++
  4 files changed, 245 insertions(+), 1 deletion(-)
  create mode 100644 drivers/cpuidle/cpuidle-exynos4210.c

diff --git a/arch/arm/mach-exynos/common.c
b/arch/arm/mach-exynos/common.c
index d5fa21e..1765a98 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -299,9 +299,18 @@ static struct platform_device exynos_cpuidle = {
  .id= -1,
  };

+static struct platform_device exynos4210_cpuidle = {
+.name  = exynos4210-cpuidle,
+.dev.platform_data = exynos_sys_powerdown_aftr,
+.id= -1,
+};
+
  void __init exynos_cpuidle_init(void)
  {
-platform_device_register(exynos_cpuidle);
+if (soc_is_exynos4210())
+platform_device_register(exynos4210_cpuidle);
+else
+platform_device_register(exynos_cpuidle);
  }

  void __init exynos_cpufreq_init(void)
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 92f0c12..2772130 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -51,3 +51,11 @@ config ARM_EXYNOS_CPUIDLE
  depends on ARCH_EXYNOS
  help
Select this to enable cpuidle for Exynos processors
+
+config ARM_EXYNOS4210_CPUIDLE
+bool Cpu Idle Driver for the Exynos 4210 processor
+default y
+depends on ARCH_EXYNOS
+select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+help
+  Select this to enable cpuidle for the Exynos 4210 processors
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 0d1540a..e0ec9bc 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE)+= cpuidle-zynq.o
  obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o
  obj-$(CONFIG_ARM_AT91_CPUIDLE)  += cpuidle-at91.o
  obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)+= cpuidle-exynos.o
+obj-$(CONFIG_ARM_EXYNOS4210_CPUIDLE)+= cpuidle-exynos4210.o


###

  # POWERPC drivers
diff --git a/drivers/cpuidle/cpuidle-exynos4210.c
b/drivers/cpuidle/cpuidle-exynos4210.c
new file mode 100644
index 000..56f6d51
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-exynos4210.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *http://www.samsung.com
+ *
+ * Copyright (c) 2014 Linaro : Daniel Lezcano
daniel.lezc...@linaro.org
+ *http://www.linaro.org
+ *
+ * Based on the work of Colin Cross ccr...@android.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/cpuidle.h
+#include linux/cpu_pm.h
+#include linux/io.h
+#include linux/platform_device.h
+
+#include asm/proc-fns.h
+#include asm/suspend.h
+#include asm/cpuidle.h
+
+#include plat/pm.h
+#include plat/cpu.h
+#include plat/map-base.h

Re: [PATCH 0/2] Add generic cpu power control functions for exynos

[Daniel Lezcano]

Hi Abhilash and Leela,

FYI I think you are working on similar patches.

On 04/24/2014 11:31 AM, Leela Krishna Amudala wrote:
 This patchset adds the generic cpu power control functions for

exynos based SoCs to power up/down and to know the status of the cpu.

Note: This series has been rebased on 3.15-rc1 and tested on
Exynos based Origen(Cortex-A9) and Arndale-octa(Cortex A7,A15) boards.

Leela Krishna Amudala (2):
   ARM: EXYNOS: Add generic cpu power control functions for all exynos
 based SoCs
   ARM: EXYNOS: use generic exynos cpu power control functions

  arch/arm/mach-exynos/common.h   |3 +++
  arch/arm/mach-exynos/platsmp.c  |9 +++--
  arch/arm/mach-exynos/pm.c   |   36 
  arch/arm/mach-exynos/regs-pmu.h |6 ++
  4 files changed, 48 insertions(+), 6 deletions(-)




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Re: [PATCH 3/4] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

[Daniel Lezcano]

On 04/21/2014 01:49 PM, Chander Kashyap wrote:

Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---


Acked-by: Daniel Lezcano daniel.lezc...@linaro.org

but will conflict with:

http://www.spinics.net/lists/arm-kernel/msg319862.html


  arch/arm/mach-exynos/cpuidle.c |3 +++
  1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index c57cae0..242f75d 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -219,6 +219,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
int cpu_id, ret;
struct cpuidle_device *device;

+   if (soc_is_exynos5420())
+   return -ENODEV;
+
if (soc_is_exynos5250())
exynos5_core_down_clk();





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Re: [PATCH 2/4] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

[Daniel Lezcano]

On 04/21/2014 01:49 PM, Chander Kashyap wrote:

Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.org
---


To be migrated to platform_driver but until that:

Acked-by: Daniel Lezcano daniel.lezc...@linaro.org


  drivers/cpuidle/cpuidle-big_little.c |3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..d0fac53 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -170,7 +170,8 @@ static int __init bl_idle_init(void)
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7) 
+   (!of_machine_is_compatible(samsung,exynos5420)))
return -ENODEV;
/*
 * For now the differentiation between little and big cores




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Re: [PATCH 1/4] cpuidle: config: Add SOC_EXYNOS5420 entry to select cpuidle-big-little driver

[Daniel Lezcano]

On 04/21/2014 01:49 PM, Chander Kashyap wrote:

Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores.
In order to use generic cpuidle-big-little driver, this patch adds Exynos5420
specific check to initialize generic cpuidle driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
  drivers/cpuidle/Kconfig.arm |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..5244d87 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@

  config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || SOC_EXYNOS5420


For the sake of consistency, I would prefer:

depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS

and let the current code (and future platform driver) to handle the 
loading of the driver.



select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help




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Re: [PATCH 4/4] mcpm: exynos: populate suspend and powered_up callbacks

[Daniel Lezcano]

On 04/21/2014 01:49 PM, Chander Kashyap wrote:

In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
  arch/arm/mach-exynos/mcpm-exynos.c |   53 
  1 file changed, 53 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index 46d4968..16af0bd 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -318,10 +318,63 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return 0; /* success: the CPU is halted */
  }

+static void enable_coherency(void)
+{
+   unsigned long v, u;
+
+   asm volatile(
+   mrc   p15, 0, %0, c1, c0, 1\n
+   orr   %0, %0, %2\n
+   ldr   %1, [%3]\n
+   and   %1, %1, #0\n
+   orr   %0, %0, %1\n
+   mcr   p15, 0, %0, c1, c0, 1\n
+   : =r (v), =r (u)
+   : Ir (0x40), Ir (S5P_INFORM0)
+   : cc);
+}


Shouldn't this function to be used from hotplug.c also ?


+
+void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(bl_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(bl_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   mpidr = read_cpuid_mpidr();
+   cpunr = enynos_pmu_cpunr(mpidr);


*enynos*_pmu_cpunr ?


+
+   __raw_writel(virt_to_phys(mcpm_entry_point), REG_ENTRY_ADDR);
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+   */
+   __raw_writel(EXYNOS_CORE_LOCAL_PWR_EN,
+   EXYNOS_ARM_CORE_CONFIGURATION(cpunr));


Why don't you use the functions defined in the

patch 5/5 arm: exynos: Add MCPM call-back functions

exynos_core_power_control() ?


+   set_cr(get_cr() | CR_C);
+   enable_coherency();
+}
+
  static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
  };

  static void __init exynos_mcpm_usage_count_init(void)




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Re: [PATCH 2/4] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

[Daniel Lezcano]

On 04/21/2014 01:49 PM, Chander Kashyap wrote:

Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.org
---
  drivers/cpuidle/cpuidle-big_little.c |3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..d0fac53 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -170,7 +170,8 @@ static int __init bl_idle_init(void)
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7) 
+   (!of_machine_is_compatible(samsung,exynos5420)))
return -ENODEV;
/*
 * For now the differentiation between little and big cores


BTW, are the latencies the same than the TC2 ?


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Re: [PATCH] ARM: EXYNOS: cpu hotplug: use v7_exit_coherency_flush macro for cache disabling

[Daniel Lezcano]

On 04/22/2014 04:18 PM, Leela Krishna Amudala wrote:

Remove the duplicated code for cache disabling and use v7_exit_coherency_flush
macro to do the same job.


Hi Leela,

thanks for this patch! It would be nice if you can describe why those 
macros can be replaced by the generic v7_exit_coherency_flush macro.




Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org

---
cpu hotplug is tested with 3.15-rc1 on Origen(which has cortex A9) and
Arndale octa(which has cortex A7 and A15) boards.

  arch/arm/mach-exynos/hotplug.c |   56 ++--
  1 file changed, 2 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..9eb8d1b 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -24,56 +24,6 @@
  #include common.h
  #include regs-pmu.h

-static inline void cpu_enter_lowpower_a9(void)
-{
-   unsigned int v;
-
-   asm volatile(
- mcr p15, 0, %1, c7, c5, 0\n
- mcr p15, 0, %1, c7, c10, 4\n
-   /*
-* Turn off coherency
-*/
- mrc p15, 0, %0, c1, c0, 1\n
- bic %0, %0, %3\n
- mcr p15, 0, %0, c1, c0, 1\n
- mrc p15, 0, %0, c1, c0, 0\n
- bic %0, %0, %2\n
- mcr p15, 0, %0, c1, c0, 0\n
- : =r (v)
- : r (0), Ir (CR_C), Ir (0x40)
- : cc);
-}
-
-static inline void cpu_enter_lowpower_a15(void)
-{
-   unsigned int v;
-
-   asm volatile(
- mrc p15, 0, %0, c1, c0, 0\n
- bic %0, %0, %1\n
- mcr p15, 0, %0, c1, c0, 0\n
- : =r (v)
- : Ir (CR_C)
- : cc);
-
-   flush_cache_louis();
-
-   asm volatile(
-   /*
-   * Turn off coherency
-   */
- mrc p15, 0, %0, c1, c0, 1\n
- bic %0, %0, %1\n
- mcr p15, 0, %0, c1, c0, 1\n
-   : =r (v)
-   : Ir (0x40)
-   : cc);
-
-   isb();
-   dsb();
-}
-
  static inline void cpu_leave_lowpower(void)
  {
unsigned int v;
@@ -141,10 +91,8 @@ void __ref exynos_cpu_die(unsigned int cpu)
 * appropriate sequence for entering low power.
 */
asm(mrc p15, 0, %0, c0, c0, 0 : =r(primary_part) : : cc);


Can't you remove this asm line above as well as the primary_part variable ?


-   if ((primary_part  0xfff0) == 0xc0f0)
-   cpu_enter_lowpower_a15();
-   else
-   cpu_enter_lowpower_a9();
+
+   v7_exit_coherency_flush(louis);

platform_do_lowpower(cpu, spurious);





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Re: [PATCH 1/3] clocksource: exynos_mct: Fix stall after CPU hotplugging

[Daniel Lezcano]

On 04/15/2014 11:34 AM, Krzysztof Kozlowski wrote:

On pią, 2014-03-28 at 14:06 +0100, Krzysztof Kozlowski wrote:

Fix stall after hotplugging CPU1. Affected are SoCs where Multi Core Timer
interrupts are shared (SPI), e.g. Exynos 4210. The stall was a result of
starting the CPU1 local timer not in L1 timer but in L0 (which is used
by CPU0).


Hi,

Do you have any comments on these 3 patches? They fix the CPU stall on
Exynos4210 and also on Exynos3250 (Chanwoo Choi sent patches for it
recently).


You describe this issue as impacting different SoC not only the exynos, 
right ?


Do you know what other SoCs are impacted by this ?

I guess this issue is not reproducible just with the line below, we need 
a timer to expire right at the moment CPU1 is hotplugged, right ?



Trigger:
$ echo 0  /sys/bus/cpu/devices/cpu1/online  echo 1  
/sys/bus/cpu/devices/cpu1/online

Stall information:
[  530.045259] INFO: rcu_preempt detected stalls on CPUs/tasks:
[  530.045618]  1: (6 GPs behind) idle=6d0/0/0 softirq=369/369
[  530.050987]  (detected by 0, t=6589 jiffies, g=33, c=32, q=0)
[  530.056721] Task dump for CPU 1:
[  530.059928] swapper/1   R running  0 0  1 0x1000
[  530.066377] [c0524e14] (__schedule+0x414/0x9b4) from [c00b6610] 
(rcu_idle_enter+0x18/0x38)
[  530.074955] [c00b6610] (rcu_idle_enter+0x18/0x38) from [c0079a18] 
(cpu_startup_entry+0x60/0x3bc)
[  530.084069] [c0079a18] (cpu_startup_entry+0x60/0x3bc) from [c0517d34] 
(secondary_start_kernel+0x164/0x1a0)
[  530.094029] [c0517d34] (secondary_start_kernel+0x164/0x1a0) from 
[40517244] (0x40517244)

The timers for CPU1 were missed:
[  591.668436] cpu: 1
[  591.670430]  clock 0:
[  591.672691]   .base:   c0ab7750
[  591.676160]   .index:  0
[  591.679025]   .resolution: 1 nsecs
[  591.682404]   .get_time:   ktime_get
[  591.685970]   .offset: 0 nsecs
[  591.689349] active timers:
[  591.692045]  #0: dfb51f40, hrtimer_wakeup, S:01
[  591.696759]  # expires at 454687834257-454687884257 nsecs [in -136770537232 
to -136770487232 nsecs]

And the event_handler for next event was wrong:
[  591.917120] Tick Device: mode: 1
[  591.920676] Per CPU device: 0
[  591.923621] Clock Event Device: mct_tick0
[  591.927623]  max_delta_ns:   178956969027
[  591.931613]  min_delta_ns:   1249
[  591.934913]  mult:   51539608
[  591.938557]  shift:  32
[  591.941681]  mode:   3
[  591.944724]  next_event: 59502500 nsecs
[  591.949227]  set_next_event: exynos4_tick_set_next_event
[  591.954522]  set_mode:   exynos4_tick_set_mode
[  591.959296]  event_handler:  hrtimer_interrupt
[  591.963730]  retries:0
[  591.966761]
[  591.968245] Tick Device: mode: 0
[  591.971801] Per CPU device: 1
[  591.974746] Clock Event Device: mct_tick1
[  591.978750]  max_delta_ns:   178956969027
[  591.982739]  min_delta_ns:   1249
[  591.986037]  mult:   51539608
[  591.989681]  shift:  32
[  591.992806]  mode:   3
[  591.995848]  next_event: 45368500 nsecs
[  592.000353]  set_next_event: exynos4_tick_set_next_event
[  592.005648]  set_mode:   exynos4_tick_set_mode
[  592.010421]  event_handler:  tick_handle_periodic
[  592.015115]  retries:0
[  592.018145]

After turning off the CPU1, the MCT L1 local timer was disabled but the
interrupt was not cleared. Turning on the CPU1 enabled the IRQ
with setup_irq() but, before setting affinity to CPU1, the pending L1 timer
interrupt was processed by CPU0 in exynos4_mct_tick_isr().

The ISR then called event handler which set up the next timer event for
current CPU (CPU0). Therefore the MCT L1 timer wasn't actually started.

Fix the stall by:
1. Setting next timer event not on current CPU but on the CPU indicated
by cpumask in 'clock_event_device'.
2. Clearing the timer interrupt upon stopping the local timer.

The patch also moves around the call to exynos4_mct_tick_stop() but this
is done only for the code readability as it is not essential for the fix.

Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: sta...@vger.kernel.org
---
  drivers/clocksource/exynos_mct.c |   33 -
  1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 48f76bc05da0..0b49b09dd1a9 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -339,7 +339,14 @@ static void exynos4_mct_tick_start(unsigned long cycles,
  static int exynos4_tick_set_next_event(unsigned long cycles,
   struct clock_event_device *evt)
  {
-   struct mct_clock_event_device *mevt = this_cpu_ptr(percpu_mct_tick);
+   /*
+* In case of hotplugging non-boot CPU, the set_next_event could be
+* called on CPU0 by ISR before IRQ affinity is set to proper CPU.
+* Thus for accessing proper MCT Lx timer, 'per_cpu' for cpumask
+* in event must be used instead of 

Re: [PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

[Daniel Lezcano]

On 04/15/2014 08:37 AM, Lukasz Majewski wrote:

Hi Daniel,


The following driver is for exynos4210. I did not yet finished the
other boards, so I created a specific driver for 4210 which could be
merged later.



If I may ask - do you plan to develop this code for Exynos4412 in a
near future?


Yes it is in my plan.


I did some tests (with hotplug) and it turns out, that due to static
leakage current one can save up to 12 % of power consumption when power
domains for cores are disabled.


Such notable power consumption reduction could drive (and justify) the
further development of power aware scheduling code.

If you don't have time, then I can offer myself to develop the code. I
just want to avoid potential duplication of effort.


I would be very glad if we can cooperate. Thanks for proposing your help.

I have put a branch containing the cleanups + driver moving + dual cpu 
support, so you can base your work in it.


git://git.linaro.org/people/daniel.lezcano/linux.git cpuidle/samsung-next

I am wondering if the 5250 board wouldn't make sense as a primary target 
before the 4412...



The driver is based on Colin Cross's driver found at:

https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9a4dfa3b393a010%5E%5E!/

This one was based on a 3.4 kernel and an old API.

It has been refreshed, simplified and based on the recent code
cleanup I sent today.

The AFTR could be entered when all the cpus (except cpu0) are down.
In order to reach this situation, the couple idle states are used.

There is a sync barrier at the entry and the exit of the low power
function. So all cpus will enter and exit the function at the same
time.

At this point, CPU0 knows the other cpu will power down itself. CPU0
waits for the CPU1 to be powered down and then initiate the AFTR
power down sequence.

No interrupts are handled by CPU1, this is why we switch to the timer
broadcast even if the local timer is not impacted by the idle state.

When CPU0 wakes up, it powers up CPU1 and waits for it to boot. Then
they both exit the idle function.

This driver allows the exynos4210 to have the same power consumption
at idle time than the one when we have to unplug CPU1 in order to let
CPU0 to reach the AFTR state.

This patch is a RFC because, we have to find a way to remove the
macros definitions and cpu powerdown function without pulling the
arch dependent headers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
  arch/arm/mach-exynos/common.c|   11 +-
  drivers/cpuidle/Kconfig.arm  |8 ++
  drivers/cpuidle/Makefile |1 +
  drivers/cpuidle/cpuidle-exynos4210.c |  226
++ 4 files changed, 245
insertions(+), 1 deletion(-) create mode 100644
drivers/cpuidle/cpuidle-exynos4210.c

diff --git a/arch/arm/mach-exynos/common.c
b/arch/arm/mach-exynos/common.c index d5fa21e..1765a98 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -299,9 +299,18 @@ static struct platform_device exynos_cpuidle = {
 .id= -1,
  };

+static struct platform_device exynos4210_cpuidle = {
+   .name  = exynos4210-cpuidle,
+   .dev.platform_data = exynos_sys_powerdown_aftr,
+   .id= -1,
+};
+
  void __init exynos_cpuidle_init(void)
  {
-   platform_device_register(exynos_cpuidle);
+   if (soc_is_exynos4210())
+   platform_device_register(exynos4210_cpuidle);
+   else
+   platform_device_register(exynos_cpuidle);
  }

  void __init exynos_cpufreq_init(void)
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 92f0c12..2772130 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -51,3 +51,11 @@ config ARM_EXYNOS_CPUIDLE
 depends on ARCH_EXYNOS
 help
   Select this to enable cpuidle for Exynos processors
+
+config ARM_EXYNOS4210_CPUIDLE
+   bool Cpu Idle Driver for the Exynos 4210 processor
+   default y
+   depends on ARCH_EXYNOS
+   select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+   help
+ Select this to enable cpuidle for the Exynos 4210 processors
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 0d1540a..e0ec9bc 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE)+=
cpuidle-zynq.o obj-$(CONFIG_ARM_U8500_CPUIDLE) +=
cpuidle-ux500.o obj-$(CONFIG_ARM_AT91_CPUIDLE)  +=
cpuidle-at91.o obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)+=
cpuidle-exynos.o +obj-$(CONFIG_ARM_EXYNOS4210_CPUIDLE)+=
cpuidle-exynos4210.o

  
###
  # POWERPC drivers
diff --git a/drivers/cpuidle/cpuidle-exynos4210.c
b/drivers/cpuidle/cpuidle-exynos4210.c new file mode 100644
index 000..56f6d51
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-exynos4210.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c

Re: [PATCH] Exynos4: cpuidle: support dual CPUs with AFTR state

[Daniel Lezcano]

On 04/15/2014 05:54 PM, Lukasz Majewski wrote:

Hi Daniel,


On 04/15/2014 08:37 AM, Lukasz Majewski wrote:

Hi Daniel,


The following driver is for exynos4210. I did not yet finished the
other boards, so I created a specific driver for 4210 which could
be merged later.



If I may ask - do you plan to develop this code for Exynos4412 in a
near future?


Yes it is in my plan.


I did some tests (with hotplug) and it turns out, that due to static
leakage current one can save up to 12 % of power consumption when
power domains for cores are disabled.


Such notable power consumption reduction could drive (and justify)
the further development of power aware scheduling code.

If you don't have time, then I can offer myself to develop the
code. I just want to avoid potential duplication of effort.


I would be very glad if we can cooperate. Thanks for proposing your
help.


You are welcome :-)



I have put a branch containing the cleanups + driver moving + dual
cpu support, so you can base your work in it.

git://git.linaro.org/people/daniel.lezcano/linux.git
cpuidle/samsung-next


Thanks for sharing code. I will look into it.



I am wondering if the 5250 board wouldn't make sense as a primary
target before the 4412...


I'm working on a device based on 4412, not 5250. Therefore, I would
prefer to have this concept implemented on 4412 as soon as possible to
not hinder my scheduler related experiments.

If you have other priorities, then we can split the work. What do you
think?


It is ok for me if you want to handle the cpuidle driver 4412. Will you 
create a new driver or extend this dual cpu driver to support 4 cpus ?




The driver is based on Colin Cross's driver found at:

https://android.googlesource.com/kernel/exynos/+/e686b1ec67423c40b4fdf811f9a4dfa3b393a010%5E%5E!/

This one was based on a 3.4 kernel and an old API.

It has been refreshed, simplified and based on the recent code
cleanup I sent today.

The AFTR could be entered when all the cpus (except cpu0) are down.
In order to reach this situation, the couple idle states are used.

There is a sync barrier at the entry and the exit of the low power
function. So all cpus will enter and exit the function at the same
time.

At this point, CPU0 knows the other cpu will power down itself.
CPU0 waits for the CPU1 to be powered down and then initiate the
AFTR power down sequence.

No interrupts are handled by CPU1, this is why we switch to the
timer broadcast even if the local timer is not impacted by the
idle state.

When CPU0 wakes up, it powers up CPU1 and waits for it to boot.
Then they both exit the idle function.

This driver allows the exynos4210 to have the same power
consumption at idle time than the one when we have to unplug CPU1
in order to let CPU0 to reach the AFTR state.

This patch is a RFC because, we have to find a way to remove the
macros definitions and cpu powerdown function without pulling the
arch dependent headers.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
   arch/arm/mach-exynos/common.c|   11 +-
   drivers/cpuidle/Kconfig.arm  |8 ++
   drivers/cpuidle/Makefile |1 +
   drivers/cpuidle/cpuidle-exynos4210.c |  226
++ 4 files changed, 245
insertions(+), 1 deletion(-) create mode 100644
drivers/cpuidle/cpuidle-exynos4210.c

diff --git a/arch/arm/mach-exynos/common.c
b/arch/arm/mach-exynos/common.c index d5fa21e..1765a98 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -299,9 +299,18 @@ static struct platform_device exynos_cpuidle
= { .id= -1,
   };

+static struct platform_device exynos4210_cpuidle = {
+   .name  = exynos4210-cpuidle,
+   .dev.platform_data = exynos_sys_powerdown_aftr,
+   .id= -1,
+};
+
   void __init exynos_cpuidle_init(void)
   {
-   platform_device_register(exynos_cpuidle);
+   if (soc_is_exynos4210())
+   platform_device_register(exynos4210_cpuidle);
+   else
+   platform_device_register(exynos_cpuidle);
   }

   void __init exynos_cpufreq_init(void)
diff --git a/drivers/cpuidle/Kconfig.arm
b/drivers/cpuidle/Kconfig.arm index 92f0c12..2772130 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -51,3 +51,11 @@ config ARM_EXYNOS_CPUIDLE
  depends on ARCH_EXYNOS
  help
Select this to enable cpuidle for Exynos processors
+
+config ARM_EXYNOS4210_CPUIDLE
+   bool Cpu Idle Driver for the Exynos 4210 processor
+   default y
+   depends on ARCH_EXYNOS
+   select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+   help
+ Select this to enable cpuidle for the Exynos 4210
processors diff --git a/drivers/cpuidle/Makefile
b/drivers/cpuidle/Makefile index 0d1540a..e0ec9bc 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE)+=
cpuidle-zynq.o obj

Re: [PATCH V5 00/20] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle

[Daniel Lezcano]

Hi Kukjin,

I believe I addressed all the comments. Is it possible to take this 
patchset for next ?


Regards

  -- Daniel



On 04/11/2014 12:39 PM, Daniel Lezcano wrote:

Changelog:

V5:
* Removed patch : Move clock setup to pm.c
* Added patch   : Move arm core power down clock to exynos5250 common 
code
V4:
* Took into account Tomasz's comments
* Fixed missing call in for central suspend
* Passed parameter to the wakeup mask function
* Moved wakeup mask, boot vector and aftr state into a single
function
* Used this function as callback for platform data
* Moved S5P_CHECK_AFTR/S5P_CHECK_SLEEP into pm.c
* Set boot vector only one time
* Splitted some patches to make them more readable
V3:
* Added patch   : ARM: exynos: cpuidle: Disable cpuidle for 5440
* Removed patch : ARM: exynos: config: Enable cpuidle
* Removed default ARM_EXYNOS4210_CPUIDLE=y
* Added comment about bug fix side effect 'for_each_possible_cpu'
V2:
* Added comment in changelog for calls order (5/17)
* Call the powerdown only for cpu0 in the pm notifier
* Set the pm notifier for all boards

V1: initial post

This patchset relies on the cpm_pm notifier to initiate the powerdown sequence
operations from pm.c instead cpuidle.c. Thus the cpuidle driver is no longer
dependent from arch specific code as everything is called from the pm.c file.

The patchset applies on top of linux-samsung/for-next.

Tested on exynos4: 4210
Tested on exynos5: 5250 (without AFTR)

Amit Daniel Kachhap (1):
   ARM: EXYNOS: Move arm core power down clock to exynos5250 common
 clock

Daniel Lezcano (19):
   ARM: exynos: cpuidle: Prevent forward declaration
   ARM: exynos: cpuidle: Use cpuidle_register
   ARM: exynos: cpuidle: Change function name prefix
   ARM: exynos: cpuidle: Encapsulate register access inside a function
   ARM: exynos: cpuidle: Move some code inside the idle_finisher
   ARM: exynos: cpuidle: Fix S5P_WAKEUP_STAT call
   ARM: exynos: cpuidle: Use the cpu_pm notifier
   ARM: exynos: cpuidle: Move scu_enable in the cpu_pm notifier
   ARM: exynos: cpuidle: Remove ifdef for scu_enable
   ARM: exynos: cpuidle: Pass wakeup mask parameter to function
   ARM: exynos: cpuidle: Encapsulate boot vector code into a function
   ARM: exynos: cpuidle: Disable cpuidle for 5440
   ARM: exynos: cpuidle: Encapsulate the AFTR code into a function
   ARM: exynos: cpuidle: Move the AFTR state function into pm.c
   ARM: exynos: cpuidle: Move the power sequence call in the cpu_pm
 notifier
   ARM: exynos: cpuidle: Move S5P_CHECK_SLEEP into pm.c
   ARM: exynos: cpuidle: Pass the AFTR callback to the platform_data
   ARM: exynos: cpuidle: Cleanup all unneeded headers from cpuidle.c
   ARM: exynos: cpuidle: Move the driver to drivers/cpuidle directory

  arch/arm/mach-exynos/Makefile|1 -
  arch/arm/mach-exynos/common.h|1 +
  arch/arm/mach-exynos/cpuidle.c   |  255 --
  arch/arm/mach-exynos/exynos.c|8 +-
  arch/arm/mach-exynos/pm.c|  152 
  arch/arm/mach-exynos/regs-pmu.h  |2 -
  drivers/clk/samsung/clk-exynos5250.c |   42 ++
  drivers/cpuidle/Kconfig.arm  |6 +
  drivers/cpuidle/Makefile |1 +
  drivers/cpuidle/cpuidle-exynos.c |   98 +
  10 files changed, 277 insertions(+), 289 deletions(-)
  delete mode 100644 arch/arm/mach-exynos/cpuidle.c
  create mode 100644 drivers/cpuidle/cpuidle-exynos.c




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Re: [PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c

[Daniel Lezcano]

On 04/10/2014 05:34 PM, Tomasz Figa wrote:

On 10.04.2014 16:23, Daniel Lezcano wrote:

On 04/10/2014 03:57 PM, Tomasz Figa wrote:

Hi Daniel,

On 10.04.2014 11:55, Daniel Lezcano wrote:

One more step is moving the clock ratio setting at idle time in pm.c

The macro names have been changed to be consistent with the other
macros
name in the file.

Note, the clock divider was working only when cpuidle was enabled
because it
was in its init routine. With this change, the clock divider is set in
the pm's
init routine, so it will also operate when the cpuidle driver is not
set, which
is good.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
  arch/arm/mach-exynos/cpuidle.c  |   54
---
  arch/arm/mach-exynos/pm.c   |   35 +
  arch/arm/mach-exynos/regs-pmu.h |   19 ++
  3 files changed, 54 insertions(+), 54 deletions(-)


Sorry that I didn't mention that before, but now I recall that there was
already a similar patch moving this code to Exynos5250 clock driver,
which is the best place for setup of any CMU registers and a step
towards removing one more static IO mapping.


Yes, Bartlomiej mentioned it.

Is it possible to merge this mentioned patch or to give a pointer to it
so I can integrate it into the patchset ?


http://marc.info/?l=linux-arm-kernelm=138147021207626w=2

I wonder if it still applies cleanly, though...


Ok, if I refer to the date, this patch has been lost in the limbus. So I 
can integrate it with my patchset without conflicting with any tree. Right ?


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Re: [PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c

[Daniel Lezcano]

On 04/11/2014 10:49 AM, Tomasz Figa wrote:

On 11.04.2014 10:30, Daniel Lezcano wrote:

On 04/10/2014 05:34 PM, Tomasz Figa wrote:

On 10.04.2014 16:23, Daniel Lezcano wrote:

On 04/10/2014 03:57 PM, Tomasz Figa wrote:

Hi Daniel,

On 10.04.2014 11:55, Daniel Lezcano wrote:

One more step is moving the clock ratio setting at idle time in pm.c

The macro names have been changed to be consistent with the other
macros
name in the file.

Note, the clock divider was working only when cpuidle was enabled
because it
was in its init routine. With this change, the clock divider is
set in
the pm's
init routine, so it will also operate when the cpuidle driver is not
set, which
is good.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
  arch/arm/mach-exynos/cpuidle.c  |   54
---
  arch/arm/mach-exynos/pm.c   |   35 +
  arch/arm/mach-exynos/regs-pmu.h |   19 ++
  3 files changed, 54 insertions(+), 54 deletions(-)


Sorry that I didn't mention that before, but now I recall that there
was
already a similar patch moving this code to Exynos5250 clock driver,
which is the best place for setup of any CMU registers and a step
towards removing one more static IO mapping.


Yes, Bartlomiej mentioned it.

Is it possible to merge this mentioned patch or to give a pointer to it
so I can integrate it into the patchset ?


http://marc.info/?l=linux-arm-kernelm=138147021207626w=2

I wonder if it still applies cleanly, though...


Ok, if I refer to the date, this patch has been lost in the limbus. So I
can integrate it with my patchset without conflicting with any tree.
Right ?



As I suspected, it doesn't apply onto current sources. I have attached a
rebased version. Feel free to send it as a part of next version of your
series.


Thanks Tomasz !



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[PATCH V5 17/20] ARM: exynos: cpuidle: Move S5P_CHECK_SLEEP into pm.c

[Daniel Lezcano]

This macro is only used there.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/pm.c   |3 ++-
 arch/arm/mach-exynos/regs-pmu.h |2 --
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 6d9ef69..b380d48 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -108,7 +108,8 @@ static int exynos_irq_set_wake(struct irq_data *data, 
unsigned int state)
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
 
-#define S5P_CHECK_AFTR 0xFCBA0D10
+#define S5P_CHECK_AFTR  0xFCBA0D10
+#define S5P_CHECK_SLEEP 0x0BAD
 
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 static void exynos_set_wakeupmask(long mask)
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..6c1d2db 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -119,8 +119,6 @@
 #define S5P_CORE_LOCAL_PWR_EN  0x3
 #define S5P_INT_LOCAL_PWR_EN   0x7
 
-#define S5P_CHECK_SLEEP0x0BAD
-
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWRS5P_PMUREG(0x1154)
 #define S5P_CMU_RESET_LCD1_LOWPWR  S5P_PMUREG(0x1174)
-- 
1.7.9.5

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[PATCH V5 15/20] ARM: exynos: cpuidle: Move the AFTR state function into pm.c

[Daniel Lezcano]

In order to remove depedency on pm code, let's move the 'exynos_enter_aftr'
function into the pm.c file as well as the other helper functions.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/common.h  |1 +
 arch/arm/mach-exynos/cpuidle.c |   29 -
 arch/arm/mach-exynos/pm.c  |   29 +
 3 files changed, 30 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83..30123a0 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -62,5 +62,6 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_enter_aftr(void);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index fe35fba..e6d813d 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -30,35 +30,6 @@
 #include common.h
 #include regs-pmu.h
 
-#define REG_DIRECTGO_ADDR  (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-   S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
-#define REG_DIRECTGO_FLAG  (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-   S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
-
-#define S5P_CHECK_AFTR 0xFCBA0D10
-
-/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(long mask)
-{
-   __raw_writel(mask, S5P_WAKEUP_MASK);
-}
-
-static void exynos_cpu_set_boot_vector(long flags)
-{
-   __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
-   __raw_writel(flags, REG_DIRECTGO_FLAG);
-}
-
-static void exynos_enter_aftr(void)
-{
-   exynos_set_wakeupmask(0xff3e);
-   exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
-   /* Set value of power down register for aftr mode */
-   exynos_sys_powerdown_conf(SYS_AFTR);
-}
-
 static int idle_finisher(unsigned long flags)
 {
exynos_enter_aftr();
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 9773a00..50b6b4d 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -101,6 +101,35 @@ static int exynos_irq_set_wake(struct irq_data *data, 
unsigned int state)
return -ENOENT;
 }
 
+#define EXYNOS_BOOT_VECTOR_ADDR(samsung_rev() == EXYNOS4210_REV_1_1 ? \
+   S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+   (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+#define EXYNOS_BOOT_VECTOR_FLAG(samsung_rev() == EXYNOS4210_REV_1_1 ? \
+   S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+   (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+
+#define S5P_CHECK_AFTR 0xFCBA0D10
+
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos_set_wakeupmask(long mask)
+{
+   __raw_writel(mask, S5P_WAKEUP_MASK);
+}
+
+static void exynos_cpu_set_boot_vector(long flags)
+{
+   __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+   __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+}
+
+void exynos_enter_aftr(void)
+{
+   exynos_set_wakeupmask(0xff3e);
+   exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+   /* Set value of power down register for aftr mode */
+   exynos_sys_powerdown_conf(SYS_AFTR);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
-- 
1.7.9.5

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[PATCH V5 09/20] ARM: exynos: cpuidle: Move scu_enable in the cpu_pm notifier

[Daniel Lezcano]

We make the cpuidle code less arch dependent.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/cpuidle.c |6 --
 arch/arm/mach-exynos/pm.c  |4 
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index aa8ab1b..95826c6 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -18,7 +18,6 @@
 #include linux/platform_device.h
 
 #include asm/proc-fns.h
-#include asm/smp_scu.h
 #include asm/suspend.h
 #include asm/unified.h
 #include asm/cpuidle.h
@@ -74,11 +73,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
 
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
-
-#ifdef CONFIG_SMP
-   if (!soc_is_exynos5250())
-   scu_enable(S5P_VA_SCU);
-#endif
cpu_pm_exit();
 
/*
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 67d75fe..aba577f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -336,6 +336,10 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
 
case CPU_PM_EXIT:
if (cpu == 0) {
+#ifdef CONFIG_SMP
+   if (!soc_is_exynos5250())
+   scu_enable(S5P_VA_SCU);
+#endif
exynos_cpu_restore_register();
}
break;
-- 
1.7.9.5

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[PATCH V5 12/20] ARM: exynos: cpuidle: Encapsulate boot vector code into a function

[Daniel Lezcano]

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |   11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 169db74..f66ee4d 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -45,13 +45,16 @@ static void exynos_set_wakeupmask(long mask)
__raw_writel(mask, S5P_WAKEUP_MASK);
 }
 
+static void exynos_cpu_set_boot_vector(long flags)
+{
+   __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
+   __raw_writel(flags, REG_DIRECTGO_FLAG);
+}
+
 static int idle_finisher(unsigned long flags)
 {
exynos_set_wakeupmask(0xff3e);
-
-   __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
-   __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-
+   exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
 
-- 
1.7.9.5

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[PATCH V5 13/20] ARM: exynos: cpuidle: Disable cpuidle for 5440

[Daniel Lezcano]

There is no point to register the cpuidle driver for the 5440 as it has only
one WFI state which is the default idle function when the cpuidle driver is
disabled.

By disabling cpuidle we prevent to enter to the governor computation for
nothing, thus saving a lot of processing time.

The only drawback is the statistic via sysfs on this state which is lost but
it is meaningless and it could be retrieved from the ftrace easily.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Amit Kucheria amit.kuche...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |3 ---
 arch/arm/mach-exynos/exynos.c  |3 +++
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index f66ee4d..95313ea 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -133,9 +133,6 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
 {
int ret;
 
-   if (soc_is_exynos5440())
-   exynos_idle_driver.state_count = 1;
-
ret = cpuidle_register(exynos_idle_driver, NULL);
if (ret) {
dev_err(pdev-dev, failed to register cpuidle driver\n);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b567361..fe8dac8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -227,6 +227,9 @@ static struct platform_device exynos_cpuidle = {
 
 void __init exynos_cpuidle_init(void)
 {
+   if (soc_is_exynos5440())
+   return;
+
platform_device_register(exynos_cpuidle);
 }
 
-- 
1.7.9.5

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[PATCH V5 20/20] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle directory

[Daniel Lezcano]

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/Makefile  |1 -
 drivers/cpuidle/Kconfig.arm|6 ++
 drivers/cpuidle/Makefile   |1 +
 .../cpuidle.c = drivers/cpuidle/cpuidle-exynos.c  |0
 4 files changed, 7 insertions(+), 1 deletion(-)
 rename arch/arm/mach-exynos/cpuidle.c = drivers/cpuidle/cpuidle-exynos.c 
(100%)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index a656dbe..21bd364 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos.o
 
 obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
 
 obj-$(CONFIG_ARCH_EXYNOS)  += pmu.o
 
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index d988948..364c984 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -44,3 +44,9 @@ config ARM_AT91_CPUIDLE
depends on ARCH_AT91
help
  Select this to enable cpuidle for AT91 processors
+
+config ARM_EXYNOS_CPUIDLE
+   bool Cpu Idle Driver for the Exynos processors
+   depends on ARCH_EXYNOS
+   help
+ Select this to enable cpuidle for Exynos processors
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index f71ae1b..0d1540a 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_KIRKWOOD_CPUIDLE)+= cpuidle-kirkwood.o
 obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) += cpuidle-zynq.o
 obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o
 obj-$(CONFIG_ARM_AT91_CPUIDLE)  += cpuidle-at91.o
+obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)+= cpuidle-exynos.o
 
 ###
 # POWERPC drivers
diff --git a/arch/arm/mach-exynos/cpuidle.c b/drivers/cpuidle/cpuidle-exynos.c
similarity index 100%
rename from arch/arm/mach-exynos/cpuidle.c
rename to drivers/cpuidle/cpuidle-exynos.c
-- 
1.7.9.5

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[PATCH V5 08/20] ARM: exynos: cpuidle: Use the cpu_pm notifier

[Daniel Lezcano]

Use the cpu_pm_enter/exit notifier to group some pm code inside the pm file.

The save and restore code is duplicated across pm.c and cpuidle.c. By using
the cpu_pm notifier, we can factor out the routine.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/cpuidle.c |   24 
 arch/arm/mach-exynos/pm.c  |   29 +
 2 files changed, 29 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 346c2d0..aa8ab1b 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -46,26 +46,6 @@ static void exynos_set_wakeupmask(void)
__raw_writel(0xff3e, S5P_WAKEUP_MASK);
 }
 
-static unsigned int g_pwr_ctrl, g_diag_reg;
-
-static void save_cpu_arch_register(void)
-{
-   /*read power control register*/
-   asm(mrc p15, 0, %0, c15, c0, 0 : =r(g_pwr_ctrl) : : cc);
-   /*read diagnostic register*/
-   asm(mrc p15, 0, %0, c15, c0, 1 : =r(g_diag_reg) : : cc);
-   return;
-}
-
-static void restore_cpu_arch_register(void)
-{
-   /*write power control register*/
-   asm(mcr p15, 0, %0, c15, c0, 0 : : r(g_pwr_ctrl) : cc);
-   /*write diagnostic register*/
-   asm(mcr p15, 0, %0, c15, c0, 1 : : r(g_diag_reg) : cc);
-   return;
-}
-
 static int idle_finisher(unsigned long flags)
 {
exynos_set_wakeupmask();
@@ -87,8 +67,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device *dev,
 {
unsigned long tmp;
 
-   save_cpu_arch_register();
-
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp = ~S5P_CENTRAL_LOWPWR_CFG;
@@ -103,8 +81,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
 #endif
cpu_pm_exit();
 
-   restore_cpu_arch_register();
-
/*
 * If PMU failed while entering sleep mode, WFI will be
 * ignored by PMU and then exiting cpu_do_idle().
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index adfdf4b..67d75fe 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -16,6 +16,7 @@
 #include linux/init.h
 #include linux/suspend.h
 #include linux/syscore_ops.h
+#include linux/cpu_pm.h
 #include linux/io.h
 #include linux/irqchip/arm-gic.h
 #include linux/err.h
@@ -321,10 +322,38 @@ static const struct platform_suspend_ops 
exynos_suspend_ops = {
.valid  = suspend_valid_only_mem,
 };
 
+static int exynos_cpu_pm_notifier(struct notifier_block *self,
+ unsigned long cmd, void *v)
+{
+   int cpu = smp_processor_id();
+
+   switch (cmd) {
+   case CPU_PM_ENTER:
+   if (cpu == 0) {
+   exynos_cpu_save_register();
+   }
+   break;
+
+   case CPU_PM_EXIT:
+   if (cpu == 0) {
+   exynos_cpu_restore_register();
+   }
+   break;
+   }
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block exynos_cpu_pm_notifier_block = {
+   .notifier_call = exynos_cpu_pm_notifier,
+};
+
 void __init exynos_pm_init(void)
 {
u32 tmp;
 
+   cpu_pm_register_notifier(exynos_cpu_pm_notifier_block);
+
/* Platform-specific GIC callback */
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 
-- 
1.7.9.5

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[PATCH V5 10/20] ARM: exynos: cpuidle: Remove ifdef for scu_enable

[Daniel Lezcano]

The scu_enable function is already a noop in the scu's header file is
CONFIG_SMP=n, so no need to use these macros in the code.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/pm.c |4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index aba577f..9773a00 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -244,7 +244,7 @@ static void exynos_pm_resume(void)
 
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
-   if (IS_ENABLED(CONFIG_SMP)  !soc_is_exynos5250())
+   if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
 
 early_wakeup:
@@ -336,10 +336,8 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
 
case CPU_PM_EXIT:
if (cpu == 0) {
-#ifdef CONFIG_SMP
if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
-#endif
exynos_cpu_restore_register();
}
break;
-- 
1.7.9.5

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[PATCH V5 06/20] ARM: exynos: cpuidle: Move some code inside the idle_finisher

[Daniel Lezcano]

Move the code around to differentiate different section of code and prepare it
to be factored out in the next patches.

The call order changed but hat doesn't have a side effect because they are
independent. The important call is cpu_do_idle() which must be done the last.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/cpuidle.c |   17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index f565186..4d8bcfd 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -68,7 +68,16 @@ static void restore_cpu_arch_register(void)
 
 static int idle_finisher(unsigned long flags)
 {
+   exynos_set_wakeupmask();
+
+   __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+   __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+
+   /* Set value of power down register for aftr mode */
+   exynos_sys_powerdown_conf(SYS_AFTR);
+
cpu_do_idle();
+
return 1;
 }
 
@@ -78,14 +87,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
 {
unsigned long tmp;
 
-   exynos_set_wakeupmask();
-
-   /* Set value of power down register for aftr mode */
-   exynos_sys_powerdown_conf(SYS_AFTR);
-
-   __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
-   __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-
save_cpu_arch_register();
 
/* Setting Central Sequence Register for power down mode */
-- 
1.7.9.5

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[PATCH V5 19/20] ARM: exynos: cpuidle: Cleanup all unneeded headers from cpuidle.c

[Daniel Lezcano]

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |   10 --
 1 file changed, 10 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 1d1222e..1d09ebd 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -8,25 +8,15 @@
  * published by the Free Software Foundation.
 */
 
-#include linux/kernel.h
-#include linux/init.h
 #include linux/cpuidle.h
 #include linux/cpu_pm.h
-#include linux/io.h
 #include linux/export.h
-#include linux/time.h
 #include linux/platform_device.h
 
 #include asm/proc-fns.h
 #include asm/suspend.h
-#include asm/unified.h
 #include asm/cpuidle.h
 
-#include plat/cpu.h
-#include plat/pm.h
-
-#include mach/map.h
-
 static void (*exynos_enter_aftr)(void);
 
 static int idle_finisher(unsigned long flags)
-- 
1.7.9.5

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[PATCH V5 16/20] ARM: exynos: cpuidle: Move the power sequence call in the cpu_pm notifier

[Daniel Lezcano]

The code to initiate and exit the powerdown sequence is the same in pm.c and
cpuidle.c.

Let's split the common part in the pm.c and reuse it from the cpu_pm notifier.

That is one more step forward to make the cpuidle driver arch indenpendant.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
 arch/arm/mach-exynos/cpuidle.c |   22 --
 arch/arm/mach-exynos/pm.c  |   24 
 2 files changed, 20 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index e6d813d..02609ac 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -28,7 +28,6 @@
 #include mach/map.h
 
 #include common.h
-#include regs-pmu.h
 
 static int idle_finisher(unsigned long flags)
 {
@@ -42,31 +41,10 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
struct cpuidle_driver *drv,
int index)
 {
-   unsigned long tmp;
-
-   /* Setting Central Sequence Register for power down mode */
-   tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-   tmp = ~S5P_CENTRAL_LOWPWR_CFG;
-   __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
cpu_pm_exit();
 
-   /*
-* If PMU failed while entering sleep mode, WFI will be
-* ignored by PMU and then exiting cpu_do_idle().
-* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
-* in this situation.
-*/
-   tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-   if (!(tmp  S5P_CENTRAL_LOWPWR_CFG)) {
-   tmp |= S5P_CENTRAL_LOWPWR_CFG;
-   __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-   /* Clear wakeup state register */
-   __raw_writel(0x0, S5P_WAKEUP_STAT);
-   }
-
return index;
 }
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 50b6b4d..6d9ef69 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -213,15 +213,21 @@ static void exynos_pm_prepare(void)
__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 }
 
-static int exynos_pm_suspend(void)
+static void exynos_pm_central_suspend(void)
 {
unsigned long tmp;
 
/* Setting Central Sequence Register for power down mode */
-
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp = ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+}
+
+static int exynos_pm_suspend(void)
+{
+   unsigned long tmp;
+
+   exynos_pm_central_suspend();
 
/* Setting SEQ_OPTION register */
 
@@ -234,7 +240,7 @@ static int exynos_pm_suspend(void)
return 0;
 }
 
-static void exynos_pm_resume(void)
+static int exynos_pm_central_resume(void)
 {
unsigned long tmp;
 
@@ -251,9 +257,17 @@ static void exynos_pm_resume(void)
/* clear the wakeup state register */
__raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
-   goto early_wakeup;
+   return -1;
}
 
+   return 0;
+}
+
+static void exynos_pm_resume(void)
+{
+   if (exynos_pm_central_resume())
+   goto early_wakeup;
+
if (!soc_is_exynos5250())
exynos_cpu_restore_register();
 
@@ -359,6 +373,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
switch (cmd) {
case CPU_PM_ENTER:
if (cpu == 0) {
+   exynos_pm_central_suspend();
exynos_cpu_save_register();
}
break;
@@ -368,6 +383,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
exynos_cpu_restore_register();
+   exynos_pm_central_resume();
}
break;
}
-- 
1.7.9.5

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[PATCH V5 07/20] ARM: exynos: cpuidle: Fix S5P_WAKEUP_STAT call

[Daniel Lezcano]

This function should be called only when the powerdown sequence fails.

Even if the current code does not hurt, by moving this line, we have the same
code than the one in pm.c.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
Reviewed-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/cpuidle.c |5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4d8bcfd..346c2d0 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -115,11 +115,10 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
if (!(tmp  S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+   /* Clear wakeup state register */
+   __raw_writel(0x0, S5P_WAKEUP_STAT);
}
 
-   /* Clear wakeup state register */
-   __raw_writel(0x0, S5P_WAKEUP_STAT);
-
return index;
 }
 
-- 
1.7.9.5

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[PATCH V5 14/20] ARM: exynos: cpuidle: Encapsulate the AFTR code into a function

[Daniel Lezcano]

Let's encapsulate the AFTR state specific call into a single function.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 95313ea..fe35fba 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -51,13 +51,17 @@ static void exynos_cpu_set_boot_vector(long flags)
__raw_writel(flags, REG_DIRECTGO_FLAG);
 }
 
-static int idle_finisher(unsigned long flags)
+static void exynos_enter_aftr(void)
 {
exynos_set_wakeupmask(0xff3e);
exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
+}
 
+static int idle_finisher(unsigned long flags)
+{
+   exynos_enter_aftr();
cpu_do_idle();
 
return 1;
-- 
1.7.9.5

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[PATCH V5 11/20] ARM: exynos: cpuidle: Pass wakeup mask parameter to function

[Daniel Lezcano]

Pass the wakeup mask to 'exynos_set_wakeupmask' as this function could be used
for different idle states with different mask.

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 95826c6..169db74 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -40,14 +40,14 @@
 #define S5P_CHECK_AFTR 0xFCBA0D10
 
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(void)
+static void exynos_set_wakeupmask(long mask)
 {
-   __raw_writel(0xff3e, S5P_WAKEUP_MASK);
+   __raw_writel(mask, S5P_WAKEUP_MASK);
 }
 
 static int idle_finisher(unsigned long flags)
 {
-   exynos_set_wakeupmask();
+   exynos_set_wakeupmask(0xff3e);
 
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-- 
1.7.9.5

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