2015-12-23 19:54 GMT+09:00 Tomasz Figa <tomasz.f...@gmail.com>:
> Hi,
>
> 2015-12-23 19:51 GMT+09:00 Krzysztof Kozlowski <k.kozlow...@samsung.com>:
>> W dniu 22.12.2015 o 13:50, Olof Johansson pisze:
>>> On Wed, Dec 02, 2015 at 10:39:42AM +0900, Krzys
cific data (2015-11-16 10:54:43
>>> +0900)
>>
>> Hi,
>>
>> This should either go in through the pinctrl tree, or have an
>> acked/reviewed-by
>> one of the pinctrl maintainers.
>
> It was acked by Tomasz Figa - Samsung Pin Controller maintaine
2015-12-23 19:58 GMT+09:00 Krzysztof Kozlowski <k.kozlow...@samsung.com>:
> W dniu 23.12.2015 o 19:54, Tomasz Figa pisze:
>> Hi,
>>
>> 2015-12-23 19:51 GMT+09:00 Krzysztof Kozlowski <k.kozlow...@samsung.com>:
>>> W dniu 22.12.2015 o 13:50, Olof Johansson
ed by spin_lock recursion.
> The same spin_lock is used by gate/mux clocks during enable/disable calls.
>
> This deadlock, can be reproduced by enabling CPUfreq (ondemand or
> userspace) and decoding video with s5p-mfc driver.
Good catch.
Acked-by: Tomasz Figa <tomasz.f...@gm
gt;
> ---
> drivers/clk/samsung/clk-exynos5420.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Tomasz Figa <tomasz.f...@gmail.com>
Best regards,
Tomasz
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2015-11-19 13:51 GMT+09:00 Krzysztof Kozlowski <k.kozlow...@samsung.com>:
> On 19.11.2015 13:18, Tomasz Figa wrote:
>> However, I don't think we can disable compilation of particular 64-bit
>> SoCs, so maybe there isn't much sense in splitting their clock drivers
>
Hi Krzysztof,
Good idea, just a couple of nits inline. Other than that:
Acked-by: Tomasz Figa <tomasz.f...@gmail.com>
2015-11-16 10:36 GMT+09:00 Krzysztof Kozlowski <k.kozlow...@samsung.com>:
> Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
> s
k inline and assuming that, after this
patch, grep ARCH_EXYNOS7 gives no results:
Reviewed-by: Tomasz Figa <tomasz.f...@gmail.com>
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
> ---
> arch/arm64/Kconfig.platforms| 11 ++-
> arch/arm64/boot
+
---
drivers/clk/samsung/clk-s5pv210.c | 2 ++
1 file changed, 2 insertions(+)
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz
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: Lee Jones l...@kernel.org
Cc: Matthias Brugger matthias@gmail.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Kukjin Kim kg...@kernel.org
Cc: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: linux-g...@vger.kernel.org
Cc: linux-rpi-ker
, self-contained (one patch to fix issue) and maintains backward
compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
valuable comments.
2. Dropped patch 2/2 because now it is not needed. The clock id TSADC
will be used on all Exynos4 boards.
3. Added CC-stable
2015-06-16 0:00 GMT+09:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
Hello Sudeep,
On 06/15/2015 11:01 AM, Sudeep Holla wrote:
On 15/06/15 08:46, Javier Martinez Canillas wrote:
[...]
Sudeep, so we may need something like $subject after all from Doug's
explanations since
2015-06-11 21:40 GMT+09:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
W dniu 11.06.2015 o 21:15, Javier Martinez Canillas pisze:
Hello Krzysztof,
On Thu, Jun 11, 2015 at 12:43 PM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
W dniu 11.06.2015 o 17:26, Krzysztof Kozlowski pisze:
Add
:
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz
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Hi Linus,
2015-04-09 9:40 GMT+02:00 Linus Walleij linus.wall...@linaro.org:
The Samsung pin control driver and subdrivers sometimes use both
an irqdomain for some IRQs and another irqdomain for wakeup irqs,
registering the first with a call to the per-SoC callback
.eint_gpio_init() and the
2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
So I disabled the sss clock before trying a S2R:
# devmem 0x10018800 32 0xFFFB
(CLK_SSS in CLK_GATE_IP_G2D is gated)
and S2R worked anyways but I see that CLK_GATE_IP_G2D is reset to
its default value
2015-04-07 16:11 GMT+02:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas javier.marti...@collabora.co.uk
Date: Tue, 7 Apr 2015 15:53:27 +0200
Subject: [RFC PATCH] clk: exynos5420:
Hi Javier,
2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
The Samsung helpers functions to register clocks, add the clock instance
returned by the common clock framework to a lookup table that is used by
OF to lookup the clocks.
But this table could also
Hi Javier,
Please see my comments inline.
2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
[snip]
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 07d666cc6a29..2d39b629144a 100644
---
| 1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 103
+
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
4 files changed, 107 insertions(+)
Acked-by: Tomasz Figa tomasz.f
-pinctrl 1058.pinctrl: irq number not available
As long as external gpio interrupts refer to non-wake-up-capable
GPIO interrupts I'm fine with this patch.
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Thanks Linus for pinging and sorry for delay.
Best regards,
Tomasz
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Hi Arnd,
Thanks a lot for these patches.
2015-03-02 21:35 GMT+09:00 Arnd Bergmann a...@arndb.de:
Hi everyone,
I've had these patches in a private git tree for a while, and have
finally gotten around to clean them up some more for submission.
Hopefully we can get all of it merged into 4.1.
2015-02-25 19:13 GMT+09:00 Inha Song ideal.s...@samsung.com:
Hi, Tomasz,
Thanks for you comment :)
On Wed, 25 Feb 2015 09:54:02 +0900
Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Inha,
Thanks for the patch. Please see my comments inline.
2015-02-24 18:22 GMT+09:00 Inha Song ideal.s
Hi Inha,
Thanks for the patch. Please see my comments inline.
2015-02-24 18:22 GMT+09:00 Inha Song ideal.s...@samsung.com:
This patch add CLKOUT driver support for Exynos3250 SoC.
Could you please add a little more information? I know that it might
be pretty obvious to people familiar with
. There are 41
general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
Changes from v2
2015-01-23 1:47 GMT+09:00 Sylwester Nawrocki s.nawro...@samsung.com:
Hi Chanwoo,
On 21/01/15 07:26, Chanwoo Choi wrote:
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
Hi,
[CCing more people]
2015-01-16 23:39 GMT+09:00 Paul Osmialowski p.osmialo...@samsung.com:
This enhancement of i2c API is designed to address following problem
caused by circular lock dependency:
- #1 (prepare_lock){+.+.+.}:
[2.730502][c0061e50] __lock_acquire+0x3c0/0x8a4
[
2015-01-06 5:25 GMT+09:00 Arnd Bergmann a...@arndb.de:
On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote:
DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened Device Tree))
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec =
On 30.12.2014 03:23, Nishanth Menon wrote:
On 12/23/2014 04:48 AM, Marek Szyprowski wrote:
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL)
On 30.12.2014 23:51, Nishanth Menon wrote:
Looks like the following also need addressing:
data-save is called twice (once more after l2cof_init)
l2c310_init_fns also needs l2c310_configure
will be nice to use l2x0_data only after we kmemdup data in __l2c_init
I'll check this.
Thanks.
Thanks a lot for investigating this, even before I could look into
splitting this.
2014-12-30 3:23 GMT+09:00 Nishanth Menon n...@ti.com:
On 12/23/2014 04:48 AM, Marek Szyprowski wrote:
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem
Hi Andreas,
On 23.11.2014 07:26, Andreas Färber wrote:
From: Hakjoo Kim ruppi@hardkernel.com
Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5410.
Signed-off-by: Hakjoo Kim ruppi@hardkernel.com
[AF: Rebased onto Exynos5260 and
Hi Chanwoo,
On 27.11.2014 16:34, Chanwoo Choi wrote:
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc
On 10.12.2014 17:39, Vivek Gautam wrote:
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Tomasz Figa
/samsung/pinctrl-exynos.c | 10 ++
2 files changed, 11 insertions(+), 0 deletions(-)
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz
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Nishanth, Tony,
On 24.12.2014 02:13, Nishanth Menon wrote:
On 12/23/2014 11:06 AM, Tony Lindgren wrote:
* Marek Szyprowski m.szyprow...@samsung.com [141223 02:51]:
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based
2014-12-06 1:23 GMT+09:00 Russell King - ARM Linux li...@arm.linux.org.uk:
On Fri, Dec 05, 2014 at 10:13:51AM -0600, Nishanth Menon wrote:
On 12/05/2014 10:10 AM, Nishanth Menon wrote:
Case #2: Reverting the following allows boot.
From next-20141204
10df7d5 ARM: 8211/1: l2c: Add support
2014-12-01 17:37 GMT+09:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
On nie, 2014-11-30 at 21:19 +0900, Tomasz Figa wrote:
Hi Krzysztof,
2014-11-28 23:08 GMT+09:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
On pią, 2014-11-28 at 15:04 +0100, Linus Walleij wrote:
On Wed, Nov 26, 2014
Hi Vivek,
Please see my comments below.
2014-11-24 22:02 GMT+09:00 Vivek Gautam gautam.vi...@samsung.com:
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Hi Andreas,
2014-11-28 21:07 GMT+09:00 Andreas Färber afaer...@suse.de:
Am 28.11.2014 um 12:59 schrieb Linus Walleij:
On Sat, Nov 22, 2014 at 11:26 PM, Andreas Färber afaer...@suse.de wrote:
From: Hakjoo Kim ruppi@hardkernel.com
Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
Hi Krzysztof,
2014-11-28 23:08 GMT+09:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
On pią, 2014-11-28 at 15:04 +0100, Linus Walleij wrote:
On Wed, Nov 26, 2014 at 3:24 PM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
The audio subsystem on Exynos 5420 has separate clocks and GPIO.
2014-11-27 20:45 GMT+09:00 Arnd Bergmann a...@arndb.de:
On Thursday 27 November 2014 16:34:58 Chanwoo Choi wrote:
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl
Hi Krzysztof,
Please see my comments inline.
2014-11-25 0:18 GMT+09:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
+static int audss_clk_gate_enable(struct clk_hw *hw)
+{
+ int ret;
+
+ if (!IS_ERR(pll_in))
+ clk_prepare_enable(pll_in);
Calling
: Consolidate irq domain callbacks
pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Naveen Krishna Ch (1):
pinctrl: exynos: Add initial driver data for Exynos7
Tomasz Figa (6):
pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
pinctrl
Hi Chanwoo,
2014-11-07 15:23 GMT+09:00 Chanwoo Choi cw00.c...@samsung.com:
Dear Linus,
Could you please review this patch?
I'll take care of this during this weekend.
Sorry for all the delays, but I was in the middle of relocation to
another country and I just didn't have enough time yet to
Hi Chanwoo,
On 20.10.2014 05:32, Chanwoo Choi wrote:
This patch add Exynos4415's SoC ID. Exynos4415 is based on the 32-bit RISC
processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a
target
speed of 1.6GHz and provides 8.5GB/s memory bandwidth.
Cc: Kukjin Kim
Hi Chanwoo,
On 24.10.2014 13:39, Chanwoo Choi wrote:
This patch add sleep mode pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pin in sleep state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park Kyungmin p...@samsung.com
I
Hi Linus,
On 24.10.2014 14:01, Linus Walleij wrote:
On Mon, Oct 20, 2014 at 4:01 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Can you please pick this series up.
Yes, sorry for the delay. I've applied patches
1,2,3,4. The patches to the DTS files should be taken
through
On 24.10.2014 15:18, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked
On 24.10.2014 15:23, Daniel Drake wrote:
On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch adds new exynos4415.dtsi to support Exynos4415 SoC
based on Cortex-A9 quad cores and includes following dt nodes:
There's a lot in common between your new
On 21.10.2014 15:52, Alim Akhtar wrote:
+mmc_0 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
Please use mmc_hs200-1_8v instead.
I guess you mean mmc-hs200-1_8v (with a hyphen between mmc and hs200).
+ supports-highspeed;
As per
On 20.10.2014 13:41, Thomas Abraham wrote:
Changes since v10:
- Rebased on top of v3.18-rc1
This patch series removes the use of Exynos4210 and Exynos5250 specific
cpufreq
drivers and enables the use of cpufreq-dt driver for these platforms. This
series also enables cpufreq support for
On 20.10.2014 13:48, Thomas Abraham wrote:
Hi Tomasz,
On Mon, Oct 20, 2014 at 5:05 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 20.10.2014 13:41, Thomas Abraham wrote:
Changes since v10:
- Rebased on top of v3.18-rc1
This patch series removes the use of Exynos4210 and Exynos5250
Hi Anton,
On 13.10.2014 06:54, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk
On 08.10.2014 12:23, Linus Walleij wrote:
On Thu, Oct 2, 2014 at 8:52 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This series intends to clean up data structures used by pinctrl-samsung
driver.
More specifically, it separates initial compile time constants from data used
at runtime
Abhilash, Linus,
On 09.10.2014 15:54, Abhilash Kesavan wrote:
Changes since v4:
- Rebased over Tomasz Figa's pinctrl clean-up patches[1]
Changes since v3:
- Changed variable name from exynos_wkup_irq_chip to irq_chip
- Added acked-by tag from Tomasz Figa
Changes since
On 06.10.2014 17:39, Sylwester Nawrocki wrote:
diff --git a/drivers/media/platform/exynos4-is/Kconfig
b/drivers/media/platform/exynos4-is/Kconfig
index 77c9512..b3b270a 100644
--- a/drivers/media/platform/exynos4-is/Kconfig
+++ b/drivers/media/platform/exynos4-is/Kconfig
@@ -2,7 +2,7 @@
On 02.10.2014 12:25, Inki Dae wrote:
On 2014년 10월 02일 08:47, Joonyoung Shim wrote:
Hi Tomasz,
On 10/02/2014 12:13 AM, Tomasz Figa wrote:
Hi Inki,
On 17.09.2014 15:48, Inki Dae wrote:
This interface and relevant codes aren't used anymore.
Hmm, I might be missing something, but after
There is no code using it and in fact there are pin controller variants
that do not even have this field initialized in their init data. This
patch removes it completely.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Marek Szyprowski m.szyprow...@samsung.com
Tested by: Javier
:
- rebased on current devel branch of pinctrl tree.
Tomasz Figa (5):
pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
pinctrl: samsung: Constify samsung_pin_bank_type struct
pinctrl: samsung: Constify
be copied to main samsung_pin_bank struct used
at runtime.
In addition, thanks to this change, all per-bank initdata can be marked
with const and __initconst keywords and dropped after init completes.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Marek Szyprowski m.szyprow...@samsung.com
struct as const and __initconst.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Marek Szyprowski m.szyprow...@samsung.com
Tested by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 39 +++---
drivers/pinctrl/samsung/pinctrl
Currently the function returns a valid pointer on success and NULL on
error, so exact error code is lost. This patch changes return convention
of the function to use ERR_PTR() on error instead.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Marek Szyprowski m.szyprow...@samsung.com
This structure is not intended to be modified at runtime and functions
as constant data shared between multiple pin banks. This patch makes all
instances of it constant across the driver.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Marek Szyprowski m.szyprow...@samsung.com
Tested
On 02.10.2014 21:27, Daniel Drake wrote:
Hi,
Thanks for looking into this.
On Wed, Oct 1, 2014 at 4:55 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
I think that comment is incorrect. If tcmp is written as -1UL then the
LED totally turns off. And there is nothing in the Exynos4412 manual
Hi Pankaj,
Please see my comments inline.
On 01.10.2014 07:48, Pankaj Dubey wrote:
Let's register reboot_notifier for Exynos5440 from it's clock driver
for reboot functionality. So that we can cleanup restart hooks from
machine specific file.
CC: Sylwester Nawrocki s.nawro...@samsung.com
Hi Pankaj,
Please see my comments inline.
On 01.10.2014 07:49, Pankaj Dubey wrote:
Let's register reboot_notifier from PMU driver for reboot
functionality. So that we can remove restart hooks from
machine specific file, and thus moving ahead when PMU moved
to driver folder, this
On 30.09.2014 20:33, Kevin Hilman wrote:
Ulf Hansson ulf.hans...@linaro.org writes:
At -probe() it's common practice for drivers/subsystems to bring their
devices to full power and without depending on CONFIG_PM_RUNTIME.
We could also expect that drivers/subsystems requires their device's
Hi Inki,
On 17.09.2014 15:48, Inki Dae wrote:
This patch removes DRM_EXYNOS_GEM_MMAP ictrl feature specific
to Exynos drm and instead uses drm generic mmap.
It looks like libdrm_exynos is still using DRM_EXYNOS_GEM_MMAP, but this
patch just removes it. This basically means that any application
Hi Inki,
On 17.09.2014 15:48, Inki Dae wrote:
This interface and relevant codes aren't used anymore.
Hmm, I might be missing something, but after removing this IOCTL, how do
we obtain an offset to pass to mmap()?
Best regards,
Tomasz
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On 30.09.2014 17:12, Abhilash Kesavan wrote:
Hi Tomasz,
On Mon, Sep 22, 2014 at 2:22 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Abhilash,
On 22.09.2014 06:47, Abhilash Kesavan wrote:
Changes since v4:
- Fixed comments from Tomasz Figa:
- Changed the namespace prefix from
On 30.09.2014 17:13, Arnd Bergmann wrote:
On Tuesday 30 September 2014 20:04:55 Abhilash Kesavan wrote:
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -55,10 +55,10 @@ static struct irq_grp_save {
u32 mask;
} eint_grp_save[5];
-#ifndef
On 30.09.2014 20:36, Arnd Bergmann wrote:
On Tuesday 30 September 2014 18:10:14 Tomasz Figa wrote:
@@ -110,7 +110,7 @@ void __init s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg
of these symbols also helps in Exynos7
serial enablement.
AFAICT this patch should be second in the series, because it removes
symbols which are used by code that is yet to be updated in current patch 2.
Otherwise:
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz
The following changes since commit a52ae5a755d980e9ff812c6f45a415ba27bfd33b:
Merge branch 'clk-fixes' into clk-next (2014-09-17 11:47:56 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
tags/for_3.18/samsung-clk
for you to
Hi Abhilash,
The patch itself seems fine, but I wonder if those config options aren't
really just leftovers from the past and couldn't be completely removed.
On 29.09.2014 07:16, Abhilash Kesavan wrote:
From: Pankaj Dubey pankaj.du...@samsung.com
Exynos7 has a similar serial controller to
Hi Abhilash,
Just two minor issues inline. I leave them up to Linus to decide.
Linus, if you don't mind them, feel free to apply this patch with my Ack.
On 29.09.2014 07:15, Abhilash Kesavan wrote:
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip
/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |3 +
8 files changed, 799 insertions(+), 36 deletions(-)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
For patches 1-2, 4-6:
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Linus, I
Hi Linus,
On 25.09.2014 09:49, Tomasz Figa wrote:
On 25.09.2014 09:47, Linus Walleij wrote:
On Tue, Sep 23, 2014 at 9:05 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This series intends to clean up data structures used by pinctrl-samsung
driver.
More specifically, it separates initial
Hi Pankaj,
On 27.09.2014 07:41, Pankaj Dubey wrote:
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Even though the patch is obvious, it should have at least one line of
description.
Best regards,
Tomasz
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Hi Pankaj,
On 27.09.2014 07:41, Pankaj Dubey wrote:
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Missing patch description.
---
drivers/clk/samsung/clk.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index
On 26.09.2014 13:01, Sylwester Nawrocki wrote:
Hi Tomasz,
On 25/09/14 23:58, Tomasz Figa wrote:
On 10.09.2014 18:37, Sylwester Nawrocki wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from
On 25.09.2014 09:47, Linus Walleij wrote:
On Tue, Sep 23, 2014 at 9:05 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
This series intends to clean up data structures used by pinctrl-samsung
driver.
More specifically, it separates initial compile time constants from data used
at runtime
Hi Kukjin,
On 25.09.2014 10:26, Kukjin Kim wrote:
On 09/25/14 17:17, Lorenzo Pieralisi wrote:
[CC'ed Daniel to make him aware this patch goes through your tree]
Thanks and just note the branch which is including this change actually
v4 is just rebased not v3 will be sent out to arm-soc last
On 25.09.2014 10:44, Kukjin Kim wrote:
On 09/25/14 17:28, Tomasz Figa wrote:
Hi Kukjin,
On 25.09.2014 10:26, Kukjin Kim wrote:
On 09/25/14 17:17, Lorenzo Pieralisi wrote:
[CC'ed Daniel to make him aware this patch goes through your tree]
Thanks and just note the branch which
Hi Sylwester,
On 10.09.2014 18:37, Sylwester Nawrocki wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended clock source and with maximum supported
frequency. If needed these settings
On 24.09.2014 09:34, Kukjin Kim wrote:
Thomas Abraham wrote:
This patch series removes the use of Exynos4210 and Exynos5250 specific
cpufreq
drivers and enables the use of cpufreq-cpu0 driver for these platforms. This
series also enables cpufreq support for Exynos5420 using arm_big_little
On 24.09.2014 13:14, Mark Rutland wrote:
On Wed, Sep 24, 2014 at 12:05:38PM +0100, Marek Szyprowski wrote:
From: Tomasz Figa t.f...@samsung.com
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
On 23.09.2014 14:53, Alim Akhtar wrote:
Hi Marek,
On Mon, Sep 22, 2014 at 6:44 PM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
Hello,
This patchset adds support for early console defined in device tree. As
an example, DTS files for all Exynos4 based machines are updated with
the
On 23.09.2014 10:16, Abhilash Kesavan wrote:
[snip]
@@ -383,9 +377,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data
*irqd, unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip
There is no code using it and in fact there are pin controller variants
that do not even have this field initialized in their init data. This
patch removes it completely.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 22
This structure is not intended to be modified at runtime and functions
as constant data shared between multiple pin banks. This patch makes all
instances of it constant across the driver.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 8
00a26000 2**6
25 .data 000db860 c0c22000 c0c22000 00a2a000 2**6
This series should not introduce any functional changes.
Tested on S3C6410-based Mini6410 board, booting with device tree.
Marek, Bart, could you do some testing on Exynos-based boards,
just to make sure?
Tomasz Figa
Currently the function returns a valid pointer on success and NULL on
error, so exact error code is lost. This patch changes return convention
of the function to use ERR_PTR() on error instead.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/pinctrl/samsung/pinctrl-samsung.c | 6
struct as const and __initconst.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 39 +++---
drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 12 ++---
drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 14 ++---
drivers/pinctrl/samsung/pinctrl-samsung.c
be copied to main samsung_pin_bank struct used
at runtime.
In addition, thanks to this change, all per-bank initdata can be marked
with const and __initconst keywords and dropped after init completes.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 44
On 22.09.2014 08:17, Abhilash Kesavan wrote:
Hi Tomasz,
On Sat, Sep 13, 2014 at 4:57 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Abhilash,
Please see my comments inline.
On 13.09.2014 10:50, Abhilash Kesavan wrote:
Exynos7 uses different offsets for wakeup interrupt configuration
On 02.09.2014 15:21, Krzysztof Kozlowski wrote:
Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.
The DMC clock domain uses different address space (0x105C) than
standard clock domain (0x1003 - 0x1005).
On 09.09.2014 14:14, Krzysztof Kozlowski wrote:
On 05.09.2014 13:54, Pankaj Dubey wrote:
As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
drivers/clk/samsung/clk-exynos3250.c |4 ++--
1 file changed, 2
On 09.09.2014 14:14, Krzysztof Kozlowski wrote:
On 09.09.2014 13:54, Pankaj Dubey wrote:
Update shift and width field of div_spi0_isp clock as per Exynos3250
user manual.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
drivers/clk/samsung/clk-exynos3250.c |2 +-
1 file
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