[PATCH 1/2] ARM: dts: add fimd device node to exynos4415.dtsi
This patch adds fimd device node to exynos4415.dtsi.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4415.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4415.dtsi
b/arch/arm/boot/dts/exynos4415.dtsi
index c1c9b37..30acb3a 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -234,6 +234,18 @@
interrupts = 0 240 0;
};
+ fimd: fimd@11C0 {
+ compatible = samsung,exynos4415-fimd;
+ reg = 0x11C0 0x3;
+ interrupt-names = fifo, vsync, lcd_sys;
+ interrupts = 0 84 0, 0 85 0, 0 86 0;
+ clocks = cmu CLK_SCLK_FIMD0, cmu CLK_FIMD0;
+ clock-names = sclk_fimd, fimd;
+ samsung,power-domain = pd_lcd0;
+ samsung,sysreg = sysreg_system_controller;
+ status = disabled;
+ };
+
hsotg: hsotg@1248 {
compatible = samsung,s3c6400-hsotg;
reg = 0x1248 0x2;
--
1.9.0
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[PATCH 2/2] ARM: dts: add mipi dsi device node to exynos4415.dtsi
This patch adds mipi dsi device node to exynos4415.dtsi.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4415.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4415.dtsi
b/arch/arm/boot/dts/exynos4415.dtsi
index 30acb3a..6105236 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -246,6 +246,21 @@
status = disabled;
};
+ dsi_0: dsi@11C8 {
+ compatible = samsung,exynos4415-mipi-dsi;
+ reg = 0x11C8 0x1;
+ interrupts = 0 83 0;
+ samsung,phy-type = 0;
+ samsung,power-domain = pd_lcd0;
+ phys = mipi_phy 1;
+ phy-names = dsim;
+ clocks = cmu CLK_DSIM0, cmu CLK_SCLK_MIPI0;
+ clock-names = bus_clk, pll_clk;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
hsotg: hsotg@1248 {
compatible = samsung,s3c6400-hsotg;
reg = 0x1248 0x2;
--
1.9.0
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[RESEND PATCH 0/2] ARM: dts: add display device nodes for Exynos4415
This patch series adds display device nodes for Exynos4415 SoC support. The drm/exynos part of original patchset[1] was merged but DTS part is not yet. This is based on for-next branch in linux-samsung git. [1] http://www.spinics.net/lists/linux-samsung-soc/msg38649.html YoungJun Cho (2): ARM: dts: add fimd device node to exynos4415.dtsi ARM: dts: add mipi dsi device node to exynos4415.dtsi arch/arm/boot/dts/exynos4415.dtsi | 27 +++ 1 file changed, 27 insertions(+) -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/9] drm/exynos: fimd: add fimd_enable_shadow_channel_path() to cleanup
This function is valid only the SoC has SHADOWCON register
and it should be used together with fimd_enable_video_output()
to match the ENWIN_F bit in WINCON# and C#_EN_F bit in SHADOWCON.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 40 ++--
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 5cfd251..fd7b469 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -242,6 +242,19 @@ static void fimd_enable_video_output(struct fimd_context
*ctx, int win,
writel(val, ctx-regs + WINCON(win));
}
+static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
+ bool enable)
+{
+ u32 val = readl(ctx-regs + SHADOWCON);
+
+ if (enable)
+ val |= SHADOWCON_CHx_ENABLE(win);
+ else
+ val = ~SHADOWCON_CHx_ENABLE(win);
+
+ writel(val, ctx-regs + SHADOWCON);
+}
+
static void fimd_clear_channel(struct exynos_drm_manager *mgr)
{
struct fimd_context *ctx = mgr-ctx;
@@ -256,12 +269,10 @@ static void fimd_clear_channel(struct exynos_drm_manager
*mgr)
if (val WINCONx_ENWIN) {
fimd_enable_video_output(ctx, win, false);
- /* unprotect windows */
- if (ctx-driver_data-has_shadowcon) {
- val = readl(ctx-regs + SHADOWCON);
- val = ~SHADOWCON_CHx_ENABLE(win);
- writel(val, ctx-regs + SHADOWCON);
- }
+ if (ctx-driver_data-has_shadowcon)
+ fimd_enable_shadow_channel_path(ctx, win,
+ false);
+
ch_enabled = 1;
}
}
@@ -759,11 +770,8 @@ static void fimd_win_commit(struct exynos_drm_manager
*mgr, int zpos)
fimd_enable_video_output(ctx, win, true);
- if (ctx-driver_data-has_shadowcon) {
- val = readl(ctx-regs + SHADOWCON);
- val |= SHADOWCON_CHx_ENABLE(win);
- writel(val, ctx-regs + SHADOWCON);
- }
+ if (ctx-driver_data-has_shadowcon)
+ fimd_enable_shadow_channel_path(ctx, win, true);
/* Enable DMA channel and unprotect windows */
fimd_shadow_protect_win(ctx, win, false);
@@ -779,7 +787,6 @@ static void fimd_win_disable(struct exynos_drm_manager
*mgr, int zpos)
struct fimd_context *ctx = mgr-ctx;
struct fimd_win_data *win_data;
int win = zpos;
- u32 val;
if (win == DEFAULT_ZPOS)
win = ctx-default_win;
@@ -800,13 +807,10 @@ static void fimd_win_disable(struct exynos_drm_manager
*mgr, int zpos)
fimd_enable_video_output(ctx, win, false);
- /* unprotect windows */
- if (ctx-driver_data-has_shadowcon) {
- val = readl(ctx-regs + SHADOWCON);
- val = ~SHADOWCON_CHx_ENABLE(win);
- writel(val, ctx-regs + SHADOWCON);
- }
+ if (ctx-driver_data-has_shadowcon)
+ fimd_enable_shadow_channel_path(ctx, win, false);
+ /* unprotect windows */
fimd_shadow_protect_win(ctx, win, false);
win_data-enabled = false;
--
1.9.0
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[PATCH v2 0/9] drm/exynos: modify LCD I80 interface display
Hi, This series modifies LCD I80 interface display for Exynos DRM driver to make it similar with Video(RGB) interface. Some patches in v1 are applied already and these are modified as Inki's comments. And Joonyoung's patches are also included for merge convenience. This is based on exynos-drm-next branch. The previous patches, v1: http://www.spinics.net/lists/dri-devel/msg69159.html Changelog v2: - Splits patches into single feature. (commented by Inki) I welcome any comments. Thank you. Best regards YJ Joonyoung Shim (2): drm/exynos: move triggering checking drm/exynos: use irq_flags instead of triggering YoungJun Cho (7): drm/exynos: fimd: move shadow unprotection position drm/exynos: fimd: add fimd_enable_video_output() to cleanup drm/exynos: fimd: add fimd_enable_shadow_channel_path() to cleanup drm/exynos: fimd: modify I80 i/f irq relevant routine drm/exynos: fimd: add triggering unset routine in fimd_trigger() drm/exynos: dsi: move TE irq handler registration position drm/exynos: dsi: set TE GPIO IRQ status as IRQ_NOAUTOEN drivers/gpu/drm/exynos/exynos_drm_dsi.c | 19 ++--- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 135 ++- 2 files changed, 85 insertions(+), 69 deletions(-) -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/9] drm/exynos: fimd: add fimd_enable_video_output() to cleanup
This bit is used for video output and logic signal control.
So it is better for readability.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 77ba961..5cfd251 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -229,6 +229,19 @@ static void fimd_wait_for_vblank(struct exynos_drm_manager
*mgr)
DRM_DEBUG_KMS(vblank wait timed out.\n);
}
+static void fimd_enable_video_output(struct fimd_context *ctx, int win,
+ bool enable)
+{
+ u32 val = readl(ctx-regs + WINCON(win));
+
+ if (enable)
+ val |= WINCONx_ENWIN;
+ else
+ val = ~WINCONx_ENWIN;
+
+ writel(val, ctx-regs + WINCON(win));
+}
+
static void fimd_clear_channel(struct exynos_drm_manager *mgr)
{
struct fimd_context *ctx = mgr-ctx;
@@ -241,9 +254,7 @@ static void fimd_clear_channel(struct exynos_drm_manager
*mgr)
u32 val = readl(ctx-regs + WINCON(win));
if (val WINCONx_ENWIN) {
- /* wincon */
- val = ~WINCONx_ENWIN;
- writel(val, ctx-regs + WINCON(win));
+ fimd_enable_video_output(ctx, win, false);
/* unprotect windows */
if (ctx-driver_data-has_shadowcon) {
@@ -746,10 +757,7 @@ static void fimd_win_commit(struct exynos_drm_manager
*mgr, int zpos)
if (win != 0)
fimd_win_set_colkey(ctx, win);
- /* wincon */
- val = readl(ctx-regs + WINCON(win));
- val |= WINCONx_ENWIN;
- writel(val, ctx-regs + WINCON(win));
+ fimd_enable_video_output(ctx, win, true);
if (ctx-driver_data-has_shadowcon) {
val = readl(ctx-regs + SHADOWCON);
@@ -790,10 +798,7 @@ static void fimd_win_disable(struct exynos_drm_manager
*mgr, int zpos)
/* protect windows */
fimd_shadow_protect_win(ctx, win, true);
- /* wincon */
- val = readl(ctx-regs + WINCON(win));
- val = ~WINCONx_ENWIN;
- writel(val, ctx-regs + WINCON(win));
+ fimd_enable_video_output(ctx, win, false);
/* unprotect windows */
if (ctx-driver_data-has_shadowcon) {
--
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[PATCH 2/9] drm/exynos: fimd: move shadow unprotection position
The C#_EN_F in SHADOWCON register is updated per frame.
So it should be protected by fimd_shadow_protect_win().
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index ec2d170..77ba961 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -751,15 +751,15 @@ static void fimd_win_commit(struct exynos_drm_manager
*mgr, int zpos)
val |= WINCONx_ENWIN;
writel(val, ctx-regs + WINCON(win));
- /* Enable DMA channel and unprotect windows */
- fimd_shadow_protect_win(ctx, win, false);
-
if (ctx-driver_data-has_shadowcon) {
val = readl(ctx-regs + SHADOWCON);
val |= SHADOWCON_CHx_ENABLE(win);
writel(val, ctx-regs + SHADOWCON);
}
+ /* Enable DMA channel and unprotect windows */
+ fimd_shadow_protect_win(ctx, win, false);
+
win_data-enabled = true;
if (ctx-i80_if)
--
1.9.0
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[PATCH 1/9] drm/exynos: move triggering checking
From: Joonyoung Shim jy0922.s...@samsung.com It's better to be checking whether triggerring in fimd_trigger function. Also it will return if in triggerring on fimd_te_handler, then it can't execute remain codes. Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 0673a39..ec2d170 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -949,6 +949,13 @@ static void fimd_trigger(struct device *dev) void *timing_base = ctx-regs + driver_data-timing_base; u32 reg; +/* +* Skips to trigger if in triggering state, because multiple triggering +* requests can cause panel reset. +*/ + if (atomic_read(ctx-triggering)) + return; + atomic_set(ctx-triggering, 1); reg = readl(ctx-regs + VIDINTCON0); @@ -969,13 +976,6 @@ static void fimd_te_handler(struct exynos_drm_manager *mgr) if (ctx-pipe 0 || !ctx-drm_dev) return; -/* -* Skips to trigger if in triggering state, because multiple triggering -* requests can cause panel reset. -*/ - if (atomic_read(ctx-triggering)) - return; - /* * If there is a page flip request, triggers and handles the page flip * event so that current fb can be updated into panel GRAM. -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/9] drm/exynos: fimd: modify I80 i/f irq relevant routine
For the I80 interface, the video interrupt pending register(VIDINTCON1)
should be handled in fimd_irq_handler() and the video interrupt control
register(VIDINTCON0) should be handled in fimd_enable_vblank() and
fimd_disable_vblank() like RGB interface.
So this patch moves each set / unset routines into proper positions.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 53
1 file changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index fd7b469..3c63237 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -469,12 +469,19 @@ static int fimd_enable_vblank(struct exynos_drm_manager
*mgr)
val = readl(ctx-regs + VIDINTCON0);
val |= VIDINTCON0_INT_ENABLE;
- val |= VIDINTCON0_INT_FRAME;
- val = ~VIDINTCON0_FRAMESEL0_MASK;
- val |= VIDINTCON0_FRAMESEL0_VSYNC;
- val = ~VIDINTCON0_FRAMESEL1_MASK;
- val |= VIDINTCON0_FRAMESEL1_NONE;
+ if (ctx-i80_if) {
+ val |= VIDINTCON0_INT_I80IFDONE;
+ val |= VIDINTCON0_INT_SYSMAINCON;
+ val = ~VIDINTCON0_INT_SYSSUBCON;
+ } else {
+ val |= VIDINTCON0_INT_FRAME;
+
+ val = ~VIDINTCON0_FRAMESEL0_MASK;
+ val |= VIDINTCON0_FRAMESEL0_VSYNC;
+ val = ~VIDINTCON0_FRAMESEL1_MASK;
+ val |= VIDINTCON0_FRAMESEL1_NONE;
+ }
writel(val, ctx-regs + VIDINTCON0);
}
@@ -493,9 +500,15 @@ static void fimd_disable_vblank(struct exynos_drm_manager
*mgr)
if (test_and_clear_bit(0, ctx-irq_flags)) {
val = readl(ctx-regs + VIDINTCON0);
- val = ~VIDINTCON0_INT_FRAME;
val = ~VIDINTCON0_INT_ENABLE;
+ if (ctx-i80_if) {
+ val = ~VIDINTCON0_INT_I80IFDONE;
+ val = ~VIDINTCON0_INT_SYSMAINCON;
+ val = ~VIDINTCON0_INT_SYSSUBCON;
+ } else
+ val = ~VIDINTCON0_INT_FRAME;
+
writel(val, ctx-regs + VIDINTCON0);
}
}
@@ -959,19 +972,15 @@ static void fimd_trigger(struct device *dev)
u32 reg;
/*
-* Skips to trigger if in triggering state, because multiple triggering
-* requests can cause panel reset.
-*/
+ * Skips triggering if in triggering state, because multiple triggering
+ * requests can cause panel reset.
+ */
if (atomic_read(ctx-triggering))
return;
+ /* Enters triggering mode */
atomic_set(ctx-triggering, 1);
- reg = readl(ctx-regs + VIDINTCON0);
- reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
- VIDINTCON0_INT_SYSMAINCON);
- writel(reg, ctx-regs + VIDINTCON0);
-
reg = readl(timing_base + TRIGCON);
reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
writel(reg, timing_base + TRIGCON);
@@ -1036,21 +1045,13 @@ static irqreturn_t fimd_irq_handler(int irq, void
*dev_id)
if (ctx-pipe 0 || !ctx-drm_dev)
goto out;
- if (ctx-i80_if) {
- /* unset I80 frame done interrupt */
- val = readl(ctx-regs + VIDINTCON0);
- val = ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON);
- writel(val, ctx-regs + VIDINTCON0);
+ drm_handle_vblank(ctx-drm_dev, ctx-pipe);
+ exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
- /* exit triggering mode */
+ if (ctx-i80_if) {
+ /* Exits triggering mode */
atomic_set(ctx-triggering, 0);
-
- drm_handle_vblank(ctx-drm_dev, ctx-pipe);
- exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
} else {
- drm_handle_vblank(ctx-drm_dev, ctx-pipe);
- exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
-
/* set wait vsync event to zero and wake up queue. */
if (atomic_read(ctx-wait_vsync_event)) {
atomic_set(ctx-wait_vsync_event, 0);
--
1.9.0
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[PATCH 6/9] drm/exynos: fimd: add triggering unset routine in fimd_trigger()
There is a case like set config which requires triggering but vblank is not enabled yet. So triggering unset routine is required to exit from triggering mode. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 3c63237..e488b80 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -984,6 +984,13 @@ static void fimd_trigger(struct device *dev) reg = readl(timing_base + TRIGCON); reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); writel(reg, timing_base + TRIGCON); + + /* +* Exits triggering mode if vblank is not enabled yet, because when the +* VIDINTCON0 register is not set, it can not exit from triggering mode. +*/ + if (!test_bit(0, ctx-irq_flags)) + atomic_set(ctx-triggering, 0); } static void fimd_te_handler(struct exynos_drm_manager *mgr) -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 8/9] drm/exynos: dsi: move TE irq handler registration position
The drm_helper_hpd_irq_event() does dpms control and the panel is initialized and displayed on by it. So the exynos_dsi_te_irq_handler() should be registered beforehand. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 66d427e..6fe6486 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -1207,9 +1207,6 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host, dsi-mode_flags = device-mode_flags; dsi-panel_node = device-dev.of_node; - if (dsi-connector.dev) - drm_helper_hpd_irq_event(dsi-connector.dev); - /* * This is a temporary solution and should be made by more generic way. * @@ -1223,6 +1220,9 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host, return ret; } + if (dsi-connector.dev) + drm_helper_hpd_irq_event(dsi-connector.dev); + return 0; } -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/9] drm/exynos: use irq_flags instead of triggering
From: Joonyoung Shim jy0922.s...@samsung.com
The drm_handle_vblank should be called whenever be vsync, te interrupt
means vsync on i80 interface.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index e488b80..a8ab3ec 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -1014,7 +1014,7 @@ static void fimd_te_handler(struct exynos_drm_manager
*mgr)
wake_up(ctx-wait_vsync_queue);
}
- if (!atomic_read(ctx-triggering))
+ if (test_bit(0, ctx-irq_flags))
drm_handle_vblank(ctx-drm_dev, ctx-pipe);
}
@@ -1052,13 +1052,15 @@ static irqreturn_t fimd_irq_handler(int irq, void
*dev_id)
if (ctx-pipe 0 || !ctx-drm_dev)
goto out;
- drm_handle_vblank(ctx-drm_dev, ctx-pipe);
- exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
-
if (ctx-i80_if) {
+ exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
+
/* Exits triggering mode */
atomic_set(ctx-triggering, 0);
} else {
+ drm_handle_vblank(ctx-drm_dev, ctx-pipe);
+ exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
+
/* set wait vsync event to zero and wake up queue. */
if (atomic_read(ctx-wait_vsync_event)) {
atomic_set(ctx-wait_vsync_event, 0);
--
1.9.0
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[PATCH 9/9] drm/exynos: dsi: set TE GPIO IRQ status as IRQ_NOAUTOEN
The exynos_dsi_te_irq_handler() works only dsi(DPMS) is on.
So it is enough to enable and disable TE GPIO IRQ in
exynos_dsi_enable(disable)_irq() like DSI IRQ.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.coma
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 6fe6486..717c719 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1155,6 +1155,7 @@ static int exynos_dsi_init(struct exynos_dsi *dsi)
static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
{
int ret;
+ int te_gpio_irq;
dsi-te_gpio = of_get_named_gpio(dsi-panel_node, te-gpios, 0);
if (!gpio_is_valid(dsi-te_gpio)) {
@@ -1169,14 +1170,10 @@ static int exynos_dsi_register_te_irq(struct exynos_dsi
*dsi)
goto out;
}
- /*
-* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
-* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
-* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
-* called by drm_panel_init() before panel is attached.
-*/
- ret = request_threaded_irq(gpio_to_irq(dsi-te_gpio),
- exynos_dsi_te_irq_handler, NULL,
+ te_gpio_irq = gpio_to_irq(dsi-te_gpio);
+
+ irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
+ ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
IRQF_TRIGGER_RISING, TE, dsi);
if (ret) {
dev_err(dsi-dev, request interrupt failed with %d\n, ret);
--
1.9.0
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Re: [PATCH 2/2] drm/exynos: use irq_flags instead of triggering
Hi JoonYoung, On 11/14/2014 11:36 AM, Joonyoung Shim wrote: The drm_handle_vblank should be called whenever be vsync, te interrupt means vsync on i80 interface. That's right. Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com --- Based on lastest exynos-drm-next branch and patch of Youngjun Cho (drm/exynos: fimd: move handle vblank position in TE handler). drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 033b18b..5cc57f7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -984,7 +984,7 @@ static void fimd_te_handler(struct exynos_drm_manager *mgr) wake_up(ctx-wait_vsync_queue); } - if (!atomic_read(ctx-triggering)) + if (test_bit(0, ctx-irq_flags)) drm_handle_vblank(ctx-drm_dev, ctx-pipe); But after triggering, fimd_irq_handler() is called by lcd_sys interrupt and that calls drm_handle_vblank(). So I think fimd_te_handler() calls drm_handle_vblank() only non-triggering condition. Thank you. Best regards YJ } -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] drm/exynos: use irq_flags instead of triggering
Hi JoonYoung, On 11/14/2014 02:12 PM, Joonyoung Shim wrote: Hi, On 11/14/2014 02:01 PM, YoungJun Cho wrote: Hi JoonYoung, On 11/14/2014 11:36 AM, Joonyoung Shim wrote: The drm_handle_vblank should be called whenever be vsync, te interrupt means vsync on i80 interface. That's right. Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com --- Based on lastest exynos-drm-next branch and patch of Youngjun Cho (drm/exynos: fimd: move handle vblank position in TE handler). drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 033b18b..5cc57f7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -984,7 +984,7 @@ static void fimd_te_handler(struct exynos_drm_manager *mgr) wake_up(ctx-wait_vsync_queue); } -if (!atomic_read(ctx-triggering)) +if (test_bit(0, ctx-irq_flags)) drm_handle_vblank(ctx-drm_dev, ctx-pipe); But after triggering, fimd_irq_handler() is called by lcd_sys interrupt and that calls drm_handle_vblank(). I missed the routine but i think drm_handle_vblank should be called by vsync interrupt handler. As you know, fimd_irq_handler is not vsync interrupt handler on i80 interface. That sounds reasonable. For that, we should modify fimd_irq_handler() not to call drm_handle_vblank() in I80 interface. Thank you. Best regards YJ So I think fimd_te_handler() calls drm_handle_vblank() only non-triggering condition. Thank you. Best regards YJ } -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] drm/exynos: fimd: support Exynos4415 SoC
This patch supports Exynos4415 SoC.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
Documentation/devicetree/bindings/video/samsung-fimd.txt | 1 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt
b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 4e6c77c..cf1af63 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -11,6 +11,7 @@ Required properties:
samsung,s5pv210-fimd; /* for S5PV210 SoC */
samsung,exynos3250-fimd; /* for Exynos3250/3472 SoCs */
samsung,exynos4210-fimd; /* for Exynos4 SoCs */
+ samsung,exynos4415-fimd; /* for Exynos4415 SoC */
samsung,exynos5250-fimd; /* for Exynos5 SoCs */
- reg: physical base address and length of the FIMD registers set.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 085b066..5dfbbdb 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -120,6 +120,15 @@ static struct fimd_driver_data exynos4_fimd_driver_data = {
.has_shadowcon = 1,
};
+static struct fimd_driver_data exynos4415_fimd_driver_data = {
+ .timing_base = 0x2,
+ .lcdblk_offset = 0x210,
+ .lcdblk_vt_shift = 10,
+ .lcdblk_bypass_shift = 1,
+ .has_shadowcon = 1,
+ .has_vidoutcon = 1,
+};
+
static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
.lcdblk_offset = 0x214,
@@ -180,6 +189,8 @@ static const struct of_device_id fimd_driver_dt_match[] = {
.data = exynos3_fimd_driver_data },
{ .compatible = samsung,exynos4210-fimd,
.data = exynos4_fimd_driver_data },
+ { .compatible = samsung,exynos4415-fimd,
+ .data = exynos4415_fimd_driver_data },
{ .compatible = samsung,exynos5250-fimd,
.data = exynos5_fimd_driver_data },
{},
--
1.9.0
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[PATCH 4/4] ARM: dts: add mipi dsi device node to exynos4415.dtsi
This patch adds mipi dsi device node to exynos4415.dtsi.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4415.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4415.dtsi
b/arch/arm/boot/dts/exynos4415.dtsi
index 30acb3a..6105236 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -246,6 +246,21 @@
status = disabled;
};
+ dsi_0: dsi@11C8 {
+ compatible = samsung,exynos4415-mipi-dsi;
+ reg = 0x11C8 0x1;
+ interrupts = 0 83 0;
+ samsung,phy-type = 0;
+ samsung,power-domain = pd_lcd0;
+ phys = mipi_phy 1;
+ phy-names = dsim;
+ clocks = cmu CLK_DSIM0, cmu CLK_SCLK_MIPI0;
+ clock-names = bus_clk, pll_clk;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
hsotg: hsotg@1248 {
compatible = samsung,s3c6400-hsotg;
reg = 0x1248 0x2;
--
1.9.0
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[PATCH 3/4] ARM: dts: add fimd device node to exynos4415.dtsi
This patch adds fimd device node to exynos4415.dtsi.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4415.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4415.dtsi
b/arch/arm/boot/dts/exynos4415.dtsi
index c1c9b37..30acb3a 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -234,6 +234,18 @@
interrupts = 0 240 0;
};
+ fimd: fimd@11C0 {
+ compatible = samsung,exynos4415-fimd;
+ reg = 0x11C0 0x3;
+ interrupt-names = fifo, vsync, lcd_sys;
+ interrupts = 0 84 0, 0 85 0, 0 86 0;
+ clocks = cmu CLK_SCLK_FIMD0, cmu CLK_FIMD0;
+ clock-names = sclk_fimd, fimd;
+ samsung,power-domain = pd_lcd0;
+ samsung,sysreg = sysreg_system_controller;
+ status = disabled;
+ };
+
hsotg: hsotg@1248 {
compatible = samsung,s3c6400-hsotg;
reg = 0x1248 0x2;
--
1.9.0
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[PATCH 1/4] drm/exynos: dsi: support Exynos4415 SoC
This patch supports Exynos4415 SoC.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
Documentation/devicetree/bindings/video/exynos_dsim.txt | 1 +
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt
b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index e74243b..ca2b4aa 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: value should be one of the following
samsung,exynos3250-mipi-dsi /* for Exynos3250/3472 SoCs */
samsung,exynos4210-mipi-dsi /* for Exynos4 SoCs */
+ samsung,exynos4415-mipi-dsi /* for Exynos4415 SoC */
samsung,exynos5410-mipi-dsi /* for Exynos5410/5420/5440 SoCs
*/
- reg: physical base address and length of the registers set for the device
- interrupts: should contain DSI interrupt
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index acf7e9e..ff17c6e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -316,6 +316,11 @@ static struct exynos_dsi_driver_data
exynos4_dsi_driver_data = {
.has_clklane_stop = 1,
};
+static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+ .has_clklane_stop = 1,
+};
+
static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
.plltmr_reg = 0x58,
};
@@ -325,6 +330,8 @@ static struct of_device_id exynos_dsi_of_match[] = {
.data = exynos3_dsi_driver_data },
{ .compatible = samsung,exynos4210-mipi-dsi,
.data = exynos4_dsi_driver_data },
+ { .compatible = samsung,exynos4415-mipi-dsi,
+ .data = exynos4415_dsi_driver_data },
{ .compatible = samsung,exynos5410-mipi-dsi,
.data = exynos5_dsi_driver_data },
{ }
--
1.9.0
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[PATCH 0/4] drm/exynos: support Exynos4415 SoC
This patch series adds of_device_id and relevant device nodes for Exynos4415 SoC support. This is based on exynos-drm-next branch for drm/exynos, and is based on for-next branch in linux-samsung git for dts. I think this requires rebase for the patch drm/exynos: add has_vtsel flag[1]. [1] http://www.spinics.net/lists/dri-devel/msg71092.html YoungJun Cho (4): drm/exynos: dsi: support Exynos4415 SoC drm/exynos: fimd: support Exynos4415 SoC ARM: dts: add fimd device node to exynos4415.dtsi ARM: dts: add mipi dsi device node to exynos4415.dtsi .../devicetree/bindings/video/exynos_dsim.txt | 1 + .../devicetree/bindings/video/samsung-fimd.txt | 1 + arch/arm/boot/dts/exynos4415.dtsi | 27 ++ drivers/gpu/drm/exynos/exynos_drm_dsi.c| 7 ++ drivers/gpu/drm/exynos/exynos_drm_fimd.c | 11 + 5 files changed, 47 insertions(+) -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] ARM: dts: add board dts file for Exynos3250-based Monk board
From: Youngjun Cho yj44@samsung.com
This patch adds new board dts file to support Samsung Monk board which is
based on Exynos3250 SoC and has different H/W configuration from Rinato.
This patch is based on linux-samsung.git for-next branch and depends on
[PATCHv2 0/2] ARM: dts: Add new board dts file for Exynos3250-based Rinato board
Changes from v1:
- The 'memory' entries coalesce into one entry
- Removes useless space
- Puts voltage-regulator-0 under the root node
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
- RTC of Exynos3250
- ADC of Exynos3250 with NTC thermistor
- I2S of Exynos3250
- TMU of Exynos3250
- Secure firmware for Exynos3250 secondary cpu boot
- Serial ports of Exynos3250
- gpio-key for power key
Signed-off-by: Youngjun Cho yj44@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Inki Dae inki@samsung.com
Signed-off-by: Seung-Woo Kim sw0312@samsung.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/exynos3250-monk.dts | 583 ++
2 files changed, 585 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/exynos3250-monk.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5728918..0c8ae64 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,7 +64,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
-dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-rinato.dtb \
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
+ exynos3250-rinato.dtb \
exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
new file mode 100644
index 000..615672f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -0,0 +1,583 @@
+/*
+ * Samsung's Exynos3250 based Monk board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Monk board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include exynos3250.dtsi
+#include dt-bindings/input/input.h
+
+/ {
+ model = Samsung Monk board;
+ compatible = samsung,monk, samsung,exynos3250, samsung,exynos3;
+
+ aliases {
+ i2c7 = i2c_max77836;
+ };
+
+ memory {
+ reg = 0x4000 0x1ff0;
+ };
+
+ chosen {
+ bootargs = console=ttySAC1,115200N8 root=/dev/mmcblk0p15
rootwait earlyprintk panic=5;
+ };
+
+ firmware@0205F000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x0205F000 0x1000;
+ };
+
+ gpio_keys {
+ compatible = gpio-keys;
+
+ power_key {
+ interrupt-parent = gpx2;
+ interrupts = 7 0;
+ gpios = gpx2 7 1;
+ linux,code = KEY_POWER;
+ label = power key;
+ debounce-interval = 10;
+ gpio-key,wakeup;
+ };
+ };
+
+ vemmc_reg: voltage-regulator-0 {
+ compatible = regulator-fixed;
+ regulator-name = V_EMMC_2.8V-fixed;
+ regulator-min-microvolt = 280;
+ regulator-max-microvolt = 280;
+ gpio = gpk0 2 0;
+ enable-active-high;
+ };
+
+ i2c_max77836: i2c-gpio-0 {
+ compatible = i2c-gpio;
+ gpios = gpd0 2 0, gpd0 3 0;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ max77836: subpmic@25 {
+ compatible = maxim,max77836;
+ interrupt-parent = gpx1;
+ interrupts = 5 0;
+ reg = 0x25;
+ wakeup;
+
+ muic: max77836-muic {
+ compatible = maxim,max77836-muic;
+ };
+
+ regulators {
+ compatible = maxim,max77836-regulator;
+ safeout_reg: SAFEOUT {
+ regulator-name = SAFEOUT;
+ };
+
+ charger_reg: CHARGER {
+ regulator-name = CHARGER
[PATCH] ARM: dts: add board dts file for Exynos3250-based Monk board
From: Youngjun Cho yj44@samsung.com
This patch adds new board dts file to support Samsung Monk board which is
based on Exynos3250 SoC and has different H/W configuration from Rinato.
This patch is based on linux-samsung.git for-next branch and depends on
[PATCH 0/2] ARM: dts: Add new board dts file for Exynos3250-based Rinato
board[1]
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
- RTC of Exynos3250
- ADC of Exynos3250 with NTC thermistor
- I2S of Exynos3250
- TMU of Exynos3250
- Secure firmware for Exynos3250 secondary cpu boot
- Serial ports of Exynos3250
- gpio-key for power key
[1] http://www.spinics.net/lists/arm-kernel/msg366849.html
Signed-off-by: Youngjun Cho yj44@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Inki Dae inki@samsung.com
Signed-off-by: Seung-Woo Kim sw0312@samsung.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/exynos3250-monk.dts | 592 ++
2 files changed, 594 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/exynos3250-monk.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5728918..0c8ae64 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,7 +64,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
-dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-rinato.dtb \
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
+ exynos3250-rinato.dtb \
exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
new file mode 100644
index 000..9e94294
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -0,0 +1,592 @@
+/*
+ * Samsung's Exynos3250 based Monk board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Monk board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include exynos3250.dtsi
+#include dt-bindings/input/input.h
+
+/ {
+ model = Samsung Monk board;
+ compatible = samsung,monk, samsung,exynos3250, samsung,exynos3;
+
+ aliases {
+ i2c7 = i2c_max77836;
+ };
+
+ memory {
+ reg = 0x4000 0x0800
+ 0x4800 0x0800
+ 0x5000 0x0800
+ 0x5800 0x07F0;
+ };
+
+ chosen {
+ bootargs = console=ttySAC1,115200N8 root=/dev/mmcblk0p15
rootwait earlyprintk panic=5;
+ };
+
+ firmware@0205F000 {
+ compatible = samsung,secure-firmware;
+ reg = 0x0205F000 0x1000;
+ } ;
+
+ gpio_keys {
+ compatible = gpio-keys;
+
+ power_key {
+ interrupt-parent = gpx2;
+ interrupts = 7 0;
+ gpios = gpx2 7 1;
+ linux,code = KEY_POWER;
+ label = power key;
+ debounce-interval = 10;
+ gpio-key,wakeup;
+ };
+ };
+
+ regulators {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ vemmc_reg: voltage-regulator-0 {
+ compatible = regulator-fixed;
+ regulator-name = V_EMMC_2.8V-fixed;
+ regulator-min-microvolt = 280;
+ regulator-max-microvolt = 280;
+ gpio = gpk0 2 0;
+ enable-active-high;
+ };
+ };
+
+ i2c_max77836: i2c-gpio-0 {
+ compatible = i2c-gpio;
+ gpios = gpd0 2 0, gpd0 3 0;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ max77836: subpmic@25 {
+ compatible = maxim,max77836;
+ interrupt-parent = gpx1;
+ interrupts = 5 0;
+ reg = 0x25;
+ wakeup;
+
+ muic: max77836-muic {
+ compatible = maxim,max77836-muic;
+ };
+
+ regulators {
+ compatible = maxim,max77836-regulator;
+ safeout_reg: SAFEOUT
[PATCH] drm/exynos: dsi: fix exynos_dsi_set_pll() wrong return value
The type of this function is unsigned long, and it is expected
to return proper fout value or zero if something is wrong.
So this patch fixes wrong return value for error cases.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 86aebd8..061017b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -421,7 +421,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
if (!fout) {
dev_err(dsi-dev,
failed to find PLL PMS for requested frequency\n);
- return -EFAULT;
+ return 0;
}
dev_dbg(dsi-dev, PLL freq %lu, (p %d, m %d, s %d)\n, fout, p, m, s);
@@ -453,7 +453,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
do {
if (timeout-- == 0) {
dev_err(dsi-dev, PLL failed to stabilize\n);
- return -EFAULT;
+ return 0;
}
reg = readl(dsi-reg_base + DSIM_STATUS_REG);
} while ((reg DSIM_PLL_STABLE) == 0);
--
1.9.0
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Re: [PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support
Hi Inki, Andrzej On 08/11/2014 04:09 PM, Inki Dae wrote: On 2014년 08월 08일 18:40, Andrzej Hajda wrote: On 08/08/2014 11:02 AM, Andrzej Hajda wrote: On 08/08/2014 09:37 AM, Inki Dae wrote: On 2014년 08월 08일 16:03, Thierry Reding wrote: On Fri, Aug 08, 2014 at 10:45:47AM +0900, Inki Dae wrote: On 2014년 08월 07일 22:55, Thierry Reding wrote: On Thu, Aug 07, 2014 at 10:39:29PM +0900, Inki Dae wrote: On 2014년 08월 07일 22:17, Thierry Reding wrote: On Thu, Aug 07, 2014 at 10:05:44PM +0900, Inki Dae wrote: On 2014년 08월 07일 20:09, Thierry Reding wrote: On Thu, Aug 07, 2014 at 07:49:03PM +0900, Inki Dae wrote: On 2014년 08월 07일 18:09, Thierry Reding wrote: On Thu, Aug 07, 2014 at 04:51:18PM +0900, Inki Dae wrote: On 2014년 08월 07일 15:58, Thierry Reding wrote: On Thu, Aug 07, 2014 at 02:09:19AM +0900, Inki Dae wrote: 2014-08-06 16:43 GMT+09:00 Thierry Reding thierry.red...@gmail.com: [...] As far as I can tell non-continuous mode simply means that the host can turn off the HS clock after a high-speed transmission. I think Andrzej mentioned this already in another subthread, but this is an optional mode that peripherals can support if they have extra circuitry that provides an internal clock. Peripherals that don't have such circuitry may rely on the HS clock to perform in between transmissions and therefore require the HS clock to be always on (continuous mode). That's what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises that the peripheral supports non-continuous mode and therefore the host can turn the HS clock off after high-speed transmissions. What I don't make sure is this sentence. With MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible operations. One is, 1. host controller will generates signals if a bit of a register related to non-contiguous clock mode is set or unset. 2. And then video data is transmitted to panel in HS mode. 3. And then D-PHY detects LP-11 signal (positive and negative lane all are high). 4. And then D-PHY disables HS clock of host controller. 5. At this time, operation mode of host controller becomes LPM. Other is, 1. host controller will generates signals if a bit of a register related to non-contiguous clock mode is set or unset. 2. And then D-PHY detects LP-11 signal (positive and negative lane all are high). 3. And then video data is transmitted to panel in LPM. 4. At this time, operation mode of host controller becomes LPM. It seems that you says latter case. No. High speed clock and low power mode are orthogonal. Non-continuous mode simply means that the clock lane enters LP-11 between HS transmissions (see 5.6 Clock Management of the DSI specification). It seems that clock lane enters LP-11 regardless of HS clock enabled if non-continous mode is used. Right? No, I think as long as HS clock is enabled the clock lane won't enter LP-11. Non-continuous mode means that the controller can disable the HS clock between HS transmissions. So in non-continuous mode the clock lane can enter LP-11 because the controller disables the HS clock. It makes me a little bit confusing. You said if HS clock is enabled, the the clock lane won't enter LP-11 But you said again the clock lane can enter LP-11 because the controller disables the HS clock What is the meaning? It means that if the HS clock is enabled, then the clock lane is not in LP-11. When the HS clock stops, then the clock lane enters LP-11. In continuous mode, then the clock will never be disabled, hence the clock lane will never enter LP-11. And also it seems that non-continous mode is different from LPM at all because with non-continuous mode, command data is transmitted to panel in HS mode, but with LPM, command data is transmitted to panel in LP mode. Also right? No. I think you can send command data to the peripheral in low power mode in both continuous and non-continuous clock modes. If so, shouldn't the host driver disable HS clock, in case of LP mode, before the host driver transmits command data? No. If the peripheral doesn't support non-continuous mode, then the HS clock must never be turned off. On the other hand, if the peripheral supports non-continuous mode, then the DSI host should automatically disable the HS clock between high-speed transmissions. That means if a packet is transmitted in low power mode the DSI host will not be transmitting in high-speed mode and therefore disable the HS clock. What is LPM you think? I thought LPM is LP-11 and HS clock disabled. So for LPM transfer, lanes should be LP-11 state and also HS clock of the host controller should be disabled. No. I don't think any transmissions can happen when all lanes are in LP-11 state. The MIPI_DSI_MSG_USE_LPM is used to specify that a packet should be transmitted in low power mode (see LP Transmission in 2.1 Definitions of the MIPI DSI specification). Hm.. I see. I meant, if (flags MIPI_DSI_MSG_USE_LPM) disable HS clock - required. transmit command data - in LPM. No. Disabling the HS clock is not
Re: [PATCH v6 10/14] drm/panel: add S6E3FA0 driver
Hi Thierry,
Sorry for late reply.
I implemented common DSI helper functions and tested in s6e3fa0 panel
(I should test with other panels).
The helper function prototypes are like below:
int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
u16 size);
int mipi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi);
int mipi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi);
int mipi_dcs_set_display_off(struct mipi_dsi_device *dsi);
int mipi_dcs_set_display_on(struct mipi_dsi_device *dsi);
int mipi_dcs_set_tear_off(struct mipi_dsi_device *dsi);
enum mipi_dcs_tear_mode {
MIPI_DCS_TEAR_MODE_VBLANK,
MIPI_DCS_TEAR_MODE_HVBLANK,
};
int mipi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
enum mipi_dcs_tear_mode mode);
Last time you recommended to implement mipi_dcs_set_tear_on() unrelated
with mipi_dsi_dcs_write().
As you know, the only difference between mipi_dcs_xxx() except
mipi_dcs_set_tear_on() is data(dcs command).
So I think it's better to use mipi_dsi_dcs_write() instead.
Do you agree?
And one more thing.
From my point of view there is no initialization sequence in simple
panel driver, so this and s6e8aa0 panel couldn't use that interface.
The s6e3fa0 and s6e8aa0 are very similar so I think it is possible to
combine together like simple panel driver.
I want to ask you for advice on this.
Thank you.
Best regards YJ
On 07/22/2014 12:56 PM, YoungJun Cho wrote:
Hi Thierry,
Now I understand what you mean.
I'll implement common DSI helper functions.
Thank you.
Best regards YJ
On 07/21/2014 06:35 PM, Thierry Reding wrote:
On Fri, Jul 18, 2014 at 10:49:35AM +0900, YoungJun Cho wrote:
Hi Thierry,
Thank you a lot for kind comments.
On 07/17/2014 07:36 PM, Thierry Reding wrote:
On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
[...]
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
[...]
+static void s6e3fa0_set_maximum_return_packet_size(struct s6e3fa0
*ctx,
+unsigned int size)
+{
+struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx-dev);
+const struct mipi_dsi_host_ops *ops = dsi-host-ops;
+
+if (ops ops-transfer) {
+unsigned char buf[] = {size, 0};
+struct mipi_dsi_msg msg = {
+.channel = dsi-channel,
+.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
+.tx_len = sizeof(buf),
+.tx_buf = buf
+};
+
+ops-transfer(dsi-host, msg);
+}
+}
The Set Maximum Return Packet Size command is a standard command, so
please turn that into a generic function exposed by the DSI core.
For this and below standard DCS commands, you want to use generic
functions,
but I have no idea for that.
Could you explain more detail?
The goal should be to make these standard DCS commands available to all
DSI peripherals, so the implementation should look something like this:
static int mipi_dsi_set_maximum_return_packet_size(struct
mipi_dsi_device *dsi,
u16 size)
{
struct mipi_dsi_msg msg;
if (!dsi-ops || !dsi-ops-transfer)
return -ENOSYS;
memset(msg, 0, sizeof(msg));
msg.channel = dsi-channel;
msg.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE;
msg.tx_len = sizeof(size);
msg.tx_buf = size;
return dsi-ops-transfer(dsi-host, msg);
}
The above is somewhat special, since it isn't DCS. For DCS I'd suggest a
common prefix, like so:
enum mipi_dcs_tear_mode {
MIPI_DCS_TEAR_VBLANK,
MIPI_DCS_TEAR_BLANK,
};
static int mipi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
enum mipi_dcs_tear_mode mode)
{
u8 data[2] = { MIPI_DSI_DCS_SET_TEAR_ON, mode };
struct mipi_dsi_msg msg;
if (!dsi-ops || !dsi-ops-transfer)
return -ENOSYS;
memset(msg, 0, sizeof(msg));
msg.channel = dsi-channel;
msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
msg.tx_len = sizeof(data);
msg.tx_buf = data;
return dsi-ops-transfer(dsi-host, msg);
}
Thierry
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Re: [PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support
Hi Andrzej,
On 07/29/2014 01:09 AM, Andrzej Hajda wrote:
On 07/28/2014 04:00 AM, Inki Dae wrote:
This patch adds below two flags for LPM transfer, and it attaches LPM flags
to a msg in accordance with master's mode_flags set by LCD Panel driver.
MIPI_DSI_MODE_CMD_LPM
- If this flag is set by Panel driver, MIPI-DSI controller will tranfer
command data to Panel device in Low Power Mode.
What do you mean by command data? It could be:
- all transfer in command mode of operations,
- transfer initialized by the driver by writing to DSIM registers.
The 2nd one.
MIPI_DSI_MODE_VIDEO_LPM
- If this flag is set by Panel driver, MIPI-DSI controller will tranfer
image data to Panel device in Low Power Mode.
What is the meaning of this flag in case of command mode of operation?
I'm also not sure that there is a case to transfer image data in Low
Power Mode, but this flag is not related with 'command mode' only.
Inki may consider generic condition.
Maybe it would be better to create flags based on source of data/FIFOs:
- commands send by SFR registers,
- commands generated from data sent from Display Controller.
And above two flags can be combined together to transfer command and video
data to Panel device.
MIPI DSI spec says,
the host processor controls the desired mode of clock operation.
Host protocol and applications control Clock Lane operating mode
(High Speed or Low Power mode). System designers are responsible
for understanding the clock requirements for peripherals attached
to DSI and controlling clock behavior in accordance with those
requirements.
Some LCD Panel devices, nt35502a, would need LPM transfer support
because they should receive some initial commands with LPM by default
hardware setting.
Is this requirement for initial commands, or for all commands.
Btw what is the mode of operation of nt35502a? What flags do you need
for it?
The nt35502a panel is video(RGB) mode panel and it requires low power
mode for initial commands, which means to initialize nt35502a panel, the
initial commands are transferred by LP mode(Not HS mode).
And after initialization, its other features like gamma control or etc
could be controlled in HS mode.
Thank you.
Best regards YJ
Changelog v2: just add more descriptions.
Signed-off-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/drm_mipi_dsi.c |3 +++
include/drm/drm_mipi_dsi.h |4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index e633df2..6b2bbda 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -232,6 +232,9 @@ int mipi_dsi_dcs_write(struct mipi_dsi_device *dsi,
unsigned int channel,
break;
}
+ if (dsi-mode_flags MIPI_DSI_MODE_CMD_LPM)
+ msg.flags = MIPI_DSI_MSG_USE_LPM;
+
return ops-transfer(dsi-host, msg);
}
Shouldn't this be also the same for dcs read?
Anyway I think check in the DSIM should be used instead, as panel driver
can issue other dsi transfers without MIPI_DSI_MSG_USE_LPM flag set.
Regards
Andrzej
EXPORT_SYMBOL(mipi_dsi_dcs_write);
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..1c41e49 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -94,6 +94,10 @@ void mipi_dsi_host_unregister(struct mipi_dsi_host *host);
#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)
/* disable EoT packets in HS mode */
#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
+/* command low power mode */
+#define MIPI_DSI_MODE_CMD_LPM BIT(10)
+/* video low power mode */
+#define MIPI_DSI_MODE_VIDEO_LPMBIT(11)
enum mipi_dsi_pixel_format {
MIPI_DSI_FMT_RGB888,
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Re: [PATCH v6 10/14] drm/panel: add S6E3FA0 driver
Hi Thierry,
On 07/22/2014 04:49 PM, Thierry Reding wrote:
On Tue, Jul 22, 2014 at 12:41:21PM +0900, YoungJun Cho wrote:
On 07/21/2014 08:18 PM, Andrzej Hajda wrote:
On 07/21/2014 11:19 AM, Thierry Reding wrote:
On Mon, Jul 21, 2014 at 10:56:08AM +0200, Andrzej Hajda wrote:
On 07/18/2014 03:49 AM, YoungJun Cho wrote:
On 07/17/2014 07:36 PM, Thierry Reding wrote:
On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
[...]
+static void s6e3fa0_read_mtp_id(struct s6e3fa0 *ctx)
+{
+ unsigned char id[MTP_ID_LEN];
+ int ret;
+
+ s6e3fa0_set_maximum_return_packet_size(ctx, MTP_ID_LEN);
+ ret = s6e3fa0_dcs_read(ctx, MIPI_DCS_GET_DISPLAY_ID, id, MTP_ID_LEN);
This also looks like a standard DCS command. I can't find it in either
v1.01 nor v1.02 of the specification, though. Do you know where it's
specified?
Yes, I also can't find it in DCS specification and there is no special
description in panel datasheet.
But as it is declared in include/video/mipi_display.h, so I think it
is a standard one.
On page 9 of the Introduction of MIPI by Renesas [2] there is info
it is a part of Nokia I/F command list, I guess it is kind of alpha
version of MIPI DCS.
[2]: http://wenku.baidu.com/view/658fab68af1ffc4ffe47acbe.html
That link is the only one which contains Nokia I/F command list on the
internet (that is, according to Google). But since this is already part
of the mipi_display.h header file we may as well use it.
I wonder if perhaps the READ_DDB_START and READ_DDB_CONTINUE commands
could be used as a replacement for this display ID.
There is a simple description for Read DDB Start(A1H) like below.
- This command returns supplier identification and display module model /
revision information.
- NOTE: This information is not the same what Read IDs(04H) command is
returning.
For reference, Read IDs(04H) description is like below.
- This read command returns 24-bit display identification information.
- The first read byte identifies the OLED module's manufacturer.
- The Second read byte is used to track the OLED module/driver version.
- The third read byte identifies the OLED module/driver.
Okay, that explains things a little better. Can you point me to the
document that this is from?
Sorry, I forgot to write specification name.
This specification is s6e3fa0 data sheet and it is confidential.
So I quoted only that portion.
But what I was trying to say is that if the Read IDs command isn't an
official DCS command, maybe it would be a better idea to use the DDB
instead. I assume that even if it isn't the same information it would
at least be a superset and therefore a suitable replacement.
This panel has several versions and each should set specific tuning
value especially for AID, ELVSS and etc.
(Current is suitable for id[2] == 0x23).
I'll check READ_DDB_START READ_DDB_CONTINUE result and try to use them
if it is possible.
Thank you.
Best regards YJ
Thierry
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Re: [PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
Hi Andrzej,
On 07/22/2014 07:12 PM, Andrzej Hajda wrote:
On 07/22/2014 03:23 AM, Inki Dae wrote:
On 2014년 07월 21일 23:01, Andrzej Hajda wrote:
On 07/17/2014 11:01 AM, YoungJun Cho wrote:
To support LCD I80 interface, the DSI host should register
TE interrupt handler from the TE GPIO of attached panel.
So the panel generates a tearing effect synchronization signal
then the DSI host calls the CRTC device manager to trigger
to transfer video image.
This whole patch seems to be a hack.
I think it is not a good idea to parse property of one device by another
device's driver.
Especially here TE GPIO belongs to the panel. The panel driver should
know how to configure it and how to use it or not. The panel driver will
generate TE signal based on this GPIO, DSI/BTA mechanism or any other
mechanism provided by the panel.
TE signal should be delivered to the display controller. The only role
of DSIM here is that it is between the panel and the display controller
so it should be used to route this signal to DC.
According to specs TE signal should/can be generated by DBI and DSI
command mode panels, so its handling should be more generic, not Exynos
specific.
Right. However, it seems that there are no much users using command mode
panel so we would need more times to discuss the generic way. I think we
can have this feature in specific to Exynos drm - it doesn't affect
other SoC -. Actually, I know OMAP people handle this feature in a way
specific to OMAP SoC. If other users need more generic way to this
feature then we could have a discussion about the generic way at that time.
That is why Mr. Cho implemented TE feature like this. Do you have more
good idea? I wish the idea would be specific so that Mr. Cho can
implement it.
P.s. Thierry already opposed the use of mipi_dsi_host_ops, I agree with
him. And also it seems not good to use crtc and encoder/connector
because these frameworks are common to all architecture including x86 so
other architectures wouldn't need TE feature.
The good thing is that DT bindings in this case are OK, TE GPIO is in
panel node.
Maybe we can leave it this way for now, but at least lets add a comment to
the code describing that it is temporary solution and should be make
more generic in the future.
Okay, I'll leave this comment at exynos_dsi_host_attach() before current
exynos_dsi_register_te_irq() relevant comment.
Thank you.
Best regards YJ
Regards
Andrzej
Thanks,
Inki Dae
Regards
Andrzej
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 95 -
1 file changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 58bfb2a..4997bfe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -16,7 +16,9 @@
#include drm/drm_panel.h
#include linux/clk.h
+#include linux/gpio/consumer.h
#include linux/irq.h
+#include linux/of_gpio.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
#include linux/component.h
@@ -24,6 +26,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -247,6 +250,7 @@ struct exynos_dsi {
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
+ int te_gpio;
u32 pll_clk_rate;
u32 burst_clk_rate;
@@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
+{
+ struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+
+ return IRQ_HANDLED;
+}
+
+static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
+{
+ enable_irq(dsi-irq);
+
+ if (gpio_is_valid(dsi-te_gpio))
+ enable_irq(gpio_to_irq(dsi-te_gpio));
+}
+
+static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
+{
+ if (gpio_is_valid(dsi-te_gpio))
+ disable_irq(gpio_to_irq(dsi-te_gpio));
+
+ disable_irq(dsi-irq);
+}
+
static int exynos_dsi_init(struct exynos_dsi *dsi)
{
exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
- enable_irq(dsi-irq);
+ exynos_dsi_enable_irq(dsi);
exynos_dsi_wait_for_reset(dsi);
exynos_dsi_init_link(dsi);
return 0;
}
+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
+{
+ int ret;
+
+ dsi-te_gpio = of_get_named_gpio(dsi-panel_node, te-gpios, 0);
+ if (!gpio_is_valid(dsi-te_gpio)) {
+ dev_err(dsi-dev, no te-gpios specified\n
[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
This is a temporary solution and should be made by more
generic way.
To support LCD I80 interface, the DSI host should register
TE interrupt handler from the TE GPIO of attached panel.
So the panel generates a tearing effect synchronization signal
then the DSI host calls the CRTC device manager to trigger
to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 97 -
1 file changed, 95 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 58bfb2a..3adad44 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -16,7 +16,9 @@
#include drm/drm_panel.h
#include linux/clk.h
+#include linux/gpio/consumer.h
#include linux/irq.h
+#include linux/of_gpio.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
#include linux/component.h
@@ -24,6 +26,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -247,6 +250,7 @@ struct exynos_dsi {
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
+ int te_gpio;
u32 pll_clk_rate;
u32 burst_clk_rate;
@@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
+{
+ struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+
+ return IRQ_HANDLED;
+}
+
+static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
+{
+ enable_irq(dsi-irq);
+
+ if (gpio_is_valid(dsi-te_gpio))
+ enable_irq(gpio_to_irq(dsi-te_gpio));
+}
+
+static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
+{
+ if (gpio_is_valid(dsi-te_gpio))
+ disable_irq(gpio_to_irq(dsi-te_gpio));
+
+ disable_irq(dsi-irq);
+}
+
static int exynos_dsi_init(struct exynos_dsi *dsi)
{
exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
- enable_irq(dsi-irq);
+ exynos_dsi_enable_irq(dsi);
exynos_dsi_wait_for_reset(dsi);
exynos_dsi_init_link(dsi);
return 0;
}
+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
+{
+ int ret;
+
+ dsi-te_gpio = of_get_named_gpio(dsi-panel_node, te-gpios, 0);
+ if (!gpio_is_valid(dsi-te_gpio)) {
+ dev_err(dsi-dev, no te-gpios specified\n);
+ ret = dsi-te_gpio;
+ goto out;
+ }
+
+ ret = gpio_request_one(dsi-te_gpio, GPIOF_IN, te_gpio);
+ if (ret) {
+ dev_err(dsi-dev, gpio request failed with %d\n, ret);
+ goto out;
+ }
+
+ /*
+* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
+* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
+* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
+* called by drm_panel_init() before panel is attached.
+*/
+ ret = request_threaded_irq(gpio_to_irq(dsi-te_gpio),
+ exynos_dsi_te_irq_handler, NULL,
+ IRQF_TRIGGER_RISING, TE, dsi);
+ if (ret) {
+ dev_err(dsi-dev, request interrupt failed with %d\n, ret);
+ gpio_free(dsi-te_gpio);
+ goto out;
+ }
+
+out:
+ return ret;
+}
+
+static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
+{
+ if (gpio_is_valid(dsi-te_gpio)) {
+ free_irq(gpio_to_irq(dsi-te_gpio), dsi);
+ gpio_free(dsi-te_gpio);
+ dsi-te_gpio = -ENOENT;
+ }
+}
+
static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
@@ -978,6 +1054,18 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host
*host,
if (dsi-connector.dev)
drm_helper_hpd_irq_event(dsi-connector.dev);
+ /*
+* This is a temporary solution and should be made by more generic way.
+*
+* If attached panel device is for command mode one, dsi should register
+* TE interrupt handler.
+*/
+ if (!(dsi-mode_flags MIPI_DSI_MODE_VIDEO)) {
+ int ret = exynos_dsi_register_te_irq(dsi);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
@@ -986,6 +1074,8 @@ static int exynos_dsi_host_detach(struct mipi_dsi_host
*host,
{
struct exynos_dsi *dsi = host_to_dsi(host
Re: [PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
Hi Varka,
This irq handler should be registered in attach() and unregistered in
detach().
The devm_* APIs are released(freed) in remove(), right?
Logically the panel could be attached and detached several times after
dsi is probed and not removed.
So I don't use devm_* APIs.
Thank you.
Best regards YJ
On 07/22/2014 07:57 PM, Varka Bhadram wrote:
On 07/22/2014 04:19 PM, YoungJun Cho wrote:
(...)
+ret = gpio_request_one(dsi-te_gpio, GPIOF_IN, te_gpio);
devm_* APIs..?
+if (ret) {
+dev_err(dsi-dev, gpio request failed with %d\n, ret);
+goto out;
+}
+
+/*
+ * This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
+ * calls drm_panel_init() first then calls mipi_dsi_attach() in
probe().
+ * It means that te_gpio is invalid when exynos_dsi_enable_irq() is
+ * called by drm_panel_init() before panel is attached.
+ */
+ret = request_threaded_irq(gpio_to_irq(dsi-te_gpio),
+exynos_dsi_te_irq_handler, NULL,
+IRQF_TRIGGER_RISING, TE, dsi);
why don't we use devm_request_threaded_irq()..?
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Re: [PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
Hi Varka, On 07/22/2014 08:14 PM, Varka Bhadram wrote: On 07/22/2014 04:40 PM, YoungJun Cho wrote: Hi Varka, This irq handler should be registered in attach() and unregistered in detach(). The devm_* APIs are released(freed) in remove(), right? Logically the panel could be attached and detached several times after dsi is probed and not removed. So I don't use devm_* APIs. You meant to say that in-case of GPIOs also you are following the same thing ..? Means requesting the GPIOs and Releasing several times ..? Yes, this TE gpio is came from panel. So it should be refresh whenever a (new) panel is attached. Thank you. Best regards YJ -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
Hi,
On 07/22/2014 10:23 AM, Inki Dae wrote:
On 2014년 07월 21일 23:01, Andrzej Hajda wrote:
On 07/17/2014 11:01 AM, YoungJun Cho wrote:
To support LCD I80 interface, the DSI host should register
TE interrupt handler from the TE GPIO of attached panel.
So the panel generates a tearing effect synchronization signal
then the DSI host calls the CRTC device manager to trigger
to transfer video image.
This whole patch seems to be a hack.
I think it is not a good idea to parse property of one device by another
device's driver.
Especially here TE GPIO belongs to the panel. The panel driver should
know how to configure it and how to use it or not. The panel driver will
generate TE signal based on this GPIO, DSI/BTA mechanism or any other
mechanism provided by the panel.
TE signal should be delivered to the display controller. The only role
of DSIM here is that it is between the panel and the display controller
so it should be used to route this signal to DC.
It looks like DSIM transfers only TE signal to FIMD, but there is one
thing important role, DSIM transfers TE signal only it is activated.
Without this thing, a broken screen would be showed at booting time.
According to specs TE signal should/can be generated by DBI and DSI
command mode panels, so its handling should be more generic, not Exynos
specific.
Right. However, it seems that there are no much users using command mode
panel so we would need more times to discuss the generic way. I think we
can have this feature in specific to Exynos drm - it doesn't affect
other SoC -. Actually, I know OMAP people handle this feature in a way
For your information, there is a dsicm_te_isr() in
drivers/video/fbdev/omap2/displays-new.
It seems like that panel - dsi - display controller.
Thank you.
Best regards YJ
specific to OMAP SoC. If other users need more generic way to this
feature then we could have a discussion about the generic way at that time.
That is why Mr. Cho implemented TE feature like this. Do you have more
good idea? I wish the idea would be specific so that Mr. Cho can
implement it.
P.s. Thierry already opposed the use of mipi_dsi_host_ops, I agree with
him. And also it seems not good to use crtc and encoder/connector
because these frameworks are common to all architecture including x86 so
other architectures wouldn't need TE feature.
Thanks,
Inki Dae
Regards
Andrzej
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 95 -
1 file changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 58bfb2a..4997bfe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -16,7 +16,9 @@
#include drm/drm_panel.h
#include linux/clk.h
+#include linux/gpio/consumer.h
#include linux/irq.h
+#include linux/of_gpio.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
#include linux/component.h
@@ -24,6 +26,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -247,6 +250,7 @@ struct exynos_dsi {
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
+ int te_gpio;
u32 pll_clk_rate;
u32 burst_clk_rate;
@@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
+{
+ struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+
+ return IRQ_HANDLED;
+}
+
+static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
+{
+ enable_irq(dsi-irq);
+
+ if (gpio_is_valid(dsi-te_gpio))
+ enable_irq(gpio_to_irq(dsi-te_gpio));
+}
+
+static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
+{
+ if (gpio_is_valid(dsi-te_gpio))
+ disable_irq(gpio_to_irq(dsi-te_gpio));
+
+ disable_irq(dsi-irq);
+}
+
static int exynos_dsi_init(struct exynos_dsi *dsi)
{
exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
- enable_irq(dsi-irq);
+ exynos_dsi_enable_irq(dsi);
exynos_dsi_wait_for_reset(dsi);
exynos_dsi_init_link(dsi);
return 0;
}
+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
+{
+ int ret;
+
+ dsi-te_gpio = of_get_named_gpio(dsi-panel_node, te-gpios, 0);
+ if (!gpio_is_valid(dsi-te_gpio)) {
+ dev_err(dsi-dev, no te-gpios specified\n);
+ ret = dsi-te_gpio;
+ goto out;
+ }
+
+ ret
Re: [PATCH v6 10/14] drm/panel: add S6E3FA0 driver
Hi,
On 07/21/2014 08:18 PM, Andrzej Hajda wrote:
On 07/21/2014 11:19 AM, Thierry Reding wrote:
On Mon, Jul 21, 2014 at 10:56:08AM +0200, Andrzej Hajda wrote:
On 07/18/2014 03:49 AM, YoungJun Cho wrote:
Hi Thierry,
Thank you a lot for kind comments.
On 07/17/2014 07:36 PM, Thierry Reding wrote:
On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
[...]
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
[...]
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER 0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT 0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL 0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM 0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1 0xf0
+#define MCS_GAMMA_UPDATE 0xf7
+#define MCS_KEY_LEV2 0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
Is this not a manufacturer specific command? I couldn't find it in the
DSI or DCS specifications, but it sounds like something standard (also
indicated by the DCS_ prefix). Can you point out the specification for
this?
Andrzej commented before and decided it as DCS one because if the value
is less than 0xb0, it is DCS one and the others are MCS one.
But still I'm not sure it is correct.
I would not say 'decided'. I have just stated that according to DCS
specification
it should be DCS command (below 0xb0), but it is not present in mipi dcs
specs.
On the other side many panels have it [1]:
[1]:
https://www.google.com/search?q=%22Write+Content+Adaptive+Brightness+Control%22
Yeah, my search yielded similar results. I wonder if this is perhaps
part of a draft future specification. I'll try to ask around some more
if anybody knows what the status of this is.
+static void s6e3fa0_read_mtp_id(struct s6e3fa0 *ctx)
+{
+ unsigned char id[MTP_ID_LEN];
+ int ret;
+
+ s6e3fa0_set_maximum_return_packet_size(ctx, MTP_ID_LEN);
+ ret = s6e3fa0_dcs_read(ctx, MIPI_DCS_GET_DISPLAY_ID, id, MTP_ID_LEN);
This also looks like a standard DCS command. I can't find it in either
v1.01 nor v1.02 of the specification, though. Do you know where it's
specified?
Yes, I also can't find it in DCS specification and there is no special
description in panel datasheet.
But as it is declared in include/video/mipi_display.h, so I think it
is a standard one.
On page 9 of the Introduction of MIPI by Renesas [2] there is info
it is a part of Nokia I/F command list, I guess it is kind of alpha
version of MIPI DCS.
[2]: http://wenku.baidu.com/view/658fab68af1ffc4ffe47acbe.html
That link is the only one which contains Nokia I/F command list on the
internet (that is, according to Google). But since this is already part
of the mipi_display.h header file we may as well use it.
I wonder if perhaps the READ_DDB_START and READ_DDB_CONTINUE commands
could be used as a replacement for this display ID.
There is a simple description for Read DDB Start(A1H) like below.
- This command returns supplier identification and display module model
/ revision information.
- NOTE: This information is not the same what Read IDs(04H) command is
returning.
For reference, Read IDs(04H) description is like below.
- This read command returns 24-bit display identification information.
- The first read byte identifies the OLED module's manufacturer.
- The Second read byte is used to track the OLED module/driver version.
- The third read byte identifies the OLED module/driver.
Adding Guennadi, Tomi, Paul and Imre on Cc since they were involved with
the original patch that added mipi_display.h. Perhaps they remember what
the origin of this command is.
I guess it was PCF8833 used in Nokia 6100 [1][2].
[1]: http://www.vintagecomputercables.com/datasheet/PCF8833_1.pdf
[2]:
http://www.elecfreaks.com/store/download/datasheet/shield/6100_Display_Driver.pdf
Yes, this command is related with Nokia.
Last Friday, I met panel vendor guy for some issues.
At the break time, I asked him for about this Read IDs(04H), why it is
not included in DCS specification.
He said that this command was originated by Nokia.
In feature phone times, most of panel vendors wanted their panels to be
used by Nokia and Nokia wanted this command, so most of panel vendors
still provide this command traditionally.
Thank you.
Best regards YJ
Regards
Andrzej
Thierry
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[PATCH v6 01/14] drm/exynos: dsi: move the EoT packets configuration point
This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 2df3592..58bfb2a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -468,13 +468,20 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
/* DSI configuration */
reg = 0;
+ /*
+* The first bit of mode_flags specifies display configuration.
+* If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
+* mode, otherwise it will support command mode.
+*/
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO) {
reg |= DSIM_VIDEO_MODE;
+ /*
+* The user manual describes that following bits are ignored in
+* command mode.
+*/
if (!(dsi-mode_flags MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
- if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
- reg |= DSIM_EOT_DISABLE;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +498,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}
+ if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
+ reg |= DSIM_EOT_DISABLE;
+
switch (dsi-format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
--
1.9.0
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[PATCH v6 12/14] ARM: dts: exynos5: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 79d0608..fdead12 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -87,6 +87,7 @@ reg = 0x1440 0x4; interrupt-names = fifo, vsync, lcd_sys; interrupts = 18 4, 18 5, 18 6; + samsung,sysreg = sysreg_system_controller; status = disabled; }; -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 04/14] drm/exynos: add TE handler to support LCD I80 interface
To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it to the display controller.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 +++
drivers/gpu/drm/exynos/exynos_drm_drv.h | 3 +++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..b68e58f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,11 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device
*drm_dev,
return -EPERM;
}
+
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+ struct exynos_drm_manager *manager = to_exynos_crtc(crtc)-manager;
+
+ if (manager-ops-te_handler)
+ manager-ops-te_handler(manager);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..690dcdd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc,
int zpos);
int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);
+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 02f3b3d..13be498 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -186,6 +186,8 @@ struct exynos_drm_display {
* @win_commit: apply hardware specific overlay data to registers.
* @win_enable: enable hardware specific overlay.
* @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
*/
struct exynos_drm_manager;
struct exynos_drm_manager_ops {
@@ -204,6 +206,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+ void (*te_handler)(struct exynos_drm_manager *mgr);
};
/*
--
1.9.0
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[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
To support LCD I80 interface, the DSI host should register
TE interrupt handler from the TE GPIO of attached panel.
So the panel generates a tearing effect synchronization signal
then the DSI host calls the CRTC device manager to trigger
to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 95 -
1 file changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 58bfb2a..4997bfe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -16,7 +16,9 @@
#include drm/drm_panel.h
#include linux/clk.h
+#include linux/gpio/consumer.h
#include linux/irq.h
+#include linux/of_gpio.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
#include linux/component.h
@@ -24,6 +26,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -247,6 +250,7 @@ struct exynos_dsi {
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
+ int te_gpio;
u32 pll_clk_rate;
u32 burst_clk_rate;
@@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
+{
+ struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+
+ return IRQ_HANDLED;
+}
+
+static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
+{
+ enable_irq(dsi-irq);
+
+ if (gpio_is_valid(dsi-te_gpio))
+ enable_irq(gpio_to_irq(dsi-te_gpio));
+}
+
+static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
+{
+ if (gpio_is_valid(dsi-te_gpio))
+ disable_irq(gpio_to_irq(dsi-te_gpio));
+
+ disable_irq(dsi-irq);
+}
+
static int exynos_dsi_init(struct exynos_dsi *dsi)
{
exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
- enable_irq(dsi-irq);
+ exynos_dsi_enable_irq(dsi);
exynos_dsi_wait_for_reset(dsi);
exynos_dsi_init_link(dsi);
return 0;
}
+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
+{
+ int ret;
+
+ dsi-te_gpio = of_get_named_gpio(dsi-panel_node, te-gpios, 0);
+ if (!gpio_is_valid(dsi-te_gpio)) {
+ dev_err(dsi-dev, no te-gpios specified\n);
+ ret = dsi-te_gpio;
+ goto out;
+ }
+
+ ret = gpio_request_one(dsi-te_gpio, GPIOF_IN, te_gpio);
+ if (ret) {
+ dev_err(dsi-dev, gpio request failed with %d\n, ret);
+ goto out;
+ }
+
+ /*
+* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
+* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
+* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
+* called by drm_panel_init() before panel is attached.
+*/
+ ret = request_threaded_irq(gpio_to_irq(dsi-te_gpio),
+ exynos_dsi_te_irq_handler, NULL,
+ IRQF_TRIGGER_RISING, TE, dsi);
+ if (ret) {
+ dev_err(dsi-dev, request interrupt failed with %d\n, ret);
+ gpio_free(dsi-te_gpio);
+ goto out;
+ }
+
+out:
+ return ret;
+}
+
+static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
+{
+ if (gpio_is_valid(dsi-te_gpio)) {
+ free_irq(gpio_to_irq(dsi-te_gpio), dsi);
+ gpio_free(dsi-te_gpio);
+ dsi-te_gpio = -ENOENT;
+ }
+}
+
static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
@@ -978,6 +1054,16 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host
*host,
if (dsi-connector.dev)
drm_helper_hpd_irq_event(dsi-connector.dev);
+ /*
+* If attached panel device is for command mode one, dsi should
+* register TE interrupt handler.
+*/
+ if (!(dsi-mode_flags MIPI_DSI_MODE_VIDEO)) {
+ int ret = exynos_dsi_register_te_irq(dsi);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
@@ -986,6 +1072,8 @@ static int exynos_dsi_host_detach(struct mipi_dsi_host
*host,
{
struct exynos_dsi *dsi = host_to_dsi(host);
+ exynos_dsi_unregister_te_irq(dsi);
+
dsi-panel_node = NULL;
if (dsi-connector.dev)
@@ -1099,7 +1187,7 @@ static void exynos_dsi_poweroff(struct
[PATCH v6 08/14] drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs
The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.
In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 +++-
1 file changed, 135 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 4997bfe..93ad4a2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -18,6 +18,7 @@
#include linux/clk.h
#include linux/gpio/consumer.h
#include linux/irq.h
+#include linux/of_device.h
#include linux/of_gpio.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
@@ -57,9 +58,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) 0xf) 0)
@@ -203,6 +207,24 @@
#define DSIM_PLL_M(x) ((x) 4)
#define DSIM_PLL_S(x) ((x) 1)
+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) 0x1ff) 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -236,6 +258,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -266,11 +294,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = samsung,exynos4210-mipi-dsi,
+ .data = exynos4_dsi_driver_data },
+ { .compatible = samsung,exynos5410-mipi-dsi,
+ .data = exynos5_dsi_driver_data },
+ { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, pdev-dev);
+
+ return (struct exynos_dsi_driver_data *)of_id-data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(dsi-completed, msecs_to_jiffies(300)))
@@ -344,14 +400,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
{
- static const unsigned long freq_bands[] = {
- 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
- 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
- 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
- 770 * MHZ, 870 * MHZ, 950 * MHZ,
- };
+ struct exynos_dsi_driver_data *driver_data = dsi-driver_data;
unsigned long fin, fout;
- int timeout, band;
+ int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -372,18 +423,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
failed to find
[PATCH v6 14/14] ARM: dts: exynos5420: add dsi node
This patch adds common part of dsi node.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 0b9d15d..3a7862b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -523,6 +523,20 @@
#phy-cells = 1;
};
+ dsi@1450 {
+ compatible = samsung,exynos5410-mipi-dsi;
+ reg = 0x1450 0x1;
+ interrupts = 0 82 0;
+ samsung,power-domain = disp_pd;
+ phys = mipi_phy 1;
+ phy-names = dsim;
+ clocks = clock CLK_DSIM1, clock CLK_SCLK_MIPI1;
+ clock-names = bus_clk, pll_clk;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
fimd: fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
--
1.9.0
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[PATCH v6 13/14] ARM: dts: exynos5420: add mipi-phy node
This patch adds mipi-phy node for MIPI DSI device.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..0b9d15d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -517,6 +517,12 @@
phy-names = dp;
};
+ mipi_phy: video-phy@10040714 {
+ compatible = samsung,s5pv210-mipi-video-phy;
+ reg = 0x10040714 12;
+ #phy-cells = 1;
+ };
+
fimd: fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
--
1.9.0
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[PATCH v6 11/14] ARM: dts: exynos4: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index fbaf426..3793881 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -608,6 +608,7 @@ clocks = clock CLK_SCLK_FIMD0, clock CLK_FIMD0; clock-names = sclk_fimd, fimd; samsung,power-domain = pd_lcd0; + samsung,sysreg = sys_reg; status = disabled; }; }; -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 02/14] drm/exynos: use wait_event_timeout() for safety usage
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc-pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (mode DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc-pending_flip_queue,
- atomic_read(exynos_crtc-pending_flip) == 0);
+ if (!wait_event_timeout(exynos_crtc-pending_flip_queue,
+ !atomic_read(exynos_crtc-pending_flip),
+ HZ/20))
+ atomic_set(exynos_crtc-pending_flip, 0);
drm_vblank_off(crtc-dev, exynos_crtc-pipe);
}
@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(dev-event_lock);
drm_vblank_put(dev, exynos_crtc-pipe);
list_del(event-base.link);
+ atomic_set(exynos_crtc-pending_flip, 0);
spin_unlock_irq(dev-event_lock);
goto out;
--
1.9.0
--
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Re: [PATCH v6 10/14] drm/panel: add S6E3FA0 driver
Hi Thierry,
Thank you a lot for kind comments.
On 07/17/2014 07:36 PM, Thierry Reding wrote:
On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
[...]
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
[...]
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER 0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT 0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL 0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM 0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1 0xf0
+#define MCS_GAMMA_UPDATE 0xf7
+#define MCS_KEY_LEV2 0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
Is this not a manufacturer specific command? I couldn't find it in the
DSI or DCS specifications, but it sounds like something standard (also
indicated by the DCS_ prefix). Can you point out the specification for
this?
Andrzej commented before and decided it as DCS one because if the value
is less than 0xb0, it is DCS one and the others are MCS one.
But still I'm not sure it is correct.
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL 0x15
+
+struct s6e3fa0 {
+ struct device *dev;
+ struct drm_panelpanel;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc*reset_gpio;
+ struct videomodevm;
+
+ unsigned intpower_on_delay;
+ unsigned intreset_delay;
+ unsigned intinit_delay;
+ unsigned intwidth_mm;
+ unsigned intheight_mm;
+
+ unsigned char id;
+ unsigned char vddm;
+ unsigned intbrightness;
+};
Please don't use this kind of artificial padding. A simple space will
do.
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
Please turn this into a function so we can get proper type checking.
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+ {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+ {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+ {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+ {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+ {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+ {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+ {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+ {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+ {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+ {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+ {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+ {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+ {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+ {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+ {0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x49, 0x03}, {0x4a, 0x02},
+ {0x4b, 0x01}, {0x4c, 0x40}, {0x4d, 0x41}, {0x4e, 0x42}, {0x4f, 0x43},
+ {0x50, 0x44}, {0x51, 0x45}, {0x52, 0x46}, {0x53, 0x47}, {0x54, 0x48},
+ {0x55, 0x49}, {0x56, 0x4a}, {0x57, 0x4b}, {0x58, 0x4c}, {0x59, 0x4d},
+ {0x5a, 0x4e}, {0x5b, 0x4f}, {0x5c, 0x50}, {0x5d, 0x51}, {0x5e, 0x52},
+ {0x5f, 0x53}, {0x60, 0x54}, {0x61, 0x55}, {0x62, 0x56}, {0x63, 0x57},
+ {0x64, 0x58}, {0x65, 0x59}, {0x66, 0x5a}, {0x67, 0x5b}, {0x68, 0x5c},
+ {0x69, 0x5d}, {0x6a, 0x5e}, {0x6b, 0x5f}, {0x6c, 0x60}, {0x6d, 0x61},
+ {0x6e, 0x62}, {0x6f, 0x63}, {0x70, 0x64}, {0x71, 0x65}, {0x72, 0x66},
+ {0x73, 0x67}, {0x74, 0x68}, {0x75, 0x69}, {0x76, 0x6a}, {0x77, 0x6b},
+ {0x78, 0x6c}, {0x79, 0x6d}, {0x7a, 0x6e}, {0x7b, 0x6f}, {0x7c, 0x70},
+ {0x7d, 0x71}, {0x7e, 0x72}, {0x7f, 0x73},
+};
What's this used for?
This ldi contains an internal memory and requires an appropriate VDD.
Each panel stores OTP value for this vddm, so reads this value, finds
matching value with vddm_lut and writes the final value to avoid noise
issues from an inappropriate VDD.
+static int s6e3fa0_dcs_read(struct s6e3fa0 *ctx, unsigned char cmd,
+ void *data, size_t len)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx-dev);
+
+ return mipi_dsi_dcs_read
Re: [PATCH v6 09/14] ARM: dts: s6e3fa0: add DT bindings
Hi Thierry, On 07/17/2014 07:38 PM, Thierry Reding wrote: On Thu, Jul 17, 2014 at 06:01:24PM +0900, YoungJun Cho wrote: This patch adds DT bindings for s6e3fa0 panel. The bindings describes panel resources and display timings. The commit message here should preferably say which platform this is used on. Although only exynos drm could use this panel now, I think this panel could be used by any platform. Do you have any good idea for that? Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt new file mode 100644 index 000..2cd32f5 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt @@ -0,0 +1,46 @@ +Samsung S6E3FA0 AMOLED LCD 5.7 inch panel + +Required properties: + - compatible: samsung,s6e3fa0 + - reg: the virtual channel number of a DSI peripheral + - vdd3-supply: core voltage supply + - vci-supply: voltage supply for analog circuits + - reset-gpios: a GPIO spec for the reset pin + - det-gpios: a GPIO spec for the OLED detection pin + - te-gpios: a GPIO spec for the TE pin + - display-timings: timings for the connected panel as described by [1] display-timings should be optional. The panel driver should provide a default mode. And only if you really need to override the default mode you should provide the option of getting an alternative set of values from DT. Could you explain why this display-timings should be optional? Most of DTs regard display-timings as required property. Thank you. Best regards YJ Thierry -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
Hi Thierry, On 07/16/2014 04:54 PM, Thierry Reding wrote: On Wed, Jul 16, 2014 at 11:23:09AM +0900, YoungJun Cho wrote: Hi Inki, On 07/15/2014 11:34 AM, Inki Dae wrote: On 2014년 07월 14일 20:03, Thierry Reding wrote: On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote: On 07/14/2014 06:41 PM, Thierry Reding wrote: [...] That said, I've been doing some research and it seems like we have a somewhat similar feature on Tegra. What happens there is that there are three GPIO pins that can be repurposed for TE signalling. But as opposed to using them as interrupts the display controller can be configured to use them, upon which it will automatically handle the TE signal by sending the next frame. Could you explain more detail how the Tegra display controller could be configured with this GPIO pins? I have no idea except that the display controller registers this GPIO as an IRQ. On Tegra the display controller has a special register that can be programmed to use one of the three GPIOs as TE signal. Then the display controller can be configured in one-shot (non-continuous) mode, which means that software needs to explicitly set a trigger bit to tell the display controller to send a new frame. If TE signalling is enabled, then the display controller will not immediately send a new frame when triggered but wait for signalling of this GPIO. So we have at least two very different implementations of this on two different SoCs. Further the specification explicitly recommends using the BTA sequence and DSI protocol to wait for TE. So I still think that controllers that provide an additional, non-spec compliant method to signal TE should handle it separately rather than within DSI. Otherwise we essentially need to make the DSI core aware of all these quirks, and I'd rather avoid that. You mean, the DSI specification guides to use BTA, so it's better to use display controller rather than DSIM, right? What I'm saying is that there's nothing about a side-band TE wire in the DSI spec. In fact the spec explicitly says that this mechanism of an external TE wire from older protocols (DBI) was replaced by the BTA sequence over the protocol. Now, my understanding is that using the BTA sequence over the DSI protocol would introduce some latency and that forces some panel vendors to still provide a side-band TE wire even in DSI compliant panels. But since this is not part of the specification there is no standard way to do this (as evidenced by Tegra and Exynos). Therefore putting such functionality into the core DSI code is bad. But that doesn't mean that you have to put this functionality into the display controller driver on Exynos. What I'm saying is that it should be handled by the SoC driver rather than the core. Where exactly probably depends on the particular case. As Inki commented before, I'll try to use remote-endpoint property of DSI device node in exynos DSIM driver and call FIMD notifier. Sounds like it matches what I said above. I'm not a huge fan of notifiers, but if it works for you I suppose that's fine. The alternative would be to directly call a FIMD function, which is somewhat more explicit than a notifier. Yes, I also like explicit call, so I want to use dsi_host_ops and calls it in panel. But there is an objection to use dis_host_ops, we think notifier in exynos dsim for fimd(display controller). There are other ways to explicitly call into the display controller. You could for example get access to the CRTC that DSIM is currently connected to (via exynos_dsi.encoder-crtc) and then cast that to a struct exynos_drm_crtc and call a function to trigger a new frame to be sent (for example exynos_drm_crtc_send_frame()). This assumes that you can safely cast struct drm_crtc * to struct exynos_drm_crtc *, but that shouldn't be a problem. With the above, you could make the DSIM handle the TE signal interrupts and trigger the DC using the new exynos_drm_crtc_send_frame() function. It seems better than the use of notifier. Actually, original patch used this way except TE event. Mr. Cho, let's use remote-endpoint property and this way instead of notifier. The struct exynos_dsi has panel_node, which is valid by exynos_dsi_host_attach() is called from panel, we could use it instead of getting new remote-endpoint node. So after called exynos_dsi_host_attach(), the dsi driver could know that the panel supports mipi command mode or video mode, and if the panel is for mipi command mode one, dsi driver gets panel te gpio and registers its irq. Why does the TE GPIO even need to be in the panel's device tree node? Wouldn't it make more sense for it to be in the DSIM node? After all that's what the GPIO is connected to, right? Well, at least logically if not physically. I also agree that the GPIO in DT means the connection after all. But the panel provides the TE pin(this is obvious) and decides the DSIM mode(command or video). This TE pin is useless in video mode. So I think
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
Hi Inki, On 07/15/2014 11:34 AM, Inki Dae wrote: On 2014년 07월 14일 20:03, Thierry Reding wrote: On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote: On 07/14/2014 06:41 PM, Thierry Reding wrote: [...] That said, I've been doing some research and it seems like we have a somewhat similar feature on Tegra. What happens there is that there are three GPIO pins that can be repurposed for TE signalling. But as opposed to using them as interrupts the display controller can be configured to use them, upon which it will automatically handle the TE signal by sending the next frame. Could you explain more detail how the Tegra display controller could be configured with this GPIO pins? I have no idea except that the display controller registers this GPIO as an IRQ. On Tegra the display controller has a special register that can be programmed to use one of the three GPIOs as TE signal. Then the display controller can be configured in one-shot (non-continuous) mode, which means that software needs to explicitly set a trigger bit to tell the display controller to send a new frame. If TE signalling is enabled, then the display controller will not immediately send a new frame when triggered but wait for signalling of this GPIO. So we have at least two very different implementations of this on two different SoCs. Further the specification explicitly recommends using the BTA sequence and DSI protocol to wait for TE. So I still think that controllers that provide an additional, non-spec compliant method to signal TE should handle it separately rather than within DSI. Otherwise we essentially need to make the DSI core aware of all these quirks, and I'd rather avoid that. You mean, the DSI specification guides to use BTA, so it's better to use display controller rather than DSIM, right? What I'm saying is that there's nothing about a side-band TE wire in the DSI spec. In fact the spec explicitly says that this mechanism of an external TE wire from older protocols (DBI) was replaced by the BTA sequence over the protocol. Now, my understanding is that using the BTA sequence over the DSI protocol would introduce some latency and that forces some panel vendors to still provide a side-band TE wire even in DSI compliant panels. But since this is not part of the specification there is no standard way to do this (as evidenced by Tegra and Exynos). Therefore putting such functionality into the core DSI code is bad. But that doesn't mean that you have to put this functionality into the display controller driver on Exynos. What I'm saying is that it should be handled by the SoC driver rather than the core. Where exactly probably depends on the particular case. As Inki commented before, I'll try to use remote-endpoint property of DSI device node in exynos DSIM driver and call FIMD notifier. Sounds like it matches what I said above. I'm not a huge fan of notifiers, but if it works for you I suppose that's fine. The alternative would be to directly call a FIMD function, which is somewhat more explicit than a notifier. Yes, I also like explicit call, so I want to use dsi_host_ops and calls it in panel. But there is an objection to use dis_host_ops, we think notifier in exynos dsim for fimd(display controller). There are other ways to explicitly call into the display controller. You could for example get access to the CRTC that DSIM is currently connected to (via exynos_dsi.encoder-crtc) and then cast that to a struct exynos_drm_crtc and call a function to trigger a new frame to be sent (for example exynos_drm_crtc_send_frame()). This assumes that you can safely cast struct drm_crtc * to struct exynos_drm_crtc *, but that shouldn't be a problem. With the above, you could make the DSIM handle the TE signal interrupts and trigger the DC using the new exynos_drm_crtc_send_frame() function. It seems better than the use of notifier. Actually, original patch used this way except TE event. Mr. Cho, let's use remote-endpoint property and this way instead of notifier. The struct exynos_dsi has panel_node, which is valid by exynos_dsi_host_attach() is called from panel, we could use it instead of getting new remote-endpoint node. So after called exynos_dsi_host_attach(), the dsi driver could know that the panel supports mipi command mode or video mode, and if the panel is for mipi command mode one, dsi driver gets panel te gpio and registers its irq. I'll try. Thank you. Best regards YJ Thanks, Inki Dae Thierry -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM, Thierry Reding wrote:
On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
include/drm/drm_mipi_dsi.h | 7 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .pass_te = exynos_dsi_host_pass_te,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal between
+ * MCU and FB to display video images. And the display controller
+ * should trigger to transfer video image at this signal. So the panel
+ * receives the TE IRQ, then calls this function to notify it to the
+ * display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ void (*pass_te)(struct mipi_dsi_host *host);
I've objected to this particular change before and that objection still
stands. I don't see how this is related to DSI. It seems like an
implementation detail of this particular setup and I think it should be
handled differently (within the Exynos DSI controller implementation
possibly).
Okay, I understand what you mean.
As you know, this function is called by panel TE interrupt handler, so it
could be accessed by panel.
Do you have any good idea for panel to access exynos_drm_dsi directly
without mipi_dis_host_ops?
I've gone through the DSI specification again and the only mention of
the tearing effect is in section 8.12 TE Signaling in DSI. That says
the following:
A Command Mode display module has its own timing controller and
local frame buffer for display refresh. In some cases the host
processor needs to be notified of timing events on the display
module, e.g. the start of vertical blanking or similar timing
information. In a traditional parallel-bus interface like DBI-2,
a dedicated signal wire labeled TE (Tearing Effect) is provided
to convey such timing information to the host processor. In a
DSI system, the same information, with reasonably low latency,
shall be transmitted from the display module to the host
processor when requested, using the bidirectional Data Lane.
My interpretation of that is that a DSI peripheral doesn't have a
dedicated TE signal. Now the panel that you want to support here seems
to have one, so I'm wondering if maybe it isn't a DSI panel at all but
rather DBI.
Uhm, this panel is DSI panel right. It provides TE external pad to
transfer TE pulse to host AP and it also provides TE relevant 3 DCS, so
host AP could choose either of them.
But I think it's better to use IRQ instead of polling method.
As Inki commented before, I'll try to use remote-endpoint property of
DSI device node in exynos DSIM driver and call FIMD notifier.
Thank you.
Best regards YJ
Re: [PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
Hi Thierry,
On 07/14/2014 06:41 PM, Thierry Reding wrote:
On Mon, Jul 14, 2014 at 06:22:39PM +0900, YoungJun Cho wrote:
Hi Thierry,
Thank you for comment.
On 07/10/2014 04:38 PM, Thierry Reding wrote:
On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
On 07/10/2014 12:22 AM, Thierry Reding wrote:
On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
include/drm/drm_mipi_dsi.h | 7 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .pass_te = exynos_dsi_host_pass_te,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal between
+ * MCU and FB to display video images. And the display controller
+ * should trigger to transfer video image at this signal. So the panel
+ * receives the TE IRQ, then calls this function to notify it to the
+ * display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ void (*pass_te)(struct mipi_dsi_host *host);
I've objected to this particular change before and that objection still
stands. I don't see how this is related to DSI. It seems like an
implementation detail of this particular setup and I think it should be
handled differently (within the Exynos DSI controller implementation
possibly).
Okay, I understand what you mean.
As you know, this function is called by panel TE interrupt handler, so it
could be accessed by panel.
Do you have any good idea for panel to access exynos_drm_dsi directly
without mipi_dis_host_ops?
I've gone through the DSI specification again and the only mention of
the tearing effect is in section 8.12 TE Signaling in DSI. That says
the following:
A Command Mode display module has its own timing controller and
local frame buffer for display refresh. In some cases the host
processor needs to be notified of timing events on the display
module, e.g. the start of vertical blanking or similar timing
information. In a traditional parallel-bus interface like DBI-2,
a dedicated signal wire labeled TE (Tearing Effect) is provided
to convey such timing information to the host processor. In a
DSI system, the same information, with reasonably low latency,
shall be transmitted from the display module to the host
processor when requested, using the bidirectional Data Lane.
My interpretation of that is that a DSI peripheral doesn't have a
dedicated TE signal. Now the panel that you want to support here seems
to have one, so I'm wondering if maybe it isn't a DSI panel at all but
rather DBI.
Uhm, this panel is DSI panel right. It provides TE external pad to transfer
TE pulse to host AP and it also provides TE relevant 3 DCS, so host AP could
choose either of them.
But I think it's better to use IRQ instead of polling method.
According to the specification you don't
[PATCH v5 06/14] drm/exynos: fimd: support LCD I80 interface
To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses lcd_sys as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one
to generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
flip request, and implements TE handler to call trigger function.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/Kconfig | 1 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 ++-
include/video/samsung_fimd.h | 3 +-
3 files changed, 235 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool Exynos DRM FIMD
depends on DRM_EXYNOS !FB_S3C
select FB_MODE_HELPERS
+ select MFD_SYSCON
help
Choose this option if you want to use Exynos FIMD for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 33161ad..28a3168 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
#include linux/of_device.h
#include linux/pm_runtime.h
#include linux/component.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include video/of_display_timing.h
#include video/of_videomode.h
@@ -61,6 +63,24 @@
/* color key value register for hardware window 1 ~ 4. */
#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0 (0x2 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) 16)
+#define LCD_WR_SETUP(x)((x) 12)
+#define LCD_WR_ACTIVE(x) ((x) 8)
+#define LCD_WR_HOLD(x) ((x) 4)
+#define I80IFEN_ENABLE (1 0)
+
/* FIMD has totally five hardware windows. */
#define WINDOWS_NR 5
@@ -68,10 +88,14 @@
struct fimd_driver_data {
unsigned int timing_base;
+ unsigned int lcdblk_offset;
+ unsigned int lcdblk_vt_shift;
+ unsigned int lcdblk_bypass_shift;
unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+ unsigned int has_vidoutcon:1;
};
static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {
static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+ .lcdblk_offset = 0x210,
+ .lcdblk_vt_shift = 10,
+ .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
};
static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+ .lcdblk_offset = 0x214,
+ .lcdblk_vt_shift = 24,
+ .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+ .has_vidoutcon = 1,
};
struct fimd_win_data {
@@ -112,15 +143,22 @@ struct fimd_context {
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem*regs;
+ struct regmap *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long irq_flags;
+ u32 vidcon0;
u32 vidcon1;
+ u32 vidout_con;
+ u32 i80ifcon;
+ booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
+ atomic_twin_updated;
+ atomic_ttriggering;
struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +281,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long
[PATCH v5 01/14] drm/exynos: dsi: move the EoT packets configuration point
This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 6302aa6..dad543a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -468,13 +468,19 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
/* DSI configuration */
reg = 0;
+ /* The first bit of mode_flags specifies display configuration.
+* If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
+* mode, otherwise it will support command mode.
+*/
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO) {
reg |= DSIM_VIDEO_MODE;
+ /*
+* The user manual describes that following bits are ignored in
+* command mode.
+*/
if (!(dsi-mode_flags MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
- if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
- reg |= DSIM_EOT_DISABLE;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +497,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}
+ if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
+ reg |= DSIM_EOT_DISABLE;
+
switch (dsi-format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
--
1.9.0
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[PATCH v5 03/14] ARM: dts: samsung-fimd: add LCD I80 interface specific properties
In case of using MIPI DSI based I80 interface panel, the relevant registers should be set. So this patch adds relevant DT bindings. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/video/samsung-fimd.txt | 28 ++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index 2dad41b..59ff61e 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -44,6 +44,34 @@ Optional Properties: - display-timings: timing settings for FIMD, as described in document [1]. Can be used in case timings cannot be provided otherwise or to override timings provided by the panel. +- samsung,sysreg: handle to syscon used to control the system registers +- i80-if-timings: timing configuration for lcd i80 interface support. + - cs-setup: clock cycles for the active period of address signal is enabled + until chip select is enabled. + If not specified, the default value(0) will be used. + - wr-setup: clock cycles for the active period of CS signal is enabled until + write signal is enabled. + If not specified, the default value(0) will be used. + - wr-active: clock cycles for the active period of CS is enabled. + If not specified, the default value(1) will be used. + - wr-hold: clock cycles for the active period of CS is disabled until write + signal is disabled. + If not specified, the default value(0) will be used. + + The parameters are defined as: + +VCLK(internal) __|¯¯|_|¯¯|_|¯¯|_|¯¯|_|¯¯ + ::::: +Address Output --:XXX::::XX + | cs-setup+1 |::: + |--|::: +Chip Select ¯¯¯|::|¯¯ + | wr-setup+1 || wr-hold+1 | + |--||--| +Write Enable||¯¯¯ +| wr-active+1| +|--| +Video Data X-- The device node can contain 'port' child nodes according to the bindings defined in [2]. The following are properties specific to those nodes: -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 00/14] drm/exynos: support LCD I80 interface display
Hi, This series adds LCD I80 interface display support for Exynos DRM driver. The FIMD(display controller) specification describes it as LCD I80 interface and the DSI specification describes it as Command mode interface. This is based on exynos-drm-next branch. The previous patches, RFC: http://www.spinics.net/lists/dri-devel/msg58898.html V1: http://www.spinics.net/lists/dri-devel/msg59291.html V2: http://www.spinics.net/lists/dri-devel/msg59867.html V3: http://www.spinics.net/lists/dri-devel/msg60708.html V4: http://www.spinics.net/lists/dri-devel/msg60943.html Changelog v2: - Fixes typo and removes unnecessary error log (commented by Andrzej Hazda) - Adds missed pendlig_flip flag clear points (commented by Daniel Kurtz) Changelog v3: - Removes generic command mode and command mode display timing interface. - Moves I80 interface timings from panel DT to the FIMD(display controller) DT. Changelog v4: - Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because it was already updated by linux-samsung-soc (commented by Vivek Gautam) Changelog v5: - Fixes FIMD vidcon0 register relevant code - Fixes panel gamma table, disable sequence - Slitely updates for code cleanup Patches 1 and 2 fix trivial bugs. Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface. The MIPI DSI command mode based panel generates Tearing Effect synchronization signal between MCU and FB to display video image, and FIMD should trigger to transfer video image at this signal. So the panel should receive the TE IRQ and call TE handler chains to notify it to the FIMD. Patches 7 and 8 implement to use Exynos5410 / 5420 / 5440 SoC DSI driver which is different from previous Exynos4 SoCs for some registers control. Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED 5.7 LCD drm panel driver. The ohters add DT property nodes to support MIPI DSI command mode. I welcome any comments. Thank you. Best regards YJ YoungJun Cho (14): drm/exynos: dsi: move the EoT packets configuration point drm/exynos: use wait_event_timeout() for safety usage ARM: dts: samsung-fimd: add LCD I80 interface specific properties drm/exynos: add TE handler to support LCD I80 interface drm/exynos: dsi: add pass TE host ops to support LCD I80 interface drm/exynos: fimd: support LCD I80 interface ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs ARM: dts: s6e3fa0: add DT bindings drm/panel: add S6E3FA0 driver ARM: dts: exynos4: add system register property ARM: dts: exynos5: add system register property ARM: dts: exynos5420: add mipi-phy node ARM: dts: exynos5420: add dsi node .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++ .../devicetree/bindings/video/exynos_dsim.txt | 4 +- .../devicetree/bindings/video/samsung-fimd.txt | 28 + arch/arm/boot/dts/exynos4.dtsi | 1 + arch/arm/boot/dts/exynos5.dtsi | 1 + arch/arm/boot/dts/exynos5420.dtsi | 20 + drivers/gpu/drm/exynos/Kconfig | 1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 15 +- drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 + drivers/gpu/drm/exynos/exynos_drm_drv.h| 3 + drivers/gpu/drm/exynos/exynos_drm_dsi.c| 181 ++- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 -- drivers/gpu/drm/panel/Kconfig | 7 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 + include/drm/drm_mipi_dsi.h | 7 + include/video/samsung_fimd.h | 3 +- 17 files changed, 1098 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 11/14] ARM: dts: exynos4: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index b8ece4b..92ee786 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -608,6 +608,7 @@ clocks = clock CLK_SCLK_FIMD0, clock CLK_FIMD0; clock-names = sclk_fimd, fimd; samsung,power-domain = pd_lcd0; + samsung,sysreg = sys_reg; status = disabled; }; }; -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 09/14] ARM: dts: s6e3fa0: add DT bindings
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+ - compatible: samsung,s6e3fa0
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: core voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin
+ - det-gpios: a GPIO spec for the OLED detection pin
+ - te-gpios: a GPIO spec for the TE pin
+ - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ panel@0 {
+ compatible = samsung,s6e3fa0;
+ reg = 0;
+ vdd3-supply = vcclcd_reg;
+ vci-supply = vlcd_reg;
+ reset-gpios = gpy7 4 0;
+ det-gpios = gpg0 6 0;
+ te-gpios = gpd1 7 0;
+
+ display-timings {
+ timings0 {
+ clock-frequency = 0;
+ hactive = 1080;
+ vactive = 1920;
+ hfront-porch = 2;
+ hback-porch = 2;
+ hsync-len = 1;
+ vfront-porch = 1;
+ vback-porch = 4;
+ vsync-len = 1;
+ };
+ };
+ };
--
1.9.0
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[PATCH v5 04/14] drm/exynos: add TE handler to support LCD I80 interface
To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it to the display controller.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 +++
drivers/gpu/drm/exynos/exynos_drm_drv.h | 3 +++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..b68e58f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,11 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device
*drm_dev,
return -EPERM;
}
+
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+ struct exynos_drm_manager *manager = to_exynos_crtc(crtc)-manager;
+
+ if (manager-ops-te_handler)
+ manager-ops-te_handler(manager);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..690dcdd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc,
int zpos);
int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);
+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 06cde45..d4e0726 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -188,6 +188,8 @@ struct exynos_drm_display {
* @win_commit: apply hardware specific overlay data to registers.
* @win_enable: enable hardware specific overlay.
* @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
*/
struct exynos_drm_manager;
struct exynos_drm_manager_ops {
@@ -206,6 +208,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+ void (*te_handler)(struct exynos_drm_manager *mgr);
};
/*
--
1.9.0
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[PATCH v5 06/14] drm/exynos: fimd: support LCD I80 interface
To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses lcd_sys as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one
to generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
flip request, and implements TE handler to call trigger function.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/Kconfig | 1 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 ++-
include/video/samsung_fimd.h | 3 +-
3 files changed, 235 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool Exynos DRM FIMD
depends on DRM_EXYNOS !FB_S3C
select FB_MODE_HELPERS
+ select MFD_SYSCON
help
Choose this option if you want to use Exynos FIMD for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 33161ad..207872d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
#include linux/of_device.h
#include linux/pm_runtime.h
#include linux/component.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include video/of_display_timing.h
#include video/of_videomode.h
@@ -61,6 +63,24 @@
/* color key value register for hardware window 1 ~ 4. */
#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0 (0x2 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) 16)
+#define LCD_WR_SETUP(x)((x) 12)
+#define LCD_WR_ACTIVE(x) ((x) 8)
+#define LCD_WR_HOLD(x) ((x) 4)
+#define I80IFEN_ENABLE (1 0)
+
/* FIMD has totally five hardware windows. */
#define WINDOWS_NR 5
@@ -68,10 +88,14 @@
struct fimd_driver_data {
unsigned int timing_base;
+ unsigned int lcdblk_offset;
+ unsigned int lcdblk_vt_shift;
+ unsigned int lcdblk_bypass_shift;
unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+ unsigned int has_vidoutcon:1;
};
static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {
static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+ .lcdblk_offset = 0x210,
+ .lcdblk_vt_shift = 10,
+ .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
};
static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+ .lcdblk_offset = 0x214,
+ .lcdblk_vt_shift = 24,
+ .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+ .has_vidoutcon = 1,
};
struct fimd_win_data {
@@ -112,15 +143,22 @@ struct fimd_context {
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem*regs;
+ struct regmap *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long irq_flags;
+ u32 vidcon0;
u32 vidcon1;
+ u32 vidout_con;
+ u32 i80ifcon;
+ booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
+ atomic_twin_updated;
+ atomic_ttriggering;
struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +281,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long
[PATCH v5 07/14] ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings
This patch adds relevant to exynos5410 compatible for exynos5410 / 5420 / 5440 SoCs support. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- Documentation/devicetree/bindings/video/exynos_dsim.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 33b5730..31036c6 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -1,7 +1,9 @@ Exynos MIPI DSI Master Required properties: - - compatible: samsung,exynos4210-mipi-dsi + - compatible: value should be one of the following + samsung,exynos4210-mipi-dsi /* for Exynos4 SoCs */ + samsung,exynos5410-mipi-dsi /* for Exynos5410/5420/5440 SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 08/14] drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs
The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.
In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 +++-
1 file changed, 135 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 76e34ca..162f74d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include linux/clk.h
#include linux/irq.h
+#include linux/of_device.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
#include linux/component.h
@@ -55,9 +56,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) 0xf) 0)
@@ -201,6 +205,24 @@
#define DSIM_PLL_M(x) ((x) 4)
#define DSIM_PLL_S(x) ((x) 1)
+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) 0x1ff) 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -234,6 +256,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -263,11 +291,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = samsung,exynos4210-mipi-dsi,
+ .data = exynos4_dsi_driver_data },
+ { .compatible = samsung,exynos5410-mipi-dsi,
+ .data = exynos5_dsi_driver_data },
+ { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, pdev-dev);
+
+ return (struct exynos_dsi_driver_data *)of_id-data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(dsi-completed, msecs_to_jiffies(300)))
@@ -341,14 +397,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
{
- static const unsigned long freq_bands[] = {
- 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
- 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
- 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
- 770 * MHZ, 870 * MHZ, 950 * MHZ,
- };
+ struct exynos_dsi_driver_data *driver_data = dsi-driver_data;
unsigned long fin, fout;
- int timeout, band;
+ int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -369,18 +420,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
failed to find PLL PMS for requested
[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
include/drm/drm_mipi_dsi.h | 7 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (dsi-state DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .pass_te = exynos_dsi_host_pass_te,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal between
+ * MCU and FB to display video images. And the display controller
+ * should trigger to transfer video image at this signal. So the panel
+ * receives the TE IRQ, then calls this function to notify it to the
+ * display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ void (*pass_te)(struct mipi_dsi_host *host);
};
/**
--
1.9.0
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[PATCH v5 14/14] ARM: dts: exynos5420: add dsi node
This patch adds common part of dsi node.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 0b9d15d..3a7862b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -523,6 +523,20 @@
#phy-cells = 1;
};
+ dsi@1450 {
+ compatible = samsung,exynos5410-mipi-dsi;
+ reg = 0x1450 0x1;
+ interrupts = 0 82 0;
+ samsung,power-domain = disp_pd;
+ phys = mipi_phy 1;
+ phy-names = dsim;
+ clocks = clock CLK_DSIM1, clock CLK_SCLK_MIPI1;
+ clock-names = bus_clk, pll_clk;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
fimd: fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
--
1.9.0
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[PATCH v5 12/14] ARM: dts: exynos5: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 79d0608..fdead12 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -87,6 +87,7 @@ reg = 0x1440 0x4; interrupt-names = fifo, vsync, lcd_sys; interrupts = 18 4, 18 5, 18 6; + samsung,sysreg = sysreg_system_controller; status = disabled; }; -- 1.9.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 10/14] drm/panel: add S6E3FA0 driver
This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/panel/Kconfig | 7 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 ++
3 files changed, 577 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E3FA0
+ tristate S6E3FA0 DSI command mode panel
+ depends on DRM DRM_PANEL
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..66058a7
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,569 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho yj44@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include drm/drmP.h
+#include drm/drm_mipi_dsi.h
+#include drm/drm_panel.h
+
+#include linux/gpio/consumer.h
+#include linux/regulator/consumer.h
+
+#include video/mipi_display.h
+#include video/of_videomode.h
+#include video/videomode.h
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER 0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT 0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL 0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM 0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1 0xf0
+#define MCS_GAMMA_UPDATE 0xf7
+#define MCS_KEY_LEV2 0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL 0x15
+
+struct s6e3fa0 {
+ struct device *dev;
+ struct drm_panelpanel;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc*reset_gpio;
+ struct gpio_desc*det_gpio;
+ struct gpio_desc*te_gpio;
+ struct videomodevm;
+
+ unsigned intpower_on_delay;
+ unsigned intreset_delay;
+ unsigned intinit_delay;
+ unsigned intwidth_mm;
+ unsigned intheight_mm;
+
+ unsigned char id;
+ unsigned char vddm;
+ unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+ {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+ {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+ {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+ {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+ {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+ {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+ {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+ {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+ {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+ {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+ {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+ {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a
[PATCH v4 03/14] ARM: dts: samsung-fimd: add LCD I80 interface specific properties
In case of using MIPI DSI based I80 interface panel, the relevant registers should be set. So this patch adds relevant DT bindings. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/video/samsung-fimd.txt | 28 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index 2dad41b..59ff61e 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -44,6 +44,34 @@ Optional Properties: - display-timings: timing settings for FIMD, as described in document [1]. Can be used in case timings cannot be provided otherwise or to override timings provided by the panel. +- samsung,sysreg: handle to syscon used to control the system registers +- i80-if-timings: timing configuration for lcd i80 interface support. + - cs-setup: clock cycles for the active period of address signal is enabled + until chip select is enabled. + If not specified, the default value(0) will be used. + - wr-setup: clock cycles for the active period of CS signal is enabled until + write signal is enabled. + If not specified, the default value(0) will be used. + - wr-active: clock cycles for the active period of CS is enabled. + If not specified, the default value(1) will be used. + - wr-hold: clock cycles for the active period of CS is disabled until write + signal is disabled. + If not specified, the default value(0) will be used. + + The parameters are defined as: + +VCLK(internal) __|¯¯|_|¯¯|_|¯¯|_|¯¯|_|¯¯ + ::::: +Address Output --:XXX::::XX + | cs-setup+1 |::: + |--|::: +Chip Select ¯¯¯|::|¯¯ + | wr-setup+1 || wr-hold+1 | + |--||--| +Write Enable||¯¯¯ +| wr-active+1| +|--| +Video Data X-- The device node can contain 'port' child nodes according to the bindings defined in [2]. The following are properties specific to those nodes: -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 05/14] drm/exynos: dsi: add TE handler to support LCD I80 interface
To support LCD I80 interface, the DSI host calls this handler
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index df2d23d..db760d8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1033,10 +1034,22 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static int exynos_dsi_host_te_handler(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (!(dsi-state DSIM_STATE_ENABLED))
+ return -EPERM;
+
+ return exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .te_handler = exynos_dsi_host_te_handler,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
--
1.7.9.5
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[PATCH v4 02/14] drm/exynos: use wait_event_timeout() for safety usage
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc-pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (mode DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc-pending_flip_queue,
- atomic_read(exynos_crtc-pending_flip) == 0);
+ if (!wait_event_timeout(exynos_crtc-pending_flip_queue,
+ !atomic_read(exynos_crtc-pending_flip),
+ HZ/20))
+ atomic_set(exynos_crtc-pending_flip, 0);
drm_vblank_off(crtc-dev, exynos_crtc-pipe);
}
@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(dev-event_lock);
drm_vblank_put(dev, exynos_crtc-pipe);
list_del(event-base.link);
+ atomic_set(exynos_crtc-pending_flip, 0);
spin_unlock_irq(dev-event_lock);
goto out;
--
1.7.9.5
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[PATCH v4 00/14] drm/exynos: support LCD I80 interface display
Hi, This series adds LCD I80 interface display support for Exynos DRM driver. The FIMD(display controller) specification describes it as LCD I80 interface and the DSI specification describes it as Command mode interface. This is based on exynos-drm-next branch. The previous patches, RFC: http://www.spinics.net/lists/dri-devel/msg58898.html V1: http://www.spinics.net/lists/dri-devel/msg59291.html V2: http://www.spinics.net/lists/dri-devel/msg59867.html V3: http://www.spinics.net/lists/dri-devel/msg60708.html Changelog v2: - Fixes typo and removes unnecessary error log (commented by Andrzej Hazda) - Adds missed pendlig_flip flag clear points (commented by Daniel Kurtz) Changelog v3: - Removes generic command mode and command mode display timing interface. - Moves I80 interface timings from panel DT to the FIMD(display controller) DT. Changelog v4: - Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because it was already updated by linux-samsung-soc (commented by Vivek Gautam) Patches 1 and 2 fix trivial bugs. Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface. The MIPI DSI command mode based panel generates Tearing Effect synchronization signal between MCU and FB to display video image, and FIMD should trigger to transfer video image at this signal. So the panel should receive the TE IRQ and call TE handler chains to notify it to the FIMD. Patches 7 and 8 implement to use Exynos5420 SoC DSI driver which is different from previous Exynos4 SoCs for some registers control. Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED 5.7 LCD drm panel driver. The ohters add DT property nodes to support MIPI DSI command mode. I welcome any comments. Thank you. Best regards YJ YoungJun Cho (14): drm/exynos: dsi: move the EoT packets configuration point drm/exynos: use wait_event_timeout() for safety usage ARM: dts: samsung-fimd: add LCD I80 interface specific properties drm/exynos: add TE handler to support LCD I80 interface drm/exynos: dsi: add TE handler to support LCD I80 interface drm/exynos: fimd: support LCD I80 interface ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings drm/exynos: dsi: add driver data to support Exynos5420 ARM: dts: s6e3fa0: add DT bindings drm/panel: add S6E3FA0 driver ARM: dts: exynos4: add system register property ARM: dts: exynos5: add system register property ARM: dts: exynos5420: add mipi-phy node ARM: dts: exynos5420: add dsi node .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++ .../devicetree/bindings/video/exynos_dsim.txt |4 +- .../devicetree/bindings/video/samsung-fimd.txt | 28 + arch/arm/boot/dts/exynos4.dtsi |1 + arch/arm/boot/dts/exynos5.dtsi |1 + arch/arm/boot/dts/exynos5420.dtsi | 20 + drivers/gpu/drm/exynos/Kconfig |1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 18 +- drivers/gpu/drm/exynos/exynos_drm_crtc.h |7 + drivers/gpu/drm/exynos/exynos_drm_drv.h|3 + drivers/gpu/drm/exynos/exynos_drm_dsi.c| 175 +- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 287 -- drivers/gpu/drm/panel/Kconfig |7 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-s6e3fa0.c | 568 include/drm/drm_mipi_dsi.h |8 + include/video/samsung_fimd.h |3 +- 17 files changed, 1107 insertions(+), 71 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 01/14] drm/exynos: dsi: move the EoT packets configuration point
This configuration could be used in MIPI DSI command mode also.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 6302aa6..df2d23d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -473,8 +473,6 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
if (!(dsi-mode_flags MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
- if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
- reg |= DSIM_EOT_DISABLE;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +489,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}
+ if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
+ reg |= DSIM_EOT_DISABLE;
+
switch (dsi-format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
--
1.7.9.5
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[PATCH v4 07/14] ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings
This patch adds relevant to exynos5420 compatible for exynos5420 SoC support. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/video/exynos_dsim.txt |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 33b5730..29bf3b2 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -1,7 +1,9 @@ Exynos MIPI DSI Master Required properties: - - compatible: samsung,exynos4210-mipi-dsi + - compatible: value should be one of the following + samsung,exynos4210-mipi-dsi /* for Exynos4 SoCs */ + samsung,exynos5420-mipi-dsi /* for Exynos5420 SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 09/14] ARM: dts: s6e3fa0: add DT bindings
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+ - compatible: samsung,s6e3fa0
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: core voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin
+ - det-gpios: a GPIO spec for the OLED detection pin
+ - te-gpios: a GPIO spec for the TE pin
+ - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ panel@0 {
+ compatible = samsung,s6e3fa0;
+ reg = 0;
+ vdd3-supply = vcclcd_reg;
+ vci-supply = vlcd_reg;
+ reset-gpios = gpy7 4 0;
+ det-gpios = gpg0 6 0;
+ te-gpios = gpd1 7 0;
+
+ display-timings {
+ timings0 {
+ clock-frequency = 0;
+ hactive = 1080;
+ vactive = 1920;
+ hfront-porch = 2;
+ hback-porch = 2;
+ hsync-len = 1;
+ vfront-porch = 1;
+ vback-porch = 4;
+ vsync-len = 1;
+ };
+ };
+ };
--
1.7.9.5
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[PATCH v4 08/14] drm/exynos: dsi: add driver data to support Exynos5420
The offset of register DSIM_PLLTMR_REG in Exynos5420 is
different from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit
in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 ++-
1 file changed, 135 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index db760d8..c348392 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include linux/clk.h
#include linux/irq.h
+#include linux/of_device.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
#include linux/component.h
@@ -55,9 +56,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) 0xf) 0)
@@ -201,6 +205,24 @@
#define DSIM_PLL_M(x) ((x) 4)
#define DSIM_PLL_S(x) ((x) 1)
+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) 0x1ff) 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -234,6 +256,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -263,11 +291,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = samsung,exynos4210-mipi-dsi,
+ .data = exynos4_dsi_driver_data },
+ { .compatible = samsung,exynos5420-mipi-dsi,
+ .data = exynos5_dsi_driver_data },
+ { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, pdev-dev);
+
+ return (struct exynos_dsi_driver_data *)of_id-data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(dsi-completed, msecs_to_jiffies(300)))
@@ -341,14 +397,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
{
- static const unsigned long freq_bands[] = {
- 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
- 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
- 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
- 770 * MHZ, 870 * MHZ, 950 * MHZ,
- };
+ struct exynos_dsi_driver_data *driver_data = dsi-driver_data;
unsigned long fin, fout;
- int timeout, band;
+ int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -369,18 +420,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
failed to find PLL PMS for requested frequency\n);
return
[PATCH v4 04/14] drm/exynos: add TE handler to support LCD I80 interface
To support LCD I80 interface, the panel should generates
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls this handler
chains to notify it to the display controller.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 11 +++
drivers/gpu/drm/exynos/exynos_drm_crtc.h |7 +++
drivers/gpu/drm/exynos/exynos_drm_drv.h |3 +++
include/drm/drm_mipi_dsi.h |8
4 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..504e023 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,14 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device
*drm_dev,
return -EPERM;
}
+
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+ struct exynos_drm_manager *manager = to_exynos_crtc(crtc)-manager;
+ int ret = 0;
+
+ if (manager-ops-te_handler)
+ ret = manager-ops-te_handler(manager);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..875d93d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc,
int zpos);
int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);
+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 36535f3..ab3a88d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -188,6 +188,8 @@ struct exynos_drm_display {
* @win_commit: apply hardware specific overlay data to registers.
* @win_enable: enable hardware specific overlay.
* @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
*/
struct exynos_drm_manager;
struct exynos_drm_manager_ops {
@@ -206,6 +208,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+ int (*te_handler)(struct exynos_drm_manager *mgr);
};
/*
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 7209df1..f6d4c85 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,13 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @te_handler: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal
+ * between MCU and FB to display video images.
+ * And the display controller should trigger to transfer video
+ * image at this signal.
+ * So the panel receives the TE IRQ, then calls this handler
+ * to notify it to the display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +64,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ int (*te_handler)(struct mipi_dsi_host *host);
};
/**
--
1.7.9.5
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[PATCH v4 06/14] drm/exynos: fimd: support LCD I80 interface
To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses lcd_sys as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one to
generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
flip request, and implements TE handler to call trigger function.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/Kconfig |1 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 287 +-
include/video/samsung_fimd.h |3 +-
3 files changed, 247 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool Exynos DRM FIMD
depends on DRM_EXYNOS !FB_S3C
select FB_MODE_HELPERS
+ select MFD_SYSCON
help
Choose this option if you want to use Exynos FIMD for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index bb45ab2..589017c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
#include linux/of_device.h
#include linux/pm_runtime.h
#include linux/component.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include video/of_display_timing.h
#include video/of_videomode.h
@@ -61,6 +63,24 @@
/* color key value register for hardware window 1 ~ 4. */
#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0 (0x2 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) 16)
+#define LCD_WR_SETUP(x)((x) 12)
+#define LCD_WR_ACTIVE(x) ((x) 8)
+#define LCD_WR_HOLD(x) ((x) 4)
+#define I80IFEN_ENABLE (1 0)
+
/* FIMD has totally five hardware windows. */
#define WINDOWS_NR 5
@@ -68,10 +88,14 @@
struct fimd_driver_data {
unsigned int timing_base;
+ unsigned int lcdblk_off;
+ unsigned int lcdblk_vt_shift;
+ unsigned int lcdblk_bypass_shift;
unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+ unsigned int has_vidoutcon:1;
};
static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {
static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+ .lcdblk_off = 0x210,
+ .lcdblk_vt_shift = 10,
+ .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
};
static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+ .lcdblk_off = 0x214,
+ .lcdblk_vt_shift = 24,
+ .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+ .has_vidoutcon = 1,
};
struct fimd_win_data {
@@ -112,15 +143,23 @@ struct fimd_context {
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem*regs;
+ struct regmap *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long irq_flags;
+ u32 vidcon0;
u32 vidcon1;
+ u32 vidout_con;
+ u32 i80ifcon;
+ booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
+ atomic_twin_updated;
+ atomic_ttriggering;
+ spinlock_t win_updated_lock;
struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +282,14 @@ static u32
[PATCH v4 10/14] drm/panel: add S6E3FA0 driver
This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/panel/Kconfig |7 +
drivers/gpu/drm/panel/Makefile|1 +
drivers/gpu/drm/panel/panel-s6e3fa0.c | 568 +
3 files changed, 576 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E3FA0
+ tristate S6E3FA0 DSI command mode panel
+ depends on DRM DRM_PANEL
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..5373ba7
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,568 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho yj44@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include drm/drmP.h
+#include drm/drm_mipi_dsi.h
+#include drm/drm_panel.h
+
+#include linux/gpio/consumer.h
+#include linux/regulator/consumer.h
+
+#include video/mipi_display.h
+#include video/of_videomode.h
+#include video/videomode.h
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER 0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT 0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL 0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM 0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1 0xf0
+#define MCS_PANEL_UPDATE 0xf7
+#define MCS_KEY_LEV2 0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL 0x15
+
+struct s6e3fa0 {
+ struct device *dev;
+ struct drm_panelpanel;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc*reset_gpio;
+ struct gpio_desc*det_gpio;
+ struct gpio_desc*te_gpio;
+ struct videomodevm;
+
+ unsigned intpower_on_delay;
+ unsigned intreset_delay;
+ unsigned intinit_delay;
+ unsigned intwidth_mm;
+ unsigned intheight_mm;
+
+ unsigned char id;
+ unsigned char vddm;
+ unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+ {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+ {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+ {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+ {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+ {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+ {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+ {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+ {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+ {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+ {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+ {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+ {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a
[PATCH v4 11/14] ARM: dts: exynos4: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos4.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 2f8bcd0..abfcbe2 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -534,6 +534,7 @@ clocks = clock CLK_SCLK_FIMD0, clock CLK_FIMD0; clock-names = sclk_fimd, fimd; samsung,power-domain = pd_lcd0; + samsung,sysreg = sys_reg; status = disabled; }; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 12/14] ARM: dts: exynos5: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos5.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 79d0608..fdead12 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -87,6 +87,7 @@ reg = 0x1440 0x4; interrupt-names = fifo, vsync, lcd_sys; interrupts = 18 4, 18 5, 18 6; + samsung,sysreg = sysreg_system_controller; status = disabled; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 13/14] ARM: dts: exynos5420: add mipi-phy node
This patch adds mipi-phy node for MIPI DSI device.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66..6fde5fd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -472,6 +472,12 @@
phy-names = dp;
};
+ mipi_phy: video-phy@10040714 {
+ compatible = samsung,s5pv210-mipi-video-phy;
+ reg = 0x10040714 12;
+ #phy-cells = 1;
+ };
+
fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
--
1.7.9.5
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[PATCH v4 14/14] ARM: dts: exynos5420: add dsi node
This patch adds common part of dsi node.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6fde5fd..43b6852 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -478,6 +478,20 @@
#phy-cells = 1;
};
+ dsi@1450 {
+ compatible = samsung,exynos5420-mipi-dsi;
+ reg = 0x1450 0x1;
+ interrupts = 0 82 0;
+ samsung,power-domain = disp_pd;
+ phys = mipi_phy 1;
+ phy-names = dsim;
+ clocks = clock CLK_DSIM1, clock CLK_SCLK_MIPI1;
+ clock-names = bus_clk, pll_clk;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
--
1.7.9.5
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Re: [PATCH v3 13/15] ARM: dts: exynos5: add system register support
Hi Vivek,
On 06/04/2014 08:50 PM, Vivek Gautam wrote:
On Mon, Jun 2, 2014 at 10:52 AM, YoungJun Cho yj44@samsung.com wrote:
This patch adds sysreg device node, and sysreg property
to fimd device node which is required to use I80 interface.
Same here. The system register nodes have been added to exynos5250 and
exynos5420 by the patch:
dfbbdbf ARM: dts: Add sysreg sytem controller node to exynos5250 and exynos5420
May be, you may want to move those two nodes to this common file (exynos5.dtsi).
Thank you for reporting.
I didn't check linux-samsung-soc.
The exynos5410, 5420 and 5422 use system register with base address
0x1005.
But exynos5260 and 5430 are different.
And I can't check exynos5250.
So with this condition, it is reasonable to remove these sysreg relevant
patches.
Thank you.
Best regards YJ
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..95ee496 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -81,12 +81,18 @@
status = disabled;
};
+ sys_reg: syscon@1005 {
+ compatible = samsung,exynos5-sysreg, syscon;
+ reg = 0x1005 0x500;
+ };
+
fimd@1440 {
compatible = samsung,exynos5250-fimd;
interrupt-parent = combiner;
reg = 0x1440 0x4;
interrupt-names = fifo, vsync, lcd_sys;
interrupts = 18 4, 18 5, 18 6;
+ samsung,sysreg = sys_reg;
status = disabled;
};
--
1.7.9.5
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Re: [PATCH] drm/exynos: remove hardware overlays disable from fimd probe
Hi Rahul,
On 06/02/2014 06:42 PM, Rahul Sharma wrote:
On 2 June 2014 14:41, Andrzej Hajda a.ha...@samsung.com wrote:
Hi Rahul,
On 05/28/2014 08:11 AM, Rahul Sharma wrote:
System hangs when FIMD registers are accessed to disable
hardware overlays. This is because of the clocks which are
not enabled before register access.
'Hardware overlay disable' is cleaned from the FIMD probe.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
This patch causes regression on some exynos4210-universal_c210 devices,
everything works expect colors are incorrect - it seems blue component
is very dark, almost black.
Oh Sorry for that. I did not see any problem on 5250/5420/5800. I do not
have setup for 4210. Better we should revert this patch.
Would you please help me by verifying the following patch on 4210? This
is an alternate solution to the same problem.
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31426.html
In my humble opinion, the patch is required to modify like below:
+ ret = pm_runtime_get_sync(ctx-dev);
+ if (ret 0) {
When the bootloader enabled FIMD to show logo(boot image) or animation,
this function pm_runtime_get_sync() in fimd_bind() would return 1.
Thank you.
Best regards YJ
Thanks Andrej, for bringing it to notice.
Regards,
Rahul Sharma
Regards
Andrzej
---
Based on exynos-drm-next branch.
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index bd30d0c..2ec634f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -703,19 +703,6 @@ static void fimd_win_disable(struct exynos_drm_manager
*mgr, int zpos)
win_data-enabled = false;
}
-static void fimd_clear_win(struct fimd_context *ctx, int win)
-{
- writel(0, ctx-regs + WINCON(win));
- writel(0, ctx-regs + VIDOSD_A(win));
- writel(0, ctx-regs + VIDOSD_B(win));
- writel(0, ctx-regs + VIDOSD_C(win));
-
- if (win == 1 || win == 2)
- writel(0, ctx-regs + VIDOSD_D(win));
-
- fimd_shadow_protect_win(ctx, win, false);
-}
-
static void fimd_window_suspend(struct exynos_drm_manager *mgr)
{
struct fimd_context *ctx = mgr-ctx;
@@ -898,16 +885,12 @@ static int fimd_bind(struct device *dev, struct device
*master, void *data)
{
struct fimd_context *ctx = fimd_manager.ctx;
struct drm_device *drm_dev = data;
- int win;
fimd_mgr_initialize(fimd_manager, drm_dev);
exynos_drm_crtc_create(fimd_manager);
if (ctx-display)
exynos_drm_create_enc_conn(drm_dev, ctx-display);
- for (win = 0; win WINDOWS_NR; win++)
- fimd_clear_win(ctx, win);
-
return 0;
}
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[PATCH v3 03/15] ARM: dts: sysreg: add exynos5 compatible to DT bindings
This patch adds relevant to exynos5 compatible for exynos5 SoCs. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/arm/samsung/sysreg.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt index 0ab3251..fd71581 100644 --- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt +++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt @@ -3,6 +3,7 @@ SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) Properties: - compatible : should contain samsung,chip name-sysreg, syscon; For Exynos4 SoC series it should be samsung,exynos4-sysreg, syscon; + For Exynos5 SoC series it should be samsung,exynos5-sysreg, syscon; - reg : offset and length of the register set. Example: -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 08/15] ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings
This patch adds relevant to exynos5420 compatible for exynos5420 SoC support. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/video/exynos_dsim.txt |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 33b5730..29bf3b2 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -1,7 +1,9 @@ Exynos MIPI DSI Master Required properties: - - compatible: samsung,exynos4210-mipi-dsi + - compatible: value should be one of the following + samsung,exynos4210-mipi-dsi /* for Exynos4 SoCs */ + samsung,exynos5420-mipi-dsi /* for Exynos5420 SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 01/15] drm/exynos: dsi: move the EoT packets configuration point
This configuration could be used in MIPI DSI command mode also.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 84661fe..0a4e3ce 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -473,8 +473,6 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
if (!(dsi-mode_flags MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
- if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
- reg |= DSIM_EOT_DISABLE;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +489,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}
+ if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
+ reg |= DSIM_EOT_DISABLE;
+
switch (dsi-format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
--
1.7.9.5
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[PATCH v3 09/15] drm/exynos: dsi: add driver data to support Exynos5420
The offset of register DSIM_PLLTMR_REG in Exynos5420 is
different from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit
in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 ++-
1 file changed, 135 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 783d7a5..35d636b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include linux/clk.h
#include linux/irq.h
+#include linux/of_device.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
#include linux/component.h
@@ -55,9 +56,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) 0xf) 0)
@@ -201,6 +205,24 @@
#define DSIM_PLL_M(x) ((x) 4)
#define DSIM_PLL_S(x) ((x) 1)
+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) 0x1ff) 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -234,6 +256,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -263,11 +291,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = samsung,exynos4210-mipi-dsi,
+ .data = exynos4_dsi_driver_data },
+ { .compatible = samsung,exynos5420-mipi-dsi,
+ .data = exynos5_dsi_driver_data },
+ { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, pdev-dev);
+
+ return (struct exynos_dsi_driver_data *)of_id-data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(dsi-completed, msecs_to_jiffies(300)))
@@ -341,14 +397,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
{
- static const unsigned long freq_bands[] = {
- 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
- 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
- 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
- 770 * MHZ, 870 * MHZ, 950 * MHZ,
- };
+ struct exynos_dsi_driver_data *driver_data = dsi-driver_data;
unsigned long fin, fout;
- int timeout, band;
+ int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -369,18 +420,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
failed to find PLL PMS for requested frequency\n);
return
[PATCH v3 00/15] drm/exynos: support LCD I80 interface display
Hi, This series adds LCD I80 interface display support for Exynos DRM driver. The FIMD(display controller) specification describes it as LCD I80 interface and the DSI specification describes it as Command mode interface. This is based on exynos-drm-next branch. The previous patches, RFC: http://www.spinics.net/lists/dri-devel/msg58898.html V1: http://www.spinics.net/lists/dri-devel/msg59291.html V2: http://www.spinics.net/lists/dri-devel/msg59867.html Changelog v2: - Fixes typo and removes unnecessary error log (commented by Andrzej Hazda) - Adds missed pendlig_flip flag clear points (commented by Daniel Kurtz) Changelog v3: - Removes generic command mode and command mode display timing interface. - Moves I80 interface timings from panel DT to the FIMD(display controller) DT. Patches 1 and 2 fix trivial bugs. Patches 3, 4, 5, 6 and 7 implement FIMD(display controller) I80 interface. The MIPI DSI command mode based panel generates Tearing Effect synchronization signal between MCU and FB to display video image, and FIMD should trigger to transfer video image at this signal. So the panel should receive the TE IRQ and call TE handler chains to notify it to the FIMD. Patches 8 and 9 implement to use Exynos5420 SoC DSI driver which is different from previous Exynos4 SoCs for some registers control. Patches 10 and 11 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED 5.7 LCD drm panel driver. The ohters add DT property nodes to support MIPI DSI command mode. I welcome any comments. Thank you. Best regards YJ YoungJun Cho (15): drm/exynos: dsi: move the EoT packets configuration point drm/exynos: use wait_event_timeout() for safety usage ARM: dts: sysreg: add exynos5 compatible to DT bindings ARM: dts: samsung-fimd: add LCD I80 interface specific properties drm/exynos: add TE handler to support LCD I80 interface drm/exynos: dsi: add TE handler to support LCD I80 interface drm/exynos: fimd: support LCD I80 interface ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings drm/exynos: dsi: add driver data to support Exynos5420 ARM: dts: s6e3fa0: add DT bindings drm/panel: add S6E3FA0 driver ARM: dts: exynos4: add system register node ARM: dts: exynos5: add system register support ARM: dts: exynos5420: add mipi-phy node ARM: dts: exynos5420: add dsi node .../devicetree/bindings/arm/samsung/sysreg.txt |1 + .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++ .../devicetree/bindings/video/exynos_dsim.txt |4 +- .../devicetree/bindings/video/samsung-fimd.txt | 28 + arch/arm/boot/dts/exynos4.dtsi |1 + arch/arm/boot/dts/exynos5.dtsi |6 + arch/arm/boot/dts/exynos5420.dtsi | 20 + drivers/gpu/drm/exynos/Kconfig |1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 18 +- drivers/gpu/drm/exynos/exynos_drm_crtc.h |7 + drivers/gpu/drm/exynos/exynos_drm_drv.h|3 + drivers/gpu/drm/exynos/exynos_drm_dsi.c| 175 +- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 287 -- drivers/gpu/drm/panel/Kconfig |7 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-s6e3fa0.c | 568 include/drm/drm_mipi_dsi.h |8 + include/video/samsung_fimd.h |3 +- 18 files changed, 1113 insertions(+), 71 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 02/15] drm/exynos: use wait_event_timeout() for safety usage
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc-pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Andrzej Hajda a.ha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (mode DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc-pending_flip_queue,
- atomic_read(exynos_crtc-pending_flip) == 0);
+ if (!wait_event_timeout(exynos_crtc-pending_flip_queue,
+ !atomic_read(exynos_crtc-pending_flip),
+ HZ/20))
+ atomic_set(exynos_crtc-pending_flip, 0);
drm_vblank_off(crtc-dev, exynos_crtc-pipe);
}
@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(dev-event_lock);
drm_vblank_put(dev, exynos_crtc-pipe);
list_del(event-base.link);
+ atomic_set(exynos_crtc-pending_flip, 0);
spin_unlock_irq(dev-event_lock);
goto out;
--
1.7.9.5
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[PATCH v3 13/15] ARM: dts: exynos5: add system register support
This patch adds sysreg device node, and sysreg property
to fimd device node which is required to use I80 interface.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..95ee496 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -81,12 +81,18 @@
status = disabled;
};
+ sys_reg: syscon@1005 {
+ compatible = samsung,exynos5-sysreg, syscon;
+ reg = 0x1005 0x500;
+ };
+
fimd@1440 {
compatible = samsung,exynos5250-fimd;
interrupt-parent = combiner;
reg = 0x1440 0x4;
interrupt-names = fifo, vsync, lcd_sys;
interrupts = 18 4, 18 5, 18 6;
+ samsung,sysreg = sys_reg;
status = disabled;
};
--
1.7.9.5
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[PATCH v3 12/15] ARM: dts: exynos4: add system register node
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos4.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 2f8bcd0..abfcbe2 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -534,6 +534,7 @@ clocks = clock CLK_SCLK_FIMD0, clock CLK_FIMD0; clock-names = sclk_fimd, fimd; samsung,power-domain = pd_lcd0; + samsung,sysreg = sys_reg; status = disabled; }; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 07/15] drm/exynos: fimd: support LCD I80 interface
To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses lcd_sys as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one to
generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
flip request, and implements TE handler to call trigger function.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/Kconfig |1 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 287 +-
include/video/samsung_fimd.h |3 +-
3 files changed, 247 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool Exynos DRM FIMD
depends on DRM_EXYNOS !FB_S3C
select FB_MODE_HELPERS
+ select MFD_SYSCON
help
Choose this option if you want to use Exynos FIMD for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 2ec634f..f317fca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
#include linux/of_device.h
#include linux/pm_runtime.h
#include linux/component.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include video/of_display_timing.h
#include video/of_videomode.h
@@ -61,6 +63,24 @@
/* color key value register for hardware window 1 ~ 4. */
#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0 (0x2 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) 16)
+#define LCD_WR_SETUP(x)((x) 12)
+#define LCD_WR_ACTIVE(x) ((x) 8)
+#define LCD_WR_HOLD(x) ((x) 4)
+#define I80IFEN_ENABLE (1 0)
+
/* FIMD has totally five hardware windows. */
#define WINDOWS_NR 5
@@ -68,10 +88,14 @@
struct fimd_driver_data {
unsigned int timing_base;
+ unsigned int lcdblk_off;
+ unsigned int lcdblk_vt_shift;
+ unsigned int lcdblk_bypass_shift;
unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+ unsigned int has_vidoutcon:1;
};
static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {
static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+ .lcdblk_off = 0x210,
+ .lcdblk_vt_shift = 10,
+ .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
};
static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+ .lcdblk_off = 0x214,
+ .lcdblk_vt_shift = 24,
+ .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+ .has_vidoutcon = 1,
};
struct fimd_win_data {
@@ -112,15 +143,23 @@ struct fimd_context {
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem*regs;
+ struct regmap *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long irq_flags;
+ u32 vidcon0;
u32 vidcon1;
+ u32 vidout_con;
+ u32 i80ifcon;
+ booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
+ atomic_twin_updated;
+ atomic_ttriggering;
+ spinlock_t win_updated_lock;
struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +282,14 @@ static u32
[PATCH v3 04/15] ARM: dts: samsung-fimd: add LCD I80 interface specific properties
In case of using MIPI DSI based I80 interface panel, the relevant registers should be set. So this patch adds relevant DT bindings. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/video/samsung-fimd.txt | 28 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index 2dad41b..59ff61e 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -44,6 +44,34 @@ Optional Properties: - display-timings: timing settings for FIMD, as described in document [1]. Can be used in case timings cannot be provided otherwise or to override timings provided by the panel. +- samsung,sysreg: handle to syscon used to control the system registers +- i80-if-timings: timing configuration for lcd i80 interface support. + - cs-setup: clock cycles for the active period of address signal is enabled + until chip select is enabled. + If not specified, the default value(0) will be used. + - wr-setup: clock cycles for the active period of CS signal is enabled until + write signal is enabled. + If not specified, the default value(0) will be used. + - wr-active: clock cycles for the active period of CS is enabled. + If not specified, the default value(1) will be used. + - wr-hold: clock cycles for the active period of CS is disabled until write + signal is disabled. + If not specified, the default value(0) will be used. + + The parameters are defined as: + +VCLK(internal) __|¯¯|_|¯¯|_|¯¯|_|¯¯|_|¯¯ + ::::: +Address Output --:XXX::::XX + | cs-setup+1 |::: + |--|::: +Chip Select ¯¯¯|::|¯¯ + | wr-setup+1 || wr-hold+1 | + |--||--| +Write Enable||¯¯¯ +| wr-active+1| +|--| +Video Data X-- The device node can contain 'port' child nodes according to the bindings defined in [2]. The following are properties specific to those nodes: -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 05/15] drm/exynos: add TE handler to support LCD I80 interface
To support LCD I80 interface, the panel should generates
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls this handler
chains to notify it to the display controller.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 11 +++
drivers/gpu/drm/exynos/exynos_drm_crtc.h |7 +++
drivers/gpu/drm/exynos/exynos_drm_drv.h |3 +++
include/drm/drm_mipi_dsi.h |8
4 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..504e023 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,14 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device
*drm_dev,
return -EPERM;
}
+
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+ struct exynos_drm_manager *manager = to_exynos_crtc(crtc)-manager;
+ int ret = 0;
+
+ if (manager-ops-te_handler)
+ ret = manager-ops-te_handler(manager);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..875d93d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc,
int zpos);
int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);
+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index e82e620..54b08d7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -181,6 +181,8 @@ struct exynos_drm_display {
* @win_commit: apply hardware specific overlay data to registers.
* @win_enable: enable hardware specific overlay.
* @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
*/
struct exynos_drm_manager;
struct exynos_drm_manager_ops {
@@ -199,6 +201,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+ int (*te_handler)(struct exynos_drm_manager *mgr);
};
/*
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 7209df1..f6d4c85 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,13 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @te_handler: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal
+ * between MCU and FB to display video images.
+ * And the display controller should trigger to transfer video
+ * image at this signal.
+ * So the panel receives the TE IRQ, then calls this handler
+ * to notify it to the display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +64,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ int (*te_handler)(struct mipi_dsi_host *host);
};
/**
--
1.7.9.5
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[PATCH v3 15/15] ARM: dts: exynos5420: add dsi node
This patch adds common part of dsi node.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6fde5fd..43b6852 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -478,6 +478,20 @@
#phy-cells = 1;
};
+ dsi@1450 {
+ compatible = samsung,exynos5420-mipi-dsi;
+ reg = 0x1450 0x1;
+ interrupts = 0 82 0;
+ samsung,power-domain = disp_pd;
+ phys = mipi_phy 1;
+ phy-names = dsim;
+ clocks = clock CLK_DSIM1, clock CLK_SCLK_MIPI1;
+ clock-names = bus_clk, pll_clk;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
--
1.7.9.5
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[PATCH v3 14/15] ARM: dts: exynos5420: add mipi-phy node
This patch adds mipi-phy node for MIPI DSI device.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66..6fde5fd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -472,6 +472,12 @@
phy-names = dp;
};
+ mipi_phy: video-phy@10040714 {
+ compatible = samsung,s5pv210-mipi-video-phy;
+ reg = 0x10040714 12;
+ #phy-cells = 1;
+ };
+
fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
--
1.7.9.5
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[PATCH v3 11/15] drm/panel: add S6E3FA0 driver
This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/panel/Kconfig |7 +
drivers/gpu/drm/panel/Makefile|1 +
drivers/gpu/drm/panel/panel-s6e3fa0.c | 568 +
3 files changed, 576 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E3FA0
+ tristate S6E3FA0 DSI command mode panel
+ depends on DRM DRM_PANEL
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..5373ba7
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,568 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho yj44@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include drm/drmP.h
+#include drm/drm_mipi_dsi.h
+#include drm/drm_panel.h
+
+#include linux/gpio/consumer.h
+#include linux/regulator/consumer.h
+
+#include video/mipi_display.h
+#include video/of_videomode.h
+#include video/videomode.h
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER 0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT 0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL 0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM 0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1 0xf0
+#define MCS_PANEL_UPDATE 0xf7
+#define MCS_KEY_LEV2 0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL 0x15
+
+struct s6e3fa0 {
+ struct device *dev;
+ struct drm_panelpanel;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc*reset_gpio;
+ struct gpio_desc*det_gpio;
+ struct gpio_desc*te_gpio;
+ struct videomodevm;
+
+ unsigned intpower_on_delay;
+ unsigned intreset_delay;
+ unsigned intinit_delay;
+ unsigned intwidth_mm;
+ unsigned intheight_mm;
+
+ unsigned char id;
+ unsigned char vddm;
+ unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+ {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+ {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+ {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+ {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+ {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+ {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+ {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+ {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+ {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+ {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+ {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+ {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a
[PATCH v3 10/15] ARM: dts: s6e3fa0: add DT bindings
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+ - compatible: samsung,s6e3fa0
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: core voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin
+ - det-gpios: a GPIO spec for the OLED detection pin
+ - te-gpios: a GPIO spec for the TE pin
+ - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ panel@0 {
+ compatible = samsung,s6e3fa0;
+ reg = 0;
+ vdd3-supply = vcclcd_reg;
+ vci-supply = vlcd_reg;
+ reset-gpios = gpy7 4 0;
+ det-gpios = gpg0 6 0;
+ te-gpios = gpd1 7 0;
+
+ display-timings {
+ timings0 {
+ clock-frequency = 0;
+ hactive = 1080;
+ vactive = 1920;
+ hfront-porch = 2;
+ hback-porch = 2;
+ hsync-len = 1;
+ vfront-porch = 1;
+ vback-porch = 4;
+ vsync-len = 1;
+ };
+ };
+ };
--
1.7.9.5
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Re: [PATCH v2 13/18] ARM: dts: s6e3fa0: add DT bindings
Hi ALL, On 05/28/2014 03:44 PM, Andrzej Hajda wrote: On 05/28/2014 06:50 AM, Inki Dae wrote: On 2014년 05월 28일 05:21, Thierry Reding wrote: On Tue, May 27, 2014 at 11:24:49PM +0900, Inki Dae wrote: 2014-05-27 16:53 GMT+09:00 Thierry Reding thierry.red...@gmail.com: On Tue, May 27, 2014 at 08:28:52AM +0200, Andrzej Hajda wrote: Hi Thierry, On 05/26/2014 03:41 PM, Thierry Reding wrote: On Wed, May 21, 2014 at 01:43:05PM +0900, YoungJun Cho wrote: This patch adds DT bindings for s6e3fa0 panel. The bindings describes panel resources, display timings and cpu mode timings. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 45 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt You're totally confusing me here. Half of this patch series is about adding i80 support to Exynos FIMD, and then you go and add what is apparently a DSI peripheral driver here that's supposed to be used by this new i80 support. Nothing I've been able to dig up indicates that i80 or DSI are in anyway related. FIMD can produce parallel RGB output or command mode in i80 style output via parallel lines. DSIM can accept parallel RGB stream in this case it produces MIPI DSI video mode signal or it can accept i80 and in this case it translates it to MIPI DSI command mode. Then the command mode timings aren't a property of the panel at all. Then the video mode timings aren't also a property of the panel. Which interface mipi and display controller should use would be decided by lcd panel type: display controller can use i80 interface based lcd panel, and also mipi controller can use i80 interface based lcd panel. In here, the only difference is that lcd panel receives packets, which includes video data or command data, packed with mipi protocol via lane lines or receives video data or command data via parallel lines. And the below is LCD types, RGB interface panel. i80 interface panel. MIPI based RGB interface panel. MIPI based i80 interface panel. RGB interface also is called video mode, and i80 interface also is called cpu mode. In case of omap SoC, it is also called Smart panel. i80 interface is just one of LCD types. So I think this interface timings should be handled by frameworks related to mode in same way as RGB interface. Some clarification about names. I am not an expert in command/cpu mode interface, so feel free to correct me. Those different terms were quite confusing for me so after some digging (for example here [1]) I have found/ensured there is a following relation between different names: MIPI DPI - RGB interface MIPI DBI type A - CPU mode m68 style MIPI DBI type B - CPU mode i80 style MIPI DBI type C - SPI, maybe also other serial interfaces (?) MIPI DSI - based on D-PHY-s serial protocol which can work in video or command mode. To add more confusion CPU mode is also named MPU mode or sys mode. To avoid confusion in the discussion I propose use i80 only to describe DBI type B interface, and DSI command mode, DSI video mode to describe DSI modes. [1]: http://www.allshore.com/pdf/DA8620.pdf LCD is a display technology, it has nothing to do with the interface. My point is that from Andrzej's description, and in fact from this patch series in general, the S6E3FA0 panel is a DSI panel. Associating timings that are i80 specific to it is therefore wrong. Consider for instance what would happen if somebody were to use the same panel on some other device (connected to a DSI controller). If you specify i80 timings for the panel then the new device won't know what to do with them because it expects DSI-related timings. Let me try to summarize the above to make sure we're all on the same page: - FIMD is a display controller that can be configured to either send RGB data or i80 data - DSIM takes either RGB as input and outputs DSI (video mode) or i80 as input and outputs DSI (command mode) In both cases the panel is connected to DSIM and it takes DSI as input, because it is a DSI panel (it doesn't understand RGB or i80). The panel needs to describe the properties of the DSI interface so that DSIM can be configured appropriately. DSIM in turn works as a bridge or encoder that converts RGB or i80 to DSI (video or command mode). So it makes no sense to describe the i80 timings for the panel because it has nothing to do with i80. Instead the DSIM is the hardware that needs to specify the i80 timings, so that FIMD can be configured to generate the timings that DSIM needs. CPU interface MIPI lane FIMD --- DSIM - LCD Panel Hmm... reasonable. So your point is that command mode timing should be placed in fimd device node, not panel device node
Re: [PATCH v2 10/18] drm/exynos: fimd: support I80 interface
Hi Daniel, On 05/26/2014 06:00 PM, Daniel Kurtz wrote: Hi YoungJun, I am not famiilar with i80. Reading through this patch, it looks like it works something like below for a page flip... - page_flip ioctl exynos_drm_crtc_page_flip() exynos_drm_crtc_mode_set_commit() exynos_plane_mode_set() exynos_drm_crtc_commit() exynos_plane_commit() exynos_drm_crtc_plane_commit() ops-win_commit() = fimd_win_commit() update BASE (scanout) register atomic_set(ctx-win_updated, 1); ... at the next TE event ... fimd_te_handler() atomic_set(ctx-win_updated, 0); fimd_trigger(ctx-dev); atomic_set(ctx-triggering, 1); VIDINTCON0 |= VIDINTCON0_INT_ENABLE; TRIGCON |= TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE ... start an i80 transaction to transfer frame data from BASE to the panel ... ... write complete signalled by ... - FIMD interrupt: source = VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON (which one?) VIDINTCON0_INT_SYSMAINCON is for main LCD interrupt. So both are required. fimd_irq_handler() atomic_set(ctx-triggering, 0); drm_handle_vblank(ctx-drm_dev, ctx-pipe); exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe); Some questions/points: (1) does the i80 done interrupt mean that the panel is now displaying the new frame? Or just that the new frame is pending in a panel-side scanout buffer? Is there a separate interrupt for (a) i80 The 'i80 done' interrupt means that display controller(FIMD) completes sending the last line of screen(framebuffer) to DSI master. transfer complete, and (b) new frame now on main display? The TE signal indicates that the panel completes dispatching gram. So like this: [ fimd ] : fimd_trigger() = frame done irq [ panel ] : te signal = show gram img (2) from the DPMS off patch, you mentioned that the panel sometimes has an issue. Do you mean that sometimes when you trigger the i80 transaction, there is no corresponding i80ifdone / sysmaincon No, I meant that fimd could miss TE signal if panel was reset / power off before generating it. interrupt? If so, then I think you want to start a timer in fimd_trigger(), that, if it expires before an I80IFDONE irq, will call exynos_drm_crtc_finish_pageflip(), rather than hiding handling this condition in dpms off of the exynos_drm_crtc.c layer. As you know that even though display controller missed TE signal and didn't trigger, the panel kept previous screen by self-refresh. After the panel recovers well and display controller sets next fb, then the panel would show it well without problem except current fb overwritten issue. But the dpms off case before the panel recovers well, there is no way to resolving pending event. Thank you. Best regards YJ Thanks, -djk On Wed, May 21, 2014 at 12:43 PM, YoungJun Cho yj44@samsung.com wrote: To support MIPI DSI command mode interface, FIMD should do followings: - Sets LCD block configuration for I80 interface. - Uses lcd_sys as an IRQ resource and sets relevant IRQ configuration. - Implements trigger feature which transfers image date if there is page flip request, and implements TE handler to call trigger function. - Sets command mode timings configuration. - Sets ideal(pixel) clock is 2 times faster than the original one to generate frame done IRQ prior to the next TE signal. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/gpu/drm/exynos/Kconfig |1 + drivers/gpu/drm/exynos/exynos_drm_fimd.c | 277 +- include/video/samsung_fimd.h |3 +- 3 files changed, 237 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index 5bf5bca..f4d34f0 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD bool Exynos DRM FIMD depends on DRM_EXYNOS !FB_S3C !ARCH_MULTIPLATFORM select FB_MODE_HELPERS + select MFD_SYSCON help Choose this option if you want to use Exynos FIMD for DRM. diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 173ee97..9d585f9 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -20,11 +20,14 @@ #include linux/of_device.h #include linux/pm_runtime.h #include linux/component.h +#include linux/mfd/syscon.h +#include linux/regmap.h #include video/of_display_timing.h #include video/of_videomode.h #include video/samsung_fimd.h #include drm/exynos_drm.h +#include drm/drm_panel.h #include exynos_drm_drv.h #include exynos_drm_fbdev.h @@ -60,6 +63,24 @@ /* color key value register for hardware window 1 ~ 4. */ #define WKEYCON1_BASE(x
Re: [PATCH v2 02/18] drm/exynos: use wait_event_timeout() for safety usage
Hi Daniel
On 05/21/2014 03:01 PM, Daniel Kurtz wrote:
On Wed, May 21, 2014 at 12:42 PM, YoungJun Cho yj44@samsung.com wrote:
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc-pending_flip in exynos_drm_crtc_page_flip() when
exynos_drm_crtc_mode_set_commit() is failed.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (mode DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc-pending_flip_queue,
- atomic_read(exynos_crtc-pending_flip) == 0);
+ if (!wait_event_timeout(exynos_crtc-pending_flip_queue,
+ !atomic_read(exynos_crtc-pending_flip),
+ HZ/20))
+ atomic_set(exynos_crtc-pending_flip, 0);
I meant that changing this to wait_event_timeout() seems to be masking
the original problem, that pending_flip wasn't being cleared.
Yes, I agree.
The original purpose of this patch is to avoid lock-up during modetest
(with test_vsync) with command mode panel.
In MIPI DSI command mode interface, the display controller can not
generate VSYNC signal and uses TE signal instead which is generated by
panel.
If there is an abnormal power off or reset condition, it is possible
that the display controller misses the TE signal and it makes lock-up.
So I needed this patch.
Now that you are now clearing pending_flip in the error path, you
don't need the timeout, right?
There might be my missing point. Would you explain more detail?
Thank you.
Best regards YJ
-Dan
drm_vblank_off(crtc-dev, exynos_crtc-pipe);
}
@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(dev-event_lock);
drm_vblank_put(dev, exynos_crtc-pipe);
list_del(event-base.link);
+ atomic_set(exynos_crtc-pending_flip, 0);
spin_unlock_irq(dev-event_lock);
goto out;
--
1.7.9.5
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Re: [PATCH v2 02/18] drm/exynos: use wait_event_timeout() for safety usage
Hi Daniel,
On 05/21/2014 03:45 PM, Daniel Kurtz wrote:
On Wed, May 21, 2014 at 2:28 PM, YoungJun Cho yj44@samsung.com wrote:
Hi Daniel
On 05/21/2014 03:01 PM, Daniel Kurtz wrote:
On Wed, May 21, 2014 at 12:42 PM, YoungJun Cho yj44@samsung.com
wrote:
There could be the case that the page flip operation isn't finished
correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip
completion
infinitely.
And clears exynos_crtc-pending_flip in exynos_drm_crtc_page_flip() when
exynos_drm_crtc_mode_set_commit() is failed.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc
*crtc, int mode)
if (mode DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc-pending_flip_queue,
- atomic_read(exynos_crtc-pending_flip)
== 0);
+ if (!wait_event_timeout(exynos_crtc-pending_flip_queue,
+ !atomic_read(exynos_crtc-pending_flip),
+ HZ/20))
+ atomic_set(exynos_crtc-pending_flip, 0);
I meant that changing this to wait_event_timeout() seems to be masking
the original problem, that pending_flip wasn't being cleared.
Yes, I agree.
The original purpose of this patch is to avoid lock-up during modetest (with
test_vsync) with command mode panel.
In MIPI DSI command mode interface, the display controller can not generate
VSYNC signal and uses TE signal instead which is generated by panel.
If there is an abnormal power off or reset condition, it is possible that
At first, I omitted the keyword panel at previous reply.
The abnormal power off or reset condition could be happened in panel
which generates TE signal.
the display controller misses the TE signal and it makes lock-up.
So I needed this patch.
If flips are not completing on MIPI DSI, may I recommend that you
start a timer when scheduling such a flip in the MIPI DSI driver that
will expire after a timeout. In that timer's expiration handler, you
The MIPI DSI doesn't take care page flip operation at all.
And the exynos_drm_crtc_finish_page_flip() is called only by interrupt
handler of display controllers.
So there is no suitable place to set time-out for this.
can then go through the normal process of completing a flip. This
would make the timeout transparent to the generic exynos_drm_crtc
layer, which can then do its normal flip complete processing: send
pending vblank events, put vblank, clear pending_flip, etc.
Does that make sense?
Is it possible?
This function is exynos_drm_crtc_dpms() and my patch is for DPMS OFF case.
That means all page flip operations should be finished already to
control DPMS off and in almost every case, there is no problem.
But if there is an issue like this lock-up, I think it should escape
this condition.
Thank you.
Best regards YJ
-Dan
Now that you are now clearing pending_flip in the error path, you
don't need the timeout, right?
There might be my missing point. Would you explain more detail?
Thank you.
Best regards YJ
-Dan
drm_vblank_off(crtc-dev, exynos_crtc-pipe);
}
@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc
*crtc,
spin_lock_irq(dev-event_lock);
drm_vblank_put(dev, exynos_crtc-pipe);
list_del(event-base.link);
+ atomic_set(exynos_crtc-pending_flip, 0);
spin_unlock_irq(dev-event_lock);
goto out;
--
1.7.9.5
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Re: [PATCH v2 04/18] video: add command mode and command mode display timing
Hi Therry On 05/21/2014 08:02 PM, Thierry Reding wrote: On Wed, May 21, 2014 at 01:42:56PM +0900, YoungJun Cho wrote: This patch is based on videomode and display_timing relevant codes. To support command mode panel, it does not need to guide its timing information to the display controller like video mode panel, but it requires signal timings to transfer video data. So this patch adds cmdmode struct, cmdmode_display_timing struct and the according helper functions to convert cmdmode_display_timing to a generic cmdmode. Can you point me to relevant documentation? I wasn't able to find it by a quick scan through the DSI specification. I'm sorry to say that there is no specific one document. I referred to several ones, CPU interface, I80 interface and DBI document(last time you said it). I think this is good to check it. [ http://cache.freescale.com/files/dsp/doc/app_note/AN4180.pdf ] And I asked panel vendor custom service centre also. Thank you. Best regards YJ Thierry -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/18] drm/exynos: use wait_event_timeout() for safety usage
Hi Daniel
Thank you for comments.
On 05/20/2014 07:02 PM, Daniel Kurtz wrote:
On Wed, May 14, 2014 at 2:26 PM, YoungJun Cho yj44@samsung.com wrote:
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
This solution looks like we aren't really handling some conditions
completely (such as panel reset?). In cases where this timeout can
occur, shouldn't we be clearing pending_flip when we detect that the
flip will never complete?
Nice catch!.
The others except pending_flip issue are done in drm_vblank_off()
instead of exynos_drm_crtc_finish_pageflip() at this case.
I'll do it for this routine and exynos_drm_crtc_page_flip() also.
There is a leak point in exynos_drm_crtc_page_flip() when
exynos_drm_crtc_mode_set_commit() is failed.
Thank you.
Best regards YJ
-Dan
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..485fa26 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,9 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (mode DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc-pending_flip_queue,
- atomic_read(exynos_crtc-pending_flip) == 0);
+ wait_event_timeout(exynos_crtc-pending_flip_queue,
+ !atomic_read(exynos_crtc-pending_flip),
+ HZ/20);
drm_vblank_off(crtc-dev, exynos_crtc-pipe);
}
--
1.7.9.5
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