On Thu, Jul 10, 2014 at 11:32:16PM +0100, Olav Haugan wrote:
On 7/9/2014 3:54 AM, Will Deacon wrote:
On Wed, Jul 09, 2014 at 02:07:38AM +0100, Olav Haugan wrote:
So how does an algorithm figure this out in both my examples? The
algorithm would have to know about both (all) bus masters and
On 7/9/2014 3:54 AM, Will Deacon wrote:
On Wed, Jul 09, 2014 at 02:07:38AM +0100, Olav Haugan wrote:
On 6/30/2014 2:52 AM, Will Deacon wrote:
On Fri, Jun 27, 2014 at 11:23:27PM +0100, Olav Haugan wrote:
Lets say I have an IOMMU with 2 masters and 2 SMRn slots with the
following stream IDs
On Wed, Jul 09, 2014 at 02:07:38AM +0100, Olav Haugan wrote:
On 6/30/2014 2:52 AM, Will Deacon wrote:
On Fri, Jun 27, 2014 at 11:23:27PM +0100, Olav Haugan wrote:
Lets say I have an IOMMU with 2 masters and 2 SMRn slots with the
following stream IDs coming from the masters:
Master 1:
On 6/30/2014 2:52 AM, Will Deacon wrote:
Hi Olav,
On Fri, Jun 27, 2014 at 11:23:27PM +0100, Olav Haugan wrote:
On 6/25/2014 2:18 AM, Will Deacon wrote:
Why can't it be dynamically detected? Whilst the StreamIDs are fixed in
hardware (from the SMMU architecture perspective), the SMRs are
Hi Olav,
On Fri, Jun 27, 2014 at 11:23:27PM +0100, Olav Haugan wrote:
On 6/25/2014 2:18 AM, Will Deacon wrote:
Why can't it be dynamically detected? Whilst the StreamIDs are fixed in
hardware (from the SMMU architecture perspective), the SMRs are completely
programmable. Why doesn't
On 6/25/2014 2:18 AM, Will Deacon wrote:
On Tue, Jun 24, 2014 at 10:35:54PM +0100, Olav Haugan wrote:
On 6/24/2014 11:11 AM, Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
On 6/24/2014 2:18 AM, Will Deacon wrote:
On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
We do describe the masked StreamID (SID) but we need to specify the mask
that the SMMU should apply to the
On Tue, Jun 24, 2014 at 10:35:54PM +0100, Olav Haugan wrote:
On 6/24/2014 11:11 AM, Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
On 6/24/2014 2:18 AM, Will Deacon wrote:
On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav Haugan wrote:
We have multiple-master
On Wednesday 25 June 2014 10:17:02 Will Deacon wrote:
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
We do describe the masked StreamID (SID) but we need to
On Wed, Jun 25, 2014 at 10:27:50AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:17:02 Will Deacon wrote:
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan
On Wednesday 25 June 2014 10:38:25 Will Deacon wrote:
On Wed, Jun 25, 2014 at 10:27:50AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:17:02 Will Deacon wrote:
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Wed, Jun 25, 2014 at 10:48:31AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:38:25 Will Deacon wrote:
On Wed, Jun 25, 2014 at 10:27:50AM +0100, Arnd Bergmann wrote:
I think the situation is a bit different here: It's less about the corner
cases for the SMMU, but about the
On Wednesday 25 June 2014 10:57:36 Will Deacon wrote:
So far, I've been avoiding the hardcoding. However, you could potentially
build a system with a small number of SMRs (compared to the number of
StreamIDs) and allocate the StreamIDs in such a way that I think the dynamic
configuration would
On Wed, Jun 25, 2014 at 11:12:13AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:57:36 Will Deacon wrote:
So far, I've been avoiding the hardcoding. However, you could potentially
build a system with a small number of SMRs (compared to the number of
StreamIDs) and allocate the
On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav Haugan wrote:
On 5/30/2014 12:06 PM, Arnd Bergmann wrote:
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
Presumably the ID would be the streamID on ARM's SMMU. How would a
master with 8 streamIDs be described? This is what Calxeda midway has
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
On 6/24/2014 2:18 AM, Will Deacon wrote:
On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav Haugan wrote:
We have multiple-master SMMUs and each master emits a variable number of
StreamIDs. However, we have to apply a mask (the ARM
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
On 6/24/2014 2:18 AM, Will Deacon wrote:
On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav Haugan wrote:
We have multiple-master SMMUs and each master emits a variable number of
On 6/24/2014 11:11 AM, Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
On 6/24/2014 2:18 AM, Will Deacon wrote:
On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav Haugan wrote:
We have multiple-master SMMUs and each master emits a variable number of
StreamIDs.
On Wednesday 18 June 2014 11:14:39 Will Deacon wrote:
On Wed, Jun 18, 2014 at 12:37:16AM +0100, Thierry Reding wrote:
- Each master has a set of fixed StreamIDs
- StreamIDs can be remastered by adding a constant offset (this could also
be used to describe RequesterID - StreamID
On Fri, Jun 20, 2014 at 04:53:08PM +0100, Arnd Bergmann wrote:
On Wednesday 18 June 2014 11:14:39 Will Deacon wrote:
On Wed, Jun 18, 2014 at 12:37:16AM +0100, Thierry Reding wrote:
- Each master has a set of fixed StreamIDs
- StreamIDs can be remastered by adding a constant offset (this
On Friday 20 June 2014 18:50:51 Will Deacon wrote:
On Fri, Jun 20, 2014 at 04:53:08PM +0100, Arnd Bergmann wrote:
On Wednesday 18 June 2014 11:14:39 Will Deacon wrote:
On Wed, Jun 18, 2014 at 12:37:16AM +0100, Thierry Reding wrote:
- Each master has a set of fixed StreamIDs
-
On 5/30/2014 12:06 PM, Arnd Bergmann wrote:
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
+IOMMU master node:
+==
+
+Devices that access memory
On Tue, Jun 17, 2014 at 03:50:25PM +0100, Stuart Yoder wrote:
I think for simple masters (i.e. those that have all their StreamIDs
under control of one driver), then setting something during attach (or
add?) based on the DT could work pretty well. The other case is when we
have masters
On Wed, Jun 18, 2014 at 12:37:16AM +0100, Thierry Reding wrote:
On Tue, Jun 17, 2014 at 01:18:11PM +0100, Will Deacon wrote:
On Tue, Jun 17, 2014 at 12:58:30PM +0100, Thierry Reding wrote:
On Mon, Jun 16, 2014 at 01:57:04PM +0100, Will Deacon wrote:
On Wed, Jun 04, 2014 at 10:12:38PM
Warren; linux-
ker...@vger.kernel.org; Marc Zyngier; Linux IOMMU; Rob Herring; Kumar
Gala; linux-te...@vger.kernel.org; Cho KyongHo; Dave P Martin; linux-arm-
ker...@lists.infradead.org
Subject: RE: [PATCH v2] devicetree: Add generic IOMMU device tree
bindings
-Original Message
On Tue, Jun 17, 2014 at 11:26:48AM +0100, Varun Sethi wrote:
The way we generally thought it would work was something like
this:
-u-boot/bootloader makes any static streamID allocation if needed,
sets a default streamID (e.g. 0x0) in device and expresses
that in the device
Subject: Re: [PATCH v2] devicetree: Add generic IOMMU device tree
bindings
On Tue, Jun 17, 2014 at 11:26:48AM +0100, Varun Sethi wrote:
The way we generally thought it would work was something like
this:
-u-boot/bootloader makes any static streamID allocation if needed,
sets
On Mon, Jun 16, 2014 at 01:57:04PM +0100, Will Deacon wrote:
On Wed, Jun 04, 2014 at 10:12:38PM +0100, Thierry Reding wrote:
On Fri, May 30, 2014 at 12:27:28PM +0100, Dave Martin wrote:
On Fri, May 30, 2014 at 08:30:08AM +0100, Thierry Reding wrote:
[...]
Arnd, can you take another
On Tue, Jun 17, 2014 at 12:58:30PM +0100, Thierry Reding wrote:
On Mon, Jun 16, 2014 at 01:57:04PM +0100, Will Deacon wrote:
On Wed, Jun 04, 2014 at 10:12:38PM +0100, Thierry Reding wrote:
It can easily be argued that if the algorithm used to remap the ID
varies, the compatibility of the
Warren; linux-ker...@vger.kernel.org; Marc
Zyngier; Linux IOMMU; Rob Herring; Kumar Gala; linux-
te...@vger.kernel.org; Cho KyongHo; Dave P Martin; linux-arm-
ker...@lists.infradead.org
Subject: RE: [PATCH v2] devicetree: Add generic IOMMU device tree
bindings
-Original Message
Herring; linux-
ker...@vger.kernel.org; Marc Zyngier; Linux IOMMU; Thierry Reding; Kumar
Gala; linux-te...@vger.kernel.org; Cho KyongHo; Dave P Martin; linux-arm-
ker...@lists.infradead.org
Subject: RE: [PATCH v2] devicetree: Add generic IOMMU device tree
bindings
-Original Message
On Tue, Jun 17, 2014 at 01:18:11PM +0100, Will Deacon wrote:
On Tue, Jun 17, 2014 at 12:58:30PM +0100, Thierry Reding wrote:
On Mon, Jun 16, 2014 at 01:57:04PM +0100, Will Deacon wrote:
On Wed, Jun 04, 2014 at 10:12:38PM +0100, Thierry Reding wrote:
It can easily be argued that if the
On Wed, Jun 04, 2014 at 10:12:38PM +0100, Thierry Reding wrote:
On Fri, May 30, 2014 at 12:27:28PM +0100, Dave Martin wrote:
On Fri, May 30, 2014 at 08:30:08AM +0100, Thierry Reding wrote:
[...]
Arnd, can you take another look at this binding and see if there's
anything else missing? If
Hi Varun,
On Thu, Jun 05, 2014 at 08:10:19PM +0100, Varun Sethi wrote:
The set of StreamIDs that can be generated by a master is fixed in the
hardware. The SMMU can then be programmed to map these incoming IDs onto
a context ID (or a set of context IDs), which are the IDs used internally
; Stephen Warren; linux-ker...@vger.kernel.org; Marc
Zyngier; Linux IOMMU; Rob Herring; Kumar Gala; linux-
te...@vger.kernel.org; Cho KyongHo; Dave P Martin; linux-arm-
ker...@lists.infradead.org; Yoder Stuart-B08248
Subject: Re: [PATCH v2] devicetree: Add generic IOMMU device tree
bindings
Hi
Hi Stuart,
On Mon, Jun 16, 2014 at 05:56:32PM +0100, Stuart Yoder wrote:
Do you have use-cases where you really need to change these mappings
dynamically?
Yes. In the case of a PCI bus-- you may not know in advance how many
PCI devices there are until you probe the bus. We have another
On Monday 16 June 2014 18:04:16 Will Deacon wrote:
On Mon, Jun 16, 2014 at 05:56:32PM +0100, Stuart Yoder wrote:
Do you have use-cases where you really need to change these mappings
dynamically?
Yes. In the case of a PCI bus-- you may not know in advance how many
PCI devices there
Campbell; Grant Grundler; Stephen Warren; linux-
ker...@vger.kernel.org; Marc Zyngier; Linux IOMMU; Rob Herring; Kumar
Gala; linux-te...@vger.kernel.org; Cho KyongHo; Dave P Martin; linux-arm-
ker...@lists.infradead.org
Subject: Re: [PATCH v2] devicetree: Add generic IOMMU device tree
bindings
Hi
On Sat, Jun 07, 2014 at 03:22:13PM +0200, Arnd Bergmann wrote:
On Saturday 07 June 2014 00:45:45 Thierry Reding wrote:
This is somewhat off-topic, but given the various concepts discussed in
this thread I'm beginning to wonder how they will be implemented.
I think it's good you raised the
On Saturday 07 June 2014 00:45:45 Thierry Reding wrote:
This is somewhat off-topic, but given the various concepts discussed in
this thread I'm beginning to wonder how they will be implemented.
I think it's good you raised the question.
The
current implementation hooks the IOMMU API into the
This is somewhat off-topic, but given the various concepts discussed in
this thread I'm beginning to wonder how they will be implemented. The
current implementation hooks the IOMMU API into the DMA mapping API, and
the way this is done is by setting a single IOMMU (or rather a set of
IOMMU
On Wednesday 04 June 2014 23:32:00 Thierry Reding wrote:
On Fri, May 30, 2014 at 09:01:19PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 12:22:32 Dave Martin wrote:
+
+Examples:
+=
+
+Single-master IOMMU:
+
+
+ iommu {
+
...@vger.kernel.org; Pawel Moll; Arnd Bergmann; Ian Campbell; Grant
Grundler; Stephen Warren; linux-ker...@vger.kernel.org; Marc Zyngier;
Linux IOMMU; Rob Herring; Kumar Gala; linux-te...@vger.kernel.org; Cho
KyongHo; Dave P Martin; linux-arm-ker...@lists.infradead.org
Subject: Re: [PATCH v2] devicetree: Add
On Sun, Jun 01, 2014 at 10:55:46AM +0100, Will Deacon wrote:
On Fri, May 30, 2014 at 08:54:37PM +0100, Arnd Bergmann wrote:
On Friday 30 May 2014 22:29:13 Hiroshi Doyu wrote:
Tegra,SMMU has a similar problem and we have used a fixed size bitmap(64
bit) to afford 64 stream IDs so that a
On Fri, May 30, 2014 at 09:54:37PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 22:29:13 Hiroshi Doyu wrote:
IIUC the original problem, a master with 8 streamIDs means something
like below, where some devices have multiple IDs but some have a
single. A sinle #address-cells cannot
On Wednesday 04 June 2014 15:44:03 Thierry Reding wrote:
Well, the iommu specific binding could allow a variable #address-cells.
That way, you just need to know the number of stream IDs for that instance
of the iommu.
That sounds fairly complicated to me. I don't see what that buys us
On Wed, Jun 04, 2014 at 02:44:03PM +0100, Thierry Reding wrote:
On Fri, May 30, 2014 at 09:54:37PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 22:29:13 Hiroshi Doyu wrote:
The disadvantage of this is that this limits the max number of streamIDs
to support. If # of streamID is
On Wednesday 04 June 2014 14:56:01 Will Deacon wrote:
On Wed, Jun 04, 2014 at 02:44:03PM +0100, Thierry Reding wrote:
On Fri, May 30, 2014 at 09:54:37PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 22:29:13 Hiroshi Doyu wrote:
The disadvantage of this is that this limits the max
On Mon, Jun 02, 2014 at 11:41:04AM +0100, Dave Martin wrote:
On Fri, May 30, 2014 at 09:49:59PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 14:31:55 Rob Herring wrote:
On Fri, May 30, 2014 at 2:06 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 30 May 2014 08:16:05 Rob Herring
On Wed, Jun 04, 2014 at 03:01:15PM +0100, Arnd Bergmann wrote:
On Wednesday 04 June 2014 14:56:01 Will Deacon wrote:
On Wed, Jun 04, 2014 at 02:44:03PM +0100, Thierry Reding wrote:
On Fri, May 30, 2014 at 09:54:37PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 22:29:13 Hiroshi Doyu
On Wed, Jun 04, 2014 at 03:35:10PM +0100, Thierry Reding wrote:
On Mon, Jun 02, 2014 at 11:41:04AM +0100, Dave Martin wrote:
In the strictest sense, no.
But for a large set of sane configurations, this probably works.
Small sets of randomly-assigned IDs can just be enumerated one by
On Wed, Jun 04, 2014 at 05:41:32PM +0100, Will Deacon wrote:
On Wed, Jun 04, 2014 at 03:35:10PM +0100, Thierry Reding wrote:
On Mon, Jun 02, 2014 at 11:41:04AM +0100, Dave Martin wrote:
In the strictest sense, no.
But for a large set of sane configurations, this probably works.
On Fri, May 30, 2014 at 12:27:28PM +0100, Dave Martin wrote:
On Fri, May 30, 2014 at 08:30:08AM +0100, Thierry Reding wrote:
[...]
Arnd, can you take another look at this binding and see if there's
anything else missing? If not I'll go through the document again and
update all
On Fri, May 30, 2014 at 09:01:19PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 12:22:32 Dave Martin wrote:
+
+Examples:
+=
+
+Single-master IOMMU:
+
+
+ iommu {
+ #address-cells = 0;
+ #size-cells = 0;
+ };
+
On Fri, May 30, 2014 at 09:49:59PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 14:31:55 Rob Herring wrote:
On Fri, May 30, 2014 at 2:06 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
On Fri, May 30, 2014 at 09:11:07PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 12:27:28 Dave Martin wrote:
On Fri, May 30, 2014 at 08:30:08AM +0100, Thierry Reding wrote:
On Thu, May 29, 2014 at 09:52:22AM -0600, Stephen Warren wrote:
On 05/23/2014 02:36 PM, Thierry Reding wrote:
On Fri, May 30, 2014 at 09:01:19PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 12:22:32 Dave Martin wrote:
+
+Examples:
+=
+
+Single-master IOMMU:
+
+
+ iommu {
+ #address-cells = 0;
+ #size-cells = 0;
+ };
+
On Fri, May 30, 2014 at 08:54:37PM +0100, Arnd Bergmann wrote:
On Friday 30 May 2014 22:29:13 Hiroshi Doyu wrote:
Tegra,SMMU has a similar problem and we have used a fixed size bitmap(64
bit) to afford 64 stream IDs so that a single device can hold multiple
IDs. If we apply the same bitmap
On Thu, May 29, 2014 at 09:52:22AM -0600, Stephen Warren wrote:
On 05/23/2014 02:36 PM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This commit introduces a generic device tree binding for IOMMU devices.
Only a very minimal subset is described here, but it is enough to
On Fri, May 23, 2014 at 10:36:35PM +0200, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This commit introduces a generic device tree binding for IOMMU devices.
Only a very minimal subset is described here, but it is enough to cover
the requirements of both the Exynos System
On Fri, May 30, 2014 at 08:30:08AM +0100, Thierry Reding wrote:
On Thu, May 29, 2014 at 09:52:22AM -0600, Stephen Warren wrote:
On 05/23/2014 02:36 PM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This commit introduces a generic device tree binding for IOMMU devices.
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
This commit introduces a generic device tree binding for IOMMU devices.
Only a very minimal subset is described here, but it is enough to cover
the requirements of both the
On Friday 30 May 2014 12:22:32 Dave Martin wrote:
+
+Examples:
+=
+
+Single-master IOMMU:
+
+
+ iommu {
+ #address-cells = 0;
+ #size-cells = 0;
+ };
+
+ master {
+ iommus = /iommu;
+ };
+
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
+IOMMU master node:
+==
+
+Devices that access memory through an IOMMU are called masters. A device
On Friday 30 May 2014 12:27:28 Dave Martin wrote:
On Fri, May 30, 2014 at 08:30:08AM +0100, Thierry Reding wrote:
On Thu, May 29, 2014 at 09:52:22AM -0600, Stephen Warren wrote:
On 05/23/2014 02:36 PM, Thierry Reding wrote:
I think this is a mistake. address-cells/size-cells are for
Arnd Bergmann a...@arndb.de writes:
+Multiple-master IOMMU:
+--
+
+ iommu {
+ /* the specifier represents the ID of the master */
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ master {
+
On Fri, May 30, 2014 at 2:06 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
+IOMMU master node:
+==
+
On Friday 30 May 2014 14:31:55 Rob Herring wrote:
On Fri, May 30, 2014 at 2:06 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
On Friday 30 May 2014 22:29:13 Hiroshi Doyu wrote:
IIUC the original problem, a master with 8 streamIDs means something
like below, where some devices have multiple IDs but some have a
single. A sinle #address-cells cannot afford those 2 masters at once.
iommu {
/*
On 05/23/2014 02:36 PM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This commit introduces a generic device tree binding for IOMMU devices.
Only a very minimal subset is described here, but it is enough to cover
the requirements of both the Exynos System MMU and Tegra SMMU
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